MSP Debuggers: User's Guide

User's Guide
SLAU647H – July 2015 – Revised April 2017
MSP Debuggers
This manual describes the use and the features of the debug probes for MSP430™ and SimpleLink™
MSP432™ microcontrollers (MCUs). It includes information about the debugger probe hardware and
software. It documents frequently asked questions on how to enable and disable certain features. It shows
the differences between the debug probes and offers a guide on how to identify the specific version of the
debug probe hardware.
Contents
1 Introduction ................................................................................................................... 3
2 MSP Debug Probe Overview ............................................................................................... 4
3 Hardware Identification ...................................................................................................... 6
4 Hardware Installation ........................................................................................................ 8
5 Debug Probes Hardware and Software ................................................................................. 12
List of Figures
1 eZ-FET Windows Enumeration ............................................................................................ 6
2 eZ-FET Emulation IP ........................................................................................................ 6
3 eZ-FET Lite Emulation IP ................................................................................................... 6
4 eZ430 Emulation IP ......................................................................................................... 7
5 eZ430 Windows Enumeration .............................................................................................. 7
6 MSP Flasher Driver Install Notification .................................................................................. 10
7 CCS Cloud Agent Installation............................................................................................. 11
8 Successful CCS Cloud Agent Installation ............................................................................... 11
9 MSP Ecosystem ............................................................................................................ 12
10 MSP-FET Top View ........................................................................................................ 15
11 MSP-FET Bottom View .................................................................................................... 15
12 MSP-FET 14-Pin JTAG Connector ...................................................................................... 18
13 Open MSP-FET Cover .................................................................................................... 20
14 Jumper J5 ................................................................................................................... 20
15 Recovery Confirmation .................................................................................................... 21
16 MSP-FET USB Debugger, Schematic (1 of 5) ......................................................................... 22
21 MSP-FET USB Debugger, PCB (Top) .................................................................................. 26
22 MSP-FET USB Debugger, PCB (Bottom)............................................................................... 26
23 MSP-FET430UIF Version 1.4a Top and Bottom Views ............................................................... 28
24 MSP-FET430UIF Version 1.3 Top and Bottom Views ................................................................ 28
25 MSP-FET430UIF 14-Pin JTAG Connector ............................................................................. 29
26 MSP-FET430UIF USB Interface, Schematic (1 of 4) .................................................................. 31
SLAU647H – July 2015 – Revised April 2017 MSP Debuggers 1

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30 MSP-FET430UIF USB Interface, PCB .................................................................................. 35
31 eZ-FET and eZ-FET Lite (Top View) .................................................................................... 36
32 eZ-FET Rev1.3 (Top View) ............................................................................................... 36
33 eZ-FET or eZ-FET Lite Debug Connector .............................................................................. 38
34 MSP-FET to LaunchPad Development Kit Pin Assignments ......................................................... 39
35 MSP-FET to LaunchPad Wiring Diagram ............................................................................... 39
36 eZ-FET Schematic (USB Connection)................................................................................... 40
37 eZ-FET Schematic (Emulation MCU).................................................................................... 41
38 eZ-FET Schematic DCDC (No eZ-FET Lite) ........................................................................... 42
39 eZ430 Emulation ........................................................................................................... 43
40 eZ430 Debug Connector on MSP-EXP430G2 LaunchPad ........................................................... 44
41 eZ430 Schematic (Emulation MCU) ..................................................................................... 45
42 eZ430 Schematic (USB Connection) .................................................................................... 46
43 MSP-FET430PIF ........................................................................................................... 47
44 MSP-FET430PIF FET Interface Module, Schematic .................................................................. 48
45 MSP-FET430PIF FET Interface Module, PCB ......................................................................... 49
List of Tables
1 Debug Probes Features and Device Compatibility ...................................................................... 4
2 MSP-FET Backchannel UART Implementation ........................................................................ 16
3 MSP-FET Backchannel UART Activation Commands ................................................................ 17
4 MSP-FET MSP Target BSL Activation Commands.................................................................... 17
5 MSP-FET LED Signals .................................................................................................... 18
6 MSP-FET Pin States ....................................................................................................... 19
7 MSP-FET430UIF LED Signals ........................................................................................... 29
8 MSP-FET430UIF Pin States .............................................................................................. 30
9 eZ-FET and eZ-FET Lite Backchannel UART Implementation ...................................................... 37
10 eZ-FET and eZ-FET Lite Backchannel UART Activation Commands ............................................... 38
11 eZ-FET LED Signals ....................................................................................................... 38
12 eZ-FET and eZ-FET Lite Pin States ..................................................................................... 39
13 eZ430 Backchannel UART Implementation ............................................................................ 44
14 eZ430 Pin States ........................................................................................................... 44
Trademarks
MSP430, SimpleLink, MSP432, Code Composer Studio, E2E, EnergyTrace are trademarks of Texas
Instruments.
ARM is a registered trademark of ARM Limited.
OS X is a registered trademark of Apple, Inc.
Ubuntu is a trademark of Canonical Group Ltd.
IAR Embedded Workbench is a registered trademark of IAR Systems.
Linux is a registered trademark of Linus Torvalds.
Windows is a registered trademark of Micosoft Corporation.
CentOS is a trademark of Red Hat, Inc.
All other trademarks are the property of their respective owners.
2 MSP Debuggers SLAU647H – July 2015 – Revised April 2017

www.ti.com Introduction
1 Introduction
1.1 Related Documentation From Texas Instruments
MSP430™ Hardware Tools User's Guide

IAR Embedded Workbench™ Version 3+ for MSP430™ User's Guide
Advanced Debugging Using the Enhanced Emulation Module (EEM) With Code Composer Studio™
Version 6
MSP430™ Programming With the Bootloader (BSL)
MSP430™ Programming With the JTAG Interface
1.2 Terms and Abbreviations
Term Definition
BSL Bootloader
CCS Code Composer Studio™ development tool for MSP430
CDC Communications device class
CPU Central processing unit
CRC Cyclic redundancy check
CTS Clear to send
FET Flash emulation tool
I2C Inter-Integrated Circuit 2-wire communication bus
IAR EW430 IAR Embedded Workbench® development tool for MSP430
JTAG Joint Test Action Group
JTAG 4-wire 4-wire JTAG protocol communication
MCLK Master clock
MSP Mixed signal processor
MSP-FET MSP debug probe
MSP-FET430 UIF MSP debug probe
Dynamic library (Windows®), shared object (Linux®), or dy library (OS X®) that offers functions to access and
MSPDebugStack
debug MSP430 devices using an MSP debug probe
PC Personal computer
RTS Request to send
RX Receive data
SBW Spy-Bi-Wire (2-wire JTAG protocol) communication
TX Transmit data
UART Universal asynchronous receiver/transmitter
UIF USB interface to debug and access MSP derivatives
USB Universal serial bus
1.3 If You Need Assistance

Support for the MSP microcontrollers and the development tools is provided by the TI Product Information
Center (PIC). Contact information for the PIC can be found on the TI website. The TI E2E™ Community
support forums for the MSP microcontrollers also provide open interaction and support from a community
of peer engineers, TI engineers, and other experts. Additional device-specific information can be found on
the MSP website.

MSP Debug Probe Overview www.ti.com
2 MSP Debug Probe Overview

Table 1 is an overview of the capabilities and features for the available MSP debug probes.
CAUTION
Never disconnect the JTAG or emulator USB cable during an active debug
session. Always terminate a running debug session properly, by clicking on the
"Terminate" icon, before disconnecting the target device.
Table 1. Debug Probes Features and Device Compatibility (1) (2) (3)
LaunchPad (MSP-EXP430G2)
eZ-FET Lite Emulation IP

MSP-WDSxx Metawatch
eZ-FET Emulation IP
MSP-EXP430FR5739
MSP-EXP430F5529
MSP-FET430UIF
MSP-FET430PIF
Feature and MSP430 Device Support
eZ430-Chronos
eZ430-RF2500
eZ430-RF2480
eZ430-RF2560
eZ430-F2013
MSP-FET
Supports all programmable MSP430 and
✓ ✓ ✓ ✓ ✓
CC430 devices
Supports only F20xx, G2x01, G2x11,
✓
G2x21, G2x31
Supports F20xx, F21x2, F22xx, G2x01,
✓
G2x11, G2x21, G2x31, G2x53
Supports F20xx, F21x2, F22xx, G2x01,
✓ ✓
G2x11, G2x21, G2x31
Supports F5438, F5438A ✓
Supports BT5190, F5438A ✓ ✓
Supports only F552x ✓
Supports FR57xx, F5638, F6638 ✓
Supports only CC430F613x ✓
Supports MSP432Pxx ✓
Allows JTAG access protection
✓ ✓
(Fuse Blow) (4)
Adjustable target supply voltage ✓ ✓
Fixed 2.8-V target supply voltage ✓
Fixed 3.3-V target supply voltage ✓ ✓
Fixed 3.6-V target supply voltage ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
4-wire JTAG ✓ ✓ ✓
(5)
2-wire JTAG ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
BSL tool or mode ✓
Backchannel UART ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
Supported by CCS for Windows ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
Supported by CCS for Linux ✓ ✓ ✓ ✓
Supported by CCS for OS X ✓ ✓ ✓ ✓
(1)
The MSP-FET430PIF is for legacy device support only. This emulation tool does not support any devices released after 2011.
(2)
See Section 3.1 to identify the hardware.
(3)
The eZ-FET Emulation IP and eZ-FET Lite Emulation IP are used as the onboard emulation for the MSP LaunchPad tools.
(4)
See Section 5.5 for more information.
(5)
The 2-wire JTAG debug interface is also referred to as Spy-Bi-Wire (SBW) interface.

www.ti.com MSP Debug Probe Overview
Table 1. Debug Probes Features and Device Compatibility (1) (2) (3) (continued)
LaunchPad (MSP-EXP430G2)
eZ-FET Lite Emulation IP

MSP-WDSxx Metawatch
eZ-FET Emulation IP
MSP-EXP430FR5739
MSP-EXP430F5529
MSP-FET430UIF
MSP-FET430PIF
Feature and MSP430 Device Support
eZ430-Chronos
eZ430-RF2500
eZ430-RF2480
eZ430-RF2560
eZ430-F2013
MSP-FET
Supported by IAR ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
EnergyTrace™, EnergyTrace++ ✓ ✓

Hardware Identification www.ti.com
3 Hardware Identification
3.1 How to Determine If Your Hardware is Based on eZ-FET or eZ-FET Lite

• Check the installed tool drivers by using the Windows Device Manager. eZ-FET tools enumerate as
CDC "MSP Debug Interface" and CDC "MSP Application UART1" devices (see Figure 1).
• Check the Experimenter Board or LaunchPad emulation section to find out if it is based on an eZ-FET
tool. If it is based on an MSP430F5528 device, it is an eZ-FET tool.
• There is a small print on the silkscreen that indicates eZ-FET or eZ-FET Lite (see Figure 2 and
Figure 3).
Figure 1. eZ-FET Windows Enumeration
Figure 2. eZ-FET Emulation IP
Figure 3. eZ-FET Lite Emulation IP

www.ti.com Hardware Identification
3.2 How to Determine If Your Hardware is Based on eZ430

• Check the installed tool drivers by using the Windows Device Manager (see Figure 5). eZ430 tools
enumerate as HID (Debugger port) and CDC (Backchannel UART) devices.
• Check the Experimenter Board to find out if it is based on an eZ430 tool (see Figure 4). If it is based
on an MSP430F1612 and a TUSB3410, it is an eZ430 tool.
Figure 4. eZ430 Emulation IP
Figure 5. eZ430 Windows Enumeration
3.3 Signal Connections for In-System Programming and Debugging

For details about the hardware connections of all debug probes see the "Signal Connections for In-System
Programming and Debugging" section of the MSP430 Hardware Tools User's Guide.
3.4 Using the Power Supply Feature of the eZ-FET and eZ-FET Lite
The eZ-FET and the eZ-FET Lite only support a fixed voltage power supply. The maximum supply current
is 75 mA. For more details, see the specific LaunchPad or experimenter board user's guide.
NOTE: These debug probes do not support externally powering of the device while debugging – if
an external voltage is needed for stand-alone testing, the eZ-FET emulation section should
not be connected through USB. If both external power and the USB power are connected,
there could be a conflict that can damage the device.
3.5 Using the Power Supply Feature of the MSP-FET430UIF and MSP-FET
All MSP debug probes can supply targets with up to 100 mA through pin 2 of the 14-pin JTAG connector.
NOTE: The target should not consume more than 60 mA at peak current, as it may violate the USB
specification. Details can found on www.USB.org.
Example: If the target board has a capacitor on the VCC line with a capacity of more than 10 µF, it may
cause an inrush current during capacitor charging that may exceed 60 mA. In this case, the current should
be limited by the design of the target board, or an external power supply should be used.

Hardware Installation www.ti.com
Target VCC is selectable in a range between 1.8 V and 3.6 V in steps of 0.1 V.
Alternatively, the target can be supplied externally. In this case, the external voltage should be connected
to pin 4 of the 14-pin JTAG connector. MSP-FET tools adjusts the level of the JTAG signals to
automatically match the external VCC.
NOTE: Only pin 2 (MSP-FET tool supplies target) or pin 4 (target is externally supplied) must be
connected. Both connections are not supported at the same time.
Even if an external supply powers the target device on the target socket module and any
user circuitry connected to the target socket module, the MSP-FET tool continues to be
powered from the PC through the USB interface.
NOTE: MSP-FET430PIF only

The PC parallel ports with a connected MSP-FET430PIF can source a maximum current of
25 mA. Because of the ultra-low-power requirement of the MSP430, a stand-alone MSP430
does not exceed the provided current. However, if additional circuits are added, the current
limit could be exceeded. In this case, the MSP430 must be supplied externally.
4 Hardware Installation
This section describes how to install the drivers for all MSP debug probes. The drivers are needed to
enable the IDE (integrated development environment) to use the debug probe that is connected to the
system. There are four different ways to install the drivers.
1. CCS desktop: During the CCS setup, all MSP debug probe drivers are installed for all supported
operation systems.
2. CCS cloud: The automatic driver installer is included in the TI Cloud Agent application, which must be
downloaded when connecting a local MSP debug probe to CCS cloud.
3. Stand-alone driver installer: The stand-alone driver installer is available only for Windows. It installs all
MSP debug probe drivers.
4. Using another supported IDE such as IAR EW430 or the MSP-Flasher: During the setup, all MSP
debug probe drivers are installed.
4.1 MSP-FET430PIF
The MSP-FET430PIF has the following system requirements:
It supports only Windows XP with IAR EW430 version 5.xx.x and Code Composer Studio version 5.x.x. No
new development is scheduled to support MSP-FET430PIF.
Follow these steps to install the hardware for the MSP-FET430PIF tool:
1. Use the 25-pin ribbon cable to connect the debugger interface module to the parallel port of the PC.
The necessary driver for accessing the PC parallel port is installed automatically during CCS or IAR
Embedded Workbench installation. Note that a restart is required after the CCS or IAR Embedded
Workbench installation.
2. Use the 14-pin ribbon cable to connect the parallel-port debug interface to a target board which
contains the target MSP430 device.
4.2 MSP-FET430UIF, MSP-FET, eZ-FET, and eZ-FET Lite
NOTE: The built-in DC-DC converter of the MSP-FET and eZ-FET emulators causes a load-
dependent amount of ripple on the output voltage (fripple = 1 kHz to 50 kHz, Vrms_ripple = 5 mV to
50 mV), which might affect sensitive analog and RF circuits that are supplied by the
emulator. For such sensitive circuits, TI recommends temporarily increasing the amount of
power supply decoupling used during development, using an emulator with an integrated
linear regulator (MSP-FET430UIF or eZ-FET430), or using a separate bench supply.

www.ti.com Hardware Installation
Installation steps for the MSP-FET430UIF, MSP-FET, eZ-FET or eZ-FET Lite:

1. Install the IDE (TI CCS or IAR EW430) before connecting the debug probe to the PC. During IDE
installation, the USB drivers for the debug probes are installed automatically. Make sure to use the
latest IDE version; older versions might install USB drivers that do not recognize the connected debug
probe.
2. Connect the debug probe to a USB port on the PC using the provided USB cable.
3. The following procedure applies to operation under Windows:
(a) After connecting to the PC, the debug probe should be recognized automatically, as the USB
device driver has been already installed together with the IDE.
(b) However, if the driver is not automatically detected, the "Found New Hardware wizard" starts.
Follow the instructions and point the wizard to the driver files.
The default location for CCS is: c:\ti\ccsv6\ccs_base\emulation\drivers\msp430\USB_CDC.
The default location for IAR Embedded Workbench is: <Installation Root>\Embedded Workbench
x.x\430\drivers\<Win_OS>.
4. The following procedure applies to operation under Linux:
• Installation as root
(a) If installing TI CCS as root, make sure that the debug probe is not connected to the computer
during installation.
(b) If you start installation with the debug probe connected to the computer, disconnect the probe
and reconnect after installation finishes.
• Installation as user
(a) If installing TI CCS without root access, install the debug probe UDEV rules manually after the
CCS TI installation has finished.
(b) Make sure that the debug probe is disconnected from the computer during this step.
(c) Open the shell and go to: <CSS installation directory>/ccsv7/install_scripts.sh
(d) Execute msp430uif_install.sh as sudo.
(e) Connect the debug probe and make sure that the debug probe is detected as other than
"modem". Use the dmseg command to check the system log.
(f) The debug probe is ready for use.
5. After connecting the debug probe to a PC, the probe performs a self-test. If the self-test passes, the
green LED stays on. For a complete list of LED signals, see the LED Signals section of each debug
probe in Section 5.6 through Section 5.8.
6. Connect the debug probe with the target board using the 14-pin ribbon cable.
7. When using a target socket board, make sure that the MSP430 device is properly inserted in the
socket and that pin 1 of the device (indicated with a circular indentation on the top surface) aligns with
the "1" mark on the PCB.
NOTE: To use the debug probe without an IDE, install the stand-alone driver package. The stand-
alone driver installer can be found at www.ti.com/mspds under the heading MSPDS-USB-
DRIVERS.
4.3 eZ430-Based Experimenter Boards and LaunchPad Kits

For driver installation on a Windows operating system, follow the steps in Section 4.2.
NOTE: eZ430-tools are not supported on USB3.0 ports. eZ430 tools are supported on Windows
operating systems only—Linux and OS X are not supported.

Hardware Installation www.ti.com
4.4 Hardware Installation Using the MSP Flasher

MSP Flasher is an open-source shell-based interface for programming any MSP430 device through a
MSP Debug Stack and provides the most common functions on the command line. MSP Flasher can be
used to download binary files (.txt or .hex) directly to the MSP430 memory without the need for an IDE like
CCS or IAR. It can also be used to extract firmware directly from a device, set hardware breakpoints, and
lock JTAG access permanently.
MSP Flasher supports the following operating systems:
• Windows 10 32-bit or 64-bit
• Windows XP 32-bit or 64-bit
• Ubuntu™ 32-bit or 64-bit
• OS X 64-bit
Installation steps for the MSP-FET430UIF, MSP-FET, eZ-FET or eZ-FET Lite:
1. After successfully downloading and executing the MSP Flasher installer, it prompts you to execute the
stand-alone driver installer for the MSP debug probes.
Figure 6. MSP Flasher Driver Install Notification
2. Follow the steps given by the stand-alone driver installer for debug probe driver installation.
3. After successful driver installation, connect the debug probe to a USB port on the PC using the
provided USB cable.
4. After connecting the debug probe to a PC, it performs a self-test. If the self-test passes, the green LED
stays on. For a complete list of LED signals, see the LED Signals section of every debug probe in
Section 5.6 through Section 5.8.
5. Connect the debug probe with the target board using the 14-pin ribbon cable.
6. When using a target socket board, make sure that the MSP430 device is properly inserted in the
socket and that its pin 1 (indicated with a circular indentation on the top surface) aligns with the "1"
mark on the PCB.

www.ti.com Hardware Installation
4.5 Hardware Installation Using CCS Cloud

CCS Cloud is web-based IDE that allows you to create, edit, and build CCS and Energia projects. After a
project is successfully built, it can be downloaded and run on the connected LaunchPad or any other
debug probe. Basic debugging features, like setting breakpoints or viewing values of target variables are
now supported.
CCS Cloud can be used with the local debug probe connected to the PC through USB. To support this
configuration, install the "CCS Cloud browser extension", and download and install the "TI Cloud Agent
Application". For more details, see the CCS cloud documentation at
processors.wiki.ti.com/index.php/TI_Cloud_Agent.
Figure 7. CCS Cloud Agent Installation
Figure 8. Successful CCS Cloud Agent Installation
After the successful Agent installation, download the application by clicking the Flash or Debug button in
CCS Cloud.

Debug Probes Hardware and Software www.ti.com
5 Debug Probes Hardware and Software

This section includes all specifications and features of all MSP debug probes. The debug probe hardware
and different debug mode configuration and setting are descried.
Figure 9 is an overview of the MSP ecosystem showing the relations between IDE and debug probe and
the MSP device itself.
Figure 9. MSP Ecosystem

www.ti.com Debug Probes Hardware and Software
5.1 MSPDebugStack
The MSPDebugStack is the host side interface to all MSP debug probes. It is a library for controlling and
debugging Texas Instruments MSP ultra-low power microcontrollers during software development phase.
For this purpose the MSP microcontroller is controlled by the MSPDebugStack using the MSP device's
JTAG interface. The MSPDebugStack provides device control (for example, run and stop), memory
programming and debugging functionality (for example, breakpoints).
The MSPDebugStack supports these operating systems:
• Ubuntu 32-bit or 64-bit
• CentOS™ 6 64-bit
• CentOS 7 64-bit
• OS X 64-bit
The debug probe firmware for all field updatable tools is included in the MSPDebugStack. It automatically
detects if an update of the debug probe is required.
For more details and information see www.ti.com/mspds.
5.2 Ultra-Low-Power (ULP) Debug Support

ULP debug support enables users to debug in the low-power modes that are used in their application
software.
If this option is enabled during an active debug session in IAR EW430 or Code Composer studio, the
target MSP430 device enters the low-power modes. Wake-up times can be measured on F5xx, F6xx,
FR5xx, and FR6xx devices. For some MSP430 devices, special debug features are disabled in this mode;
for example, setting breakpoints (hardware and software) while device is running in ULP mode.
NOTE: When debugging with EnergyTrace++ active, this mode must be used.
NOTE: Measured currents might be slightly higher than in stand-alone mode (EnergyTrace) due to
the active debugger connection.
For more details and information, see the MSP430 Ultra-Low-Power LPMx.5 Mode section of
the IAR Embedded Workbench Version 3+ for MSP430 User's Guide and Code Composer
Studio v6.1 for MSP430 User's Guide.
5.3 EnergyTrace™ Technology

EnergyTrace technology is an energy-based code analysis tool that measures and displays the energy
profile of an application, which helps to optimize it for ultra-low power consumption.
MSP devices with built-in EnergyTrace+[CPU State]+[Peripheral States] (or in short EnergyTrace++)
technology allow real-time monitoring of many internal device states while user program code executes.
EnergyTrace++ technology is supported on selected MSP devices and debuggers (see Table 1).
EnergyTrace mode (without the "++") is a fundamental part of EnergyTrace technology and enables
analog energy measurement to determine the energy consumption of an application but does not correlate
it to internal device information. The EnergyTrace mode is available for all MSP devices with selected
debuggers, including CCS (see Table 1).
For more details about EnergyTrace technology, visit www.ti.com/tool/energytrace.

5.4 Unlimited Software Breakpoints in Flash, FRAM, and RAM

All MSP430 debug tools support the use of software breakpoints in Flash, FRAM, and RAM. Software
breakpoints let the user set an unlimited number of breakpoints during an active debug session.
Without software breakpoints enabled, the number of breakpoints that can be set is limited to the number
of hardware breakpoints available by the specific MSP MCU. All MSP debug tools prefer the use of
hardware breakpoints as much as possible. However, if the MSP breakpoint logic runs out of hardware
breakpoints, software breakpoints are used automatically (if enabled in the IDE).
NOTE: When the debug session is closed, all software breakpoints are erased and the original
memory content is restored.
For more details about the software breakpoints and their IDE-specific use, see the
"Breakpoint Types" section in AR Embedded Workbench Version 3+ for MSP430 User's
Guide and Code Composer Studio v6.1 for MSP430 User's Guide.
For a practical example of different breakpoint types, see Advanced Debugging Using the
Enhanced Emulation Module (EEM) With Code Composer Studio Version 6.
5.5 JTAG Access Protection (Fuse Blow)

Different MSP430 devices implement different methods to prevent JTAG debug access to the MSP430
target device.
NOTE: Only the MSP-FET and the MSP-FET430UIF support JTAG access protection to disable
JTAG access.
For more details how the JTAG access protection mechanism is implemented see the "JTAG
Access Protection" section in MSP430 Programming With the JTAG Interface.
JTAG fuse
• Available on 1xx, 2xx, and 4xx families (except FRxx and I20xx devices)
• Applying a high voltage to test the TEST pin of the MSP430 target device blows an actual physical
polyfuse and disables the JTAG interface.
JTAG lock without password (eFuse/"soft" fuse)
• Available on 5xx, 6xx, and FRxx families
• A certain lock pattern is written into the MSP430 target memory to disable the JTAG interface.
JTAG lock with password
• Available only FRxx families
• A user-defined password can disable JTAG access to the MSP430 target device.
• Using CCS, EW430, or the MSP Flasher, applying the configured password to the MSP430 target
restores JTAG access
Memory protection by custom startup code (SUC)
• Available on only the i20xx family (for example, the MSP430i2040 device)
• Custom startup code can enable or disable JTAG access to the MSP430i20xx target device.
DAP (Debug Access Port) lock
• Available on MSP432P401x family – Locks JTAG/SWD connection to MSP432P401x device
• Execute a Factory Reset to unlock the Debug Access port.

5.6 MSP-FET Stand-Alone Debug Probe

The MSP-FET (see Figure 10 and Figure 11) is a powerful debug probe for application development
supporting all MSP430 microcontrollers.
The MSP-FET provides a USB interface to program and debug the MSP430 devices in-system through
the JTAG interface or the pin-saving Spy-Bi-Wire (2-wire JTAG) protocol. Furthermore, the USB interface
can be used for Backchannel UART and MSP target BSL communication. UART BSL and I2C BSL
communication modes are supported.
The MSP-FET development tool supports development with all MSP430 devices and is designed for use
with PCBs that contain MSP430 devices; for example, the MSP430 target socket boards.
Figure 10. MSP-FET Top View Figure 11. MSP-FET Bottom View
5.6.1 General Features

The MSP-FET debug probe includes the following features:
• MSP-FET is supported since:
– CCS v6.0.0
– IAR EW430 v5.60.7 and v6.10.1
• Operating systems: OS X, Linux, Windows
• Software configurable supply voltage between 1.8 V and 3.6 V at 100 mA
NOTE: The MSP-FET supply voltage is generated by an DC/DC converter, which creates a voltage
ripple on the target supply line. This ripple can affect the performance of the analog modules
of the MSP device (for example, the ADC and the DAC). If necessary, connect an low-ripple
external power supply to the target application.
• External voltage detection

• Supports JTAG security fuse blow to disable debugging
• Supports all MSP430 boards with JTAG header
• Supports both JTAG and Spy-Bi-Wire (2-wire JTAG) debug protocols
• EnergyTrace Technology (MSP430 and MSP432 devices), EnergyTrace+ (MSP432 devices only), and
EnergyTrace++ (MSP430 devices only) support
• EnergyTrace technology accuracy
– Current < 25 µA: Error range = ±500 nA
– Current ≥ 25 µA and ≤ 75 mA: Error range = ±2%
– Current > 75 mA: Error range = ±4%
• Software breakpoints in flash, FRAM, and RAM
• MSPDS application backchannel UART included

• Target BSL communication mode available

• Flash and FRAM programming support
• Debug probe firmware field update is supported (4)
• Supports all MSP432P401x boards with ARM® 20-pin and 10-pin connectors using the MSP432
Adapter for MSP-FET
• Supports JTAG and SWD MSP432 debug protocols
5.6.2 Backchannel UART

The MSP-FET supports the Backchannel UART functionality only when using an MSPDebugStack
v3.4.1.0 or higher for the MSP-FET connection.
The baud rates that are supported depend on the target configuration and the debug settings. Table 2
shows which baud rates are supported with certain configuration combinations.
✓ means that the corresponding baud rate is supported without any data loss with the specified
combination of settings.
✗ means that the corresponding baud rate is not supported (data loss is expected) with the specified
(4)
Enable new device support by in field firmware updates
Table 2. MSP-FET Backchannel UART Implementation

Target MCLK
1 MHz 8 MHz 1 MHz 8 MHz
Frequency:
Debugger: Active Inactive
Flow Control: No Yes No Yes No Yes No Yes
4800 baud ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
9600 baud ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
19200 baud ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
28800 baud ✗ ✓ ✓ ✓ ✓ ✓ ✓ ✓
38400 baud ✗ ✓ ✗ ✓ ✗ ✓ ✗ ✓
57600 baud ✗ ✓ ✗ ✓ ✗ ✓ ✗ ✓
115200 baud ✗ ✗ ✗ ✓ ✗ ✗ ✗ ✓
5.6.2.1 UART Backchannel Activation Commands

The MSP-FET supports two different Backchannel UART modes, one with flow control and one without.
The different modes can be selected by opening the corresponding COM port with a dedicated baud rate.
See Table 3 for the specific baud rates for each command.
NOTE: The baud rates used by these activation commands cannot be used for communication.
NOTE: The Backchannel UART is disabled until the COM port is opened with a valid baud rate.
If none of the specified commands are transferred before setting the communication baud rate,
communication starts with the default settings: 3.3-V target VCC, no flow control mechanism.

Table 3. MSP-FET Backchannel UART Activation Commands

Baud Rate Command
9620 Set all backchannel UART pins to high impedance – no current flow into target device
9621 Configure backchannel UART communication without handshake (default start behavior)
9622 Configure backchannel UART communication with handshake
Voltage configuration command. When this command is received, target VCC is set to 3.3 V. After target VCC is
9623
configured, it is switched through to the target device.
5.6.3 Target BSL Connection and BSL-Scripter Support

The MSP-FET can be used for communication with the target device bootloader (BSL) through the I2C and
UART protocols. The activation of the different protocols is equivalent to the MSP-FET backchannel
UART. See Table 4 for command details.
The BSL-Scripter software implements support for these activation commands and performs the correct
sequence according to the communication interface (UART, I2C) that is specified in the script.
In MSP-FET BSL communication mode, flow control is not available, because this is not supported by the
MSP target device BSL.
UART BSL: The MSP-FET BSL UART mode supports the following baud rates: 9600, 14400, 19200,
28800, 38400, 56000, 57600, and 115200. For the BSL UART, 8 + 1 + even parity is used.
I2C BSL: The MSP-FET is always the I2C master, and the target device BSL is always the I2C slave. 7-bit
I2C addressing mode is used with a fixed I2C slave address of 0x48.
NOTE: If the MSP-FET is configured to support BSL communication, debugger functionality is

disabled. To switch to debugger mode, either perform a power cycle (unplug the USB cable)
or configure the baud rate to 8001. The BSL mode is disabled until sending a BSL entry
baud rate command.
NOTE: MSP-FET BSL I2C pullup resistors must not exceed 2-kΩ resistance.
The maximum I2C clock rate is 55 kHz.
Table 4. MSP-FET MSP Target BSL Activation Commands

Baud Rate Command
9620 Set all UART or I2C pins to high impedance – no current flow into target device
9601 BSL entry sequence and power up 3.3 V (UART BSL) – debugger is disabled
100000 or 100001 BSL entry sequence and power up 3.3 V (I2C BSL) – debugger is disabled
400000 or 400001 BSL entry sequence and power up 3.3 V (I2C BSL) – debugger is disabled
9623 Power up 3.3 V
8001 Activate debugger
NOTE: The MSP-FET I2C interface is a software I2C implementation, which always runs with a
speed of approximately 55 kHz. The four different speed configurations are supported for
compatibility purposes with BSL-Scripter and the BSL-Rocket.

5.6.4 LED Signals

The MSP-FET shows its operating states using two LEDs, one green and one red. Table 5 lists all
available operation modes. An or icon indicates that the LED is off, an or icon indicates that
the LED is on, and an or icon indicates that the LED flashes.
Table 5. MSP-FET LED Signals

Power
Mode LED Function
LED
MSP-FET not connected to PC or MSP-FET not ready; for example, after a major firmware update.
Connect or reconnect MSP-FET to PC.
MSP-FET connected and ready
MSP-FET waiting for data transfer
Ongoing data transfer – during active debug session
An error has occurred; for example, target VCC over current. Unplug MSP-FET from target, and cycle the
power off and on. Check target connection, and reconnect MSP-FET.
Firmware update in progress. Do not disconnect MSP-FET while both LEDs are blinking slowly.
FPGA update in progress. Do not disconnect MSP-FET while both LEDs are blinking rapidly.
5.6.5 Hardware
This section includes MSP-FET hardware descriptions like the JTAG connector, schematics, and power-
up states of the MSP-FET JTAG pins.
5.6.5.1 JTAG Target Connector

Figure 12 shows the pinout of the MSP-FET JTAG connector.
Figure 12. MSP-FET 14-Pin JTAG Connector

5.6.5.2 MSP-FET Pin States After Power Up

Table 6 describes the electrical state of every JTAG pin after debug probe power up.
Table 6. MSP-FET Pin States

When JTAG Protocol is When Spy-Bi-Wire
Pin Name After Power up
Active Protocol is Active
In and Out, SBWTDIO
1 TDO/TDI Hi-Z, pulled up to 3.3 V In, TDO
(RST pin)
2 VCC_TOOL 3.3 V Target VCC Target VCC
3 TDI/VPP Hi-Z, pulled up to 3.3 V Out, TDI Hi-Z, pulled up to VCC
4 VCC_TARGET In, external VCC sense In, external VCC sense In, external VCC sense
5 TMS Hi-Z, pulled up to 3.3 V Out, TMS Hi-Z, pulled up to VCC
6 N/C N/C N/C N/C
7 TCK Hi-Z, pulled up to 3.3 V Out, TCK Out, SBWTCK
8 TEST/VPP Out, Ground Out, TEST Hi-Z, pulled up to VCC
9 GND Ground Ground Ground
Out, Target UART Clear- Out, Target UART Clear-
10 UART_CTS/SPI_CLK/I2C_SCL Hi-Z, pulled up to 3.3 V
To-Send Handshake input To-Send Handshake input
11 RST Out, VCC Out, RST Ground
In, Target UART TXD In, Target UART TXD
12 UART_TXD/SPI_SOMI/I2C_SDA Hi-Z, pulled up to 3.3 V
output output
In, Target UART Ready- In, Target UART Ready-
13 UART_RTS Hi-Z, pulled up to 3.3 V to-Send Handshake to-Send Handshake
output output
Out, Target UART RXD Out, Target UART RXD
14 UART_RXD/SPI_SIMO Hi-Z, pulled up to 3.3 V
input input
NOTE: To enable the UART, I2C, or SPI pins, the correct invalid baud rate activation command
must be sent (see Table 3 and Table 4). After this, the pins switch to the states in Table 6.
NOTE: MSP430BSL-SPI support is currently not available using the MSP-FET. The pin names used
in Table 6 are the same as the names that are printed on the back of the MSP-FET.

5.6.5.3 MSP-FET HID Cold Boot

If the MSP-FET does not respond to software commands or firmware updates, a cold boot is the last
option to bring it back to operation. A cold boot is performed by connecting VBUS to the PUR signal of the
MSP-FET host device (MSP430F6638) with a serial resistor.
To execute this procedure, the MSP-FET cover must be opened by unscrewing the four screws on its
back (see Figure 13). Make sure that the USB cable is disconnected from the computer.
Figure 13. Open MSP-FET Cover
Next connect a cable or jumper to J5 (see Figure 14).
Figure 14. Jumper J5
Plug in the USB cable while the jumper is on J5. After boot, remove the jumper from J5. The MSP-FET is
recognized by the device manager of the OS as an HID-compliant device. The green LED should be on.
Start the IDE while the MSP-FET is in recovery (HID) mode. When prompted (see Figure 15), confirm the
request to recover the firmware and all following firmware update requests.

Figure 15. Recovery Confirmation

www.ti.com

A B C D E F
VBUS5
0R, dnp
USB interface Host MCU Debug i/f

R85
0R R17 C70 C71

4.7u, dnp 100n VCC_POD33
D7 VBUS bypass
11
10
J1 B0530W-7-F GND1 GND1

1 A C VBUS
27k
VUSB
1 2 R45 27R PUR R76 1
3 R3 27R 1k4 R2 PU.0/DP
HOST_RST
4 PU.1/DM
IO3 4
IO4 5
VCC 6
TPD4E004DRYR
1
5 C14 C23 C8 C55
4.7u, dnp 100n R62 220n
A_VCC_SENSE0_TRGT
C31 C33 R61 100R

U5
1n
A_VCC_SUPPLY_HOST
7
6
1M 2
10p 10p
3 GND
Figure 16. MSP-FET USB Debugger, Schematic (1 of 5)

2 IO2
1 IO1
3 1
33k R60 1
VCC_POD33
VCC_POD33
HOST_TEST
HOST_TDO
HOST_TMS
HOST_RST
HOST_TCK
DCDC_IO1
HOST_TDI
GND1
USB BSL activation P1
A_VBUS5
PU.1/DM
PU.0/DP
1 1 1
J5
VBUS
VBAK
A_VF
VUSB
PUR
V18
1 1 1 1
1 1
100
P6.1/CB1/A1 98
P6.0/CB0/A0 97
RST/NMI/SBWTDIO 96
PJ.3/TCK 95
PJ.2/TMS 94
PJ.0/TDO 92
TEST/SBWTCK 91
DVSS3 90
DVCC3 89
P5.7/RTCCLK 88
VBAK 86
P7.3/XT2OUT 85
P7.2/XT2IN 84
AVSS3 83
V18 82
VBUS 80
PU.1/DM 79
PUR 78
PU.0/DP 77
VSSU 76
99
93
87
81
PJ.1/TDI/TCLK
P6.3/CB3/A3
P6.2/CB2/A2

VUSB
VBAT
General power supply
VCC_POD33
2 VCC_POD33 2
A_VCC_DT 1 P6.4/CB4/A4 P9.7/S0 75 PWM_SETVF
C7
DVCC2 A_VCC_DT_BSR 2 P6.5/CB5/A5 P9.6/S1 74 VCC_DT2SUPPLY_CTRL
100n
VCC_DT_SENSE 3 P6.6/CB6/A6/DAC0 P9.5/S2 73 MCU_P9.5
LED0 4 P6.7/CB7/A7/DAC1 P9.4/S3 72 FPGA_TRST
AVCC_POD DCDC_TEST 5 P7.4/CB8/A12 P9.3/S4 71 FPGA_TDO
1 DCDC_RST 6 P7.5/CB9/A13 P9.2/S5 70 FPGA_TMS
AVCC1 + C5 C6 VCC_DT_REF 7 P7.6/CB10/A14/DAC0 P9.1/S6 69 FPGA_TDI
4k7
VCC_POD33
100n VCC_DCDC_REF 8 P7.7/CB11/A15/DAC1 R28
10uF/6.3V P9.0/S7 68 FPGA_TCK
4k7
VREF+ 9 P5.0/VREF+/VEREF+ R30
P8.7/S8 67 VCC_SUPPLY2TRGT_CTRL
C9
DVCC3 FPGA_RESET 10 P5.1/VREF-/VEREF- P8.6/UCB1SOMI 66 HOST_SCL
100n
AVCC_POD 11 AVCC1 P8.5/UCB1SIMO 65 HOST_SDA
12 AVSS1 DVCC2 64 VCC_POD33
1
13 XIN U1 DVSS2 63
0R R1
VCC_POD33 14 XOUT MSP430F6638IPZR
1 AVCC_POD P8.4/UCB1CLK/UCA1ST62 DCDC_IO0
15 AVSS2 P8.3/UCA1RXD 61 MCU_P8.3
VCC_POD33
0R R50 MCU_DMAE0 16 P5.6/ADC12CLK/DMAE0 P8.2/UCA1TXD 60 MCU_P8.2
1
DVCC1 + DCDC_PULSE 17 P2.0/P2MAP0 P8.1/UCB1STE 59 MCU_P8.1

C12 C11
MCU_P2.1 18 P2.1/P2MAP1 P8.0/TB0CLK/S15 58 VCC_DT2TRGT_CTRL
3 10uF/6.3V 100n 3
MCU_P2.2 19 P2.2/P2MAP2 P4.7/TB0OUTH/SVMOUT57 MCU_P4.7
MCU_P2.3 20 P2.3/P2MAP3 P4.6/TB0.6/S17 56 MCU_P4.6
MCU_P2.4 21
P2.4/P2MAP4 P4.5/TB0.5/S18 55 MCU_P4.5
MCU_P2.5 22
1 P2.5/P2MAP5 P4.4/TB0.4/S19 54 MCU_P4.4
MCU_P2.6 23
P2.6/P2MAP6/R03 P4.3/TB0.3/S20 53 MCU_P4.3
MCU_P2.7 24
P2.7/P2MAP7/LCDREF/ P4.2/TB0.2/S21 52 MCU_P4.2
VCC_POD33 25
DVCC1 P4.1/TB0.1/S22 51 MCU_P4.1
Debug Probes Hardware and Software
P3.0/TA1CLK/CBOUT/S
P3.4/TA2CLK/SMCLK/S
P1.0/TA0CLK/ACLK/S3
LED
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P4.0/TB0.0/S23
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
LCDCAP/R33
Additional supply
VCORE(2)
P5.2/R23
LED0
LED1
DVSS1
COM0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCORE
VREF+
VBAK
V18
R47 470R
R46 470R
Schematics
VF2TEST_CTRL
VF2TDI_CTRL
TDIOFF_CTRL
MCU_P1.0
MCU_P1.1
MCU_P1.3
MCU_P1.4
MCU_P1.5
MCU_P1.6
MCU_P1.7
MCU_P3.0
MCU_P3.1
MCU_P3.2
MCU_P3.3
MCU_P3.4
MCU_P3.5
MCU_P3.6
MCU_P3.7
MCU_P4.0
MCU_P1.2
VCORE
LED1
MSP Debuggers
4 4
C15 C16 C17 C18 Title
68p 470n 220n 4.7n
MSP-FET Rev 1.2
D1 D2
Size Number Rev
C 1 A
1 1 1
1 1
Date 3/12/2014
Sheet 1 of 5
A B C D E F 3/12/2014
5.6.5.4
22
23
MSP Debuggers
A B C D E F
FPGA
MCU_DMAE0
VCC_POD15
VCC_POD33
MCU_P9.5
MCU_P2.1
MCU_P2.2
MCU_P2.3
MCU_P2.4
MCU_P2.5
MCU_P2.6
MCU_P1.0
MCU_P1.1
MCU_P1.2
MCU_P1.3
MCU_P1.4
MCU_P1.5
MCU_P1.6
MCU_P1.7
MCU_P3.0
MCU_P3.1
MCU_P3.2
MCU_P3.3
MCU_P3.4
1 1
1
100
GAA0/IO02RSB0 98
GAA1/IO03RSB0 97
GAB0/IO04RSB0 96
GAB1/IO05RSB0 95
GAC0/IO06RSB0 94
IO08RSB0 92
IO09RSB0 91
IO10RSB0 90
VCC 89
GND 88
IO11RSB0 86
IO13RSB0 85
IO15RSB0 84
IO17RSB0 83
IO18RSB0 82
GBC1/IO20RSB0 80
GBB0/IO21RSB0 79
GBB1/IO22RSB0 78
GBA0/IO23RSB0 77
GBA1/IO24RSB0 76
99
93
87
81
GAC1/IO07RSB0
GBC0/IO19RSB0
IO00RSB0
IO01RSB0
VCCIB0

1
1
1 GND GNDQ 75
FPGA_IO_TCK 2 GAA2/IO51RSB1 VMV0 74 VCC_POD33
FPGA_DIR_CTRL_TCK 3 IO52RSB1 GBA2/IO25RSB0 73 MCU_P3.5

FPGA_IO_TMS 4 GAB2/IO53RSB1 IO26RSB0 72 MCU_P3.6
FPGA_DIR_CTRL_TMS 5 IO95RSB1 GBB2/IO27RSB0 71 MCU_P3.7
FPGA_IO_TDI 6 GAC2/IO94RSB1 GBC2/IO29RSB0 70 MCU_P4.0
FPGA_DIR_CTRL_TDI 7 IO93RSB1 IO31RSB0 69 MCU_P4.1
FPGA_IO_TDO 8 IO92RSB1 VCC 68 VCC_POD15
1
1
2 9 GND GND 67 2
FPGA_DIR_CTRL_TDO 10 GFB1/IO87RSB1 VCCIB0 66 VCC_POD33
VCC_PLF
MCU_P2.7 11 GFB0/IO86RSB1 GCC1/IO35RSB0 65 MCU_P4.2

1
L3 12 VCOMPLF GCC0/IO36RSB0 64 MCU_P4.3

33n FPGA_DIR_CTRL_RST 13 GFA0/IO85RSB1 U2 GCA1/IO39RSB0 63 MCU_P4.4
VCC_POD15 1 2 14 VCCPLF A3PN125-VQG100 GCA0/IO40RSB0 62 MCU_P4.5
FPGA_IO_TEST 15 GFA1/IO84RSB1 GCB2/IO42RSB0 61 MCU_P4.6
FPGA_DIR_CTRL_TEST 16 GFA2/IO83RSB1 GCC2/IO43RSB0 60 MCU_P4.7
+ C19
VCC_POD15 17 VCC GDC1/IO45RSB0 59 MCU_P8.1
10uF/6.3V
VCC_POD33 18 VCCIB1 GDC0/IO46RSB0 58 MCU_P8.2
FPGA_IO_UART_TXD 19 GEC1/IO77RSB1 GDA1/IO49RSB0 57 MCU_P8.3
FPGA_DIR_CTRL_UART_TXD 20 GEB1/IO75RSB1 VJTAG 56 VCC_POD33
1
FPGA_IO_UART_RXD 21
GEB0/IO74RSB1 TRST 55 FPGA_TRST
FPGA_DIR_CTRL_UART_RXD 22
GEA1/IO73RSB1 TDO 54 FPGA_TDO
FPGA_IO_UART_CTS 23
GEA0/IO72RSB1 NC 53
R44 27R
VCC_POD33 24
VMV1 VPUMP 52 VCC_POD33 R4
1k
1
25
GNDQ GND 51
VCC_POD15
3 1
3
FF/GEB2/IO70RSB1
GDC2/IO56RSB1
GDB2/IO55RSB1
GDA2/IO54RSB1
GEC2/IO69RSB1
GEA2/IO71RSB1
C20 C21 C22 C34 C49 C50 C51 C52
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO63RSB1
IO62RSB1
IO61RSB1
IO60RSB1
IO59RSB1
IO58RSB1
IO57RSB1
100n 10n 100n 10n 100n 10n 100n 10n
VCCIB1
VMV1
GND
TMS
VCC
TCK
TDI
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
1
VCC_POD33
FPGA_DIR_CTRL_UART_CTS
FPGA_DIR_CTRL_UART_RTS

FPGA_IO_UART_RTS
R5
FPGA_IO_RST
FPGA_RESET
FPGA_TMS
VCC_POD15
VCC_POD33
VCC_POD33
FPGA_TDI
FPGA_TP0
FPGA_TP1
FPGA_TP2
1k
FPGA_TCK
C35 C36 C37 C38 C39 C40 C41 C42
100n 10n 100n 10n 100n 10n 100n 10n
1

1
VCC_PUMP VCC_JTAG
VCC_PLF VCC_POD33 VCC_POD33
4 C43 C44 C45 C46 C47 C48 4
100n 10n 100n 10n 100n 10n Title
MSP-FET Rev 1.2
Size Number Rev
1 1 1
C 1 A
Date 3/12/2014
Sheet 2 of 5
www.ti.com
A B C D E F 3/12/2014
www.ti.com

A B C D E F
S/W controlled DCDC converter
GND1
DCDC calibration switch
Energy measurement method protected under U.S. Patent Application 13/329,073
R20
1 and subsequent patent applications 1
VCC_SUPPLY
0R
VCC_DT
VBUS5
DCDC MCU
+ DCDCGND
C57 C56 C63
2.2u 4.7u 100n
R53
U4
2

GND1
MSP430G2452PW C72 2.2u U20

S
DCDCGND 1
VCC_POD33 1 DVCC DVSS 14 G TS3A4751PWR
R56
A_VCC_SUPPLY 2 P1.0/TA0CLK XIN/P2.6 13 DCDC_CAL0 1 NO1 V+ 14
3
Q3
D
DCDC_CAL1 3 P1.1/TA0.0 XOUT/P2.7 12 DCDC_CAL2 D4 2 COM1 IN1 13 DCDC_CAL0

R64
3
DCDC_PULSE 4 P1.2/TA0.1 TEST/SBWTCK 11 DCDC_TEST 3 NO2 IN4 12

L4
DCDC_IO0 5 P1.3/ADC10CLK NMI-RST 10 DCDC_RST C69 2.2u 4 COM2 NO4 11
1
1 2 VCC_SUPPLY
DCDC_IO1 6 P1.4/TA0.2 C3
P1.7/SDI 9 HOST_SDA DCDC_CAL1 5 IN2 COM4 10
C1,C2 3

VCC_DCDC_REF 7 P1.5/TA0.0 HOST_SCL B1 Q4
P1.6/TA0.1 8 DCDC_CAL2 6 IN3 COM3 9 VCC_SUPPLY
D8
MSP430G2452PW 7 GND NO3 8
E
2 C53 C29
1 A1
2 A2
TS3A4751PWR R63
C66 100n 4.7u
R55
C73 2.2u
1n
DCDCGND DCDCGND DCDCGND GND1 GND1 GND1
2 2
R19
GND1
DCDCGND
DCDC MCU reference voltage DT level shifter supply
VCC_DT_BSR
VCC_SUPPLY VCC_SUPPLY
U7
TPS73401DDCT DT current measurement shunt
R57 0.2
R65 R6 VBUS 1 IN OUT 5 VCC_DT
R23 180k
220k 220k 2 GND
C54 1n
C26
C10 C62 3 EN NR 4
A_VCC_SUPPLY A_VCC_SUPPLY_HOST 2.2u
1u 10n
GND1
R25 150k
R24 160k
R15 R7 GND1 GND1 GND1
C28 C1
VCC_DT_REF
220k 33p 220k 33p
C24 1n
3 GND1 3
GND1
1 1
DT current sense
VCC_POD33
DCDC MCU debug i/f
C65 100n
C67 10p
VCC_POD33
27k, dnp U10
V+
R26 GND1 GND1 3 INA214AIDCKT
10R R49
VCC_DT 5 IN-
6 VCC_DT_SENSE
DCDC_RST 4 IN+ OUT
2 INA21XDCK
C68 1n
REF
1
GND
C13
1n, dnp
10R R54
VCC_DT_BSR
GND1
MSP Debuggers
4 4
GND1
Size Number Rev
MSP-FET Rev 1.2 A
C 1
Date 3/12/2014
Sheet 3 of 5
A B C D E F 3/12/2014
24
25
MSP Debuggers
A B C D E F
Fuse blow step-up converter
L2
DT level shifters VCC_POD33 VCC_DT_TRGT
33u D10
B0530W-7-F C77 C78 C79 C80 C83 C84 C85 C82
VBUS A C VF 100n 100n 100n 100n 100n 100n 100n 100n
1 1
C30 D3
C74 U12 U17
+ GND1 GND1
330n dnp SN74LVC1T45DCKR SN74LVC1T45DCKR
DDZ9692-7 VCC_POD33 1 VCCA VCCB 6 VCC_DT_TRGT VCC_POD33 1 VCCA VCCB 6 VCC_DT_TRGT
100u/10V
1
1
2 GND DIR 5 FPGA_DIR_CTRL_TCK 2 GND DIR 5 FPGA_DIR_CTRL_TEST
GND1
R42
C
1k
FPGA_IO_TCK 3 A B 4 TC_TCK_FD FPGA_IO_TEST 3 A B 4 TC_TEST_FD

B Q1 GND1 GND1
PWM_SETVF
BC817-16LT1

E 47k 47k 47k 47k, dnp
R31 R27 R86 R84
47k VCC_DT_TRGT VCC_DT_TRGT
R29
U13 GND1 U22 GND1
VF = +5V ... 6.5V VCC_POD33
SN74LVC1T45DCKR
1 VCCA VCC_DT_TRGT
SN74LVC1T45DCKR
VCC_DT_TRGT
GND1 GND1 VCCB 6 VCC_POD33 1 VCCA VCCB 6
1
1
2 GND DIR 5 FPGA_DIR_CTRL_TMS 2 GND DIR 5 FPGA_DIR_CTRL_UART_TXD
FPGA_IO_TMS 3 A B 4 TC_TMS_FD FPGA_IO_UART_TXD 3 A B 4 TC_UART_TXD_FD

47k 47k 47k 47k
R90 R89 R88 R87
Fuse voltage multiplexer / VCC_DT to level shifters VF2TEST_CTRL
VCC_DT_TRGT VCC_DT_TRGT
U14 GND1 U26 GND1
D6 SN74LVC1T45DCKR SN74LVC1T45DCKR
DNP B0530W-7-F U6
2 ADG821BRMZ-REEL7 47k VCC_POD33 1 VCCA VCCB 6 VCC_DT_TRGT VCC_POD33 1 VCCA VCCB 6 VCC_DT_TRGT 2
A C TC_TEST_BSR
R59
1
VF_TEST S1 VDD VF 2 GND DIR 5 FPGA_DIR_CTRL_TDI 2 GND DIR 5 FPGA_DIR_CTRL_UART_RXD
VF D1 IN1 FPGA_IO_TDI 3 A B 4 TC_TDI_FD FPGA_IO_UART_RXD 3 A B 4 TC_UART_RXD_FD
VCC_DT2TRGT_CTRL
GND1
TC_TEST_FD VF2TDI_CTRL IN2 D2
47k 47k 47k 47k
1
R13 100R GND S2 VF_TDI

R91 R92 R93 R94
VCC_POD33
47k
GND1
R58 VCC_DT_TRGT VCC_DT_TRGT

R14 U9
D5 2k2 U15 GND1 U27 GND1
ADG821BRMZ-REEL7
dnp 47k SN74LVC1T45DCKR SN74LVC1T45DCKR
R48 VCC_DT_TRGT S1 VDD VF
MMSZ5232B-7-F VCC_POD33 1 VCCA VCCB 6 VCC_DT_TRGT VCC_POD33 1 VCCA VCCB 6 VCC_DT_TRGT
VCC_DT D1 IN1
1
1 2 GND DIR 5 FPGA_DIR_CTRL_TDO 2 GND DIR 5 FPGA_DIR_CTRL_UART_CTS
1 IN2 D2 TC_TDI_FD
FPGA_IO_TDO 3 A B 4 TC_TDO_FD FPGA_IO_UART_CTS 3 A B 4 TC_UART_CTS_FD
1
TDIOFF_CTRL GND S2 TC_TDI_BSR

47k
R22
47k 47k 47k 47k
R98 R97 R96 R95
GND1
U16 GND1 U28 GND1
SN74LVC1T45DCKR SN74LVC1T45DCKR
Target MCU connector VCC_POD33 1 VCCA VCCB 6 VCC_DT_TRGT VCC_POD33 1 VCCA VCCB 6 VCC_DT_TRGT
1
2 GND DIR 5 FPGA_DIR_CTRL_RST 2 GND DIR 5 FPGA_DIR_CTRL_UART_RTS
TC_TDO_FD FPGA_IO_RST 3 A B 4 TC_RST_FD FPGA_IO_UART_RTS 3 A B 4 TC_UART_RTS_FD
3 R35 100R
3
VCC_SUPPLY_TRGT
47k 47k 47k 47k
R99 R100 R101 R102
TC_TDI_BSR
R32 100R
GND1 GND1
VF_TDI
VCC_SENSE0_TRGT
TC_TMS_FD J6

R33 100R 1
VCC_JTAGLDO_TRGT 2
TC_TCK_FD
3
4
5
ESD protection
6
R34 100R 7 U21 U3
TC_TEST_BSR 8 TPD8E003DQDR TPD8E003DQDR
9
R37 100R 10 VCC_SUPPLY_TRGT 1 IO1 IO8 8 TC_TCK_FD 1 IO1 IO8 8 TC_UART_RTS_FD
1
VF_TEST 11

12 TC_TDO_FD 2 IO2 IO7 7 TC_TEST_BSR 2 IO2 IO7 7 TC_UART_RXD_FD
13
TC_UART_CTS_FD 14 VCC_SENSE0_TRGT 3 IO3 IO6 6 TC_TMS_FD VCC_JTAGLDO_TRGT 3 IO3 IO6 6 TC_RST_FD
R38 100R TC_TDI_BSR 4 IO4 IO5 5 TC_UART_CTS_FD 4 IO4 IO5 5 TC_UART_TXD_FD
9 GND
9 GND
TC_RST_FD
R39 100R
TC_UART_TXD_FD TPD8E003DQD TPD8E003DQD
R40 100R
4 TC_UART_RTS_FD 1 1
4
R41 100R
TC_UART_RXD_FD
R43 100R
Size Number Rev
MSP-FET Rev 1.2 A
C 1
Date 3/12/2014
Sheet 4 of 5
www.ti.com
A B C D E F 3/12/2014
www.ti.com

A B C D E F
MSP-FET power supply Test points
U19 TP0 TP4 TP11
1 TLV7111533D
1
VCC_SUPPLY FPGA_TP0 VCC_DT
1 EN1 OUT1 6 VCC_POD15
VBUS 2 IN OUT2 5 VCC_POD33
TP1 TP5
3 EN2 GND 4
VBUS FPGA_TP1
R80R
C59 C61
C58 C25
1u 1u TP2 TP6

1u 10n
GND1 FPGA_TP2
1
PWRGND PWRGND PWRGND PWRGND PWRGND
TP3 TP7
DCDC_PULSE GND1
TP9 TP8
DCDC_IO0 DCDC_IO1

Target power switch
U18
TS5A21366RSER
VCC_SUPPLY 1 NO1 COM1 8 VCC_SUPPLY_TRGT
2 VBUS 2 V+ IN2 7 VCC_DT2SUPPLY_CTRL 2
VCC_SUPPLY2TRGT_CTRL 3 IN1 GND 6
GND1
VCC_SUPPLY_TRGT 4 COM2 NO2 5 VCC_DT
47k
47k R16
R21 TS5A21366RSE
GND1 GND1
Common debug and test i/f
J2
1
2 VBUS
3 GND1
HOST_TEST
4 HOST_TDO
5 HOST_TDI
6 HOST_TMS
7 HOST_TCK
8 HOST_RST
HEADER_1X8_50MIL_A
Analog inputs to Host MCU J3
1 A_VCC_SUPPLY_HOST
2
VCC_SENSE0_TRGT VBUS5 VF VCC_DT VCC_DT_BSR 3 DCDC_RST
4 DCDC_TEST
5 VCC_POD33
6
7 VCC_POD15
R10 R51 R12 R78 R9 8 GND1
150k 240k 270k 150k 150k HEADER_1X8_50MIL_A
3 A_VCC_SENSE0_TRGT A_VBUS5 A_VF A_VCC_DT A_VCC_DT_BSR
3
J4
1 FPGA_TRST
2 FPGA_TCK
R11 C3 R52 C27 R36 C4 R79 C32 R18 C2 3 FPGA_TMS
4 FPGA_TDI
150k 33p 150k 33p 150k 33p 150k 33p 150k 33p 5 FPGA_TDO
6 HOST_SCL
7 HOST_SDA
8 VBUS5
HEADER_1X8_50MIL_A
1 1 1 1 1
MSP Debuggers
4 4
Size Number Rev
MSP-FET Rev 1.2 A
C 1
Date 3/12/2014
Sheet 5 of 5
A B C D E F 3/12/2014
26
Figure 21. MSP-FET USB Debugger, PCB (Top) Figure 22. MSP-FET USB Debugger, PCB (Bottom)

5.7 MSP-FET430UIF Stand-Alone Debugger

The MSP-FET430UIF is a powerful debug probe for application development on MSP430 microcontrollers.
This is a legacy debugger being replaced by MSP-FET.
The MSP-FET430UIF provides a USB interface to program and debug the MSP430 devices in-system
through the JTAG interface or the pin-saving Spy-Bi-Wire (2-wire JTAG) protocol.
The MSP-FET430UIF development tool supports development with all MSP430 devices and is designed
for use with PCBs that contain MSP430 devices; for example, the MSP430 target socket boards.
Two different version of the MSP-FET430UIF are available, version 1.3 and version 1.4a. There are
limitations when using version 1.3. See Section 5.7.1 for more details.
Figure 23. MSP-FET430UIF Version 1.4a Top and Bottom Figure 24. MSP-FET430UIF Version 1.3 Top and Bottom
Views Views

The following features are provided by the MSP-FET430UIF debug probe.
Features:
NOTE: OS X El Capitan is not supported using the MSP-FET430UIF.
• Software configurable supply voltage between 1.8 V and 3.6 V at 100 mA

• External voltage detection
• Supports JTAG security fuse blow to protect code
• Supports all MSP430 boards with JTAG header
• Supports both JTAG and Spy-Bi-Wire (2-wire JTAG) debug protocols
• Software breakpoints in flash, FRAM, and RAM support
• Software field update is possible (enable new device support by in field firmware updates)
NOTE: The MSP-FET430UIF version 1.3 does not support Spy-Bi-Wire connection for MSP430
devices with 1-µF capacitance on the reset line.

5.7.2 LED Signals

The MSP-FET430UIF shows its operating states using two LEDs, one green and one red. Table 7 lists all
Table 7. MSP-FET430UIF LED Signals

Power
Mode LED Function
LED
MSP-FET430UIF not connected to PC, or MSP-FET430UIF not ready; for example, after a major
firmware update. Connect or reconnect MSP-FET430UIF to PC.
MSP-FET430UIF connected and ready
MSP-FET430UIF waiting for data transfer
An error has occurred; for example, target VCC over current. Unplug MSP-FET430UIF from target, and
cycle the power off and on. Check target connection, and reconnect MSP-FET430UIF.
Firmware update in progress. Do not disconnect MSP-FET430UIF while both LEDs are blinking.
5.7.3 Hardware
This section includes MSP-FET430UIF hardware descriptions like the JTAG connector, schematic, and
power up states of the JTAG pins.

Figure 25 shows the pinout of the MSP-FET430UIF JTAG connector.
Figure 25. MSP-FET430UIF 14-Pin JTAG Connector

5.7.3.2 Pin States After Power Up

Table 8. MSP-FET430UIF Pin States

When JTAG Protocol is When Spy-Bi-Wire
Pin Name After Power-Up
Active Protocol is Active
1 TDO/TDI Hi-Z, pulled up to 3.3 V In, TDO In and Out, SBWTDIO
2 VCC_TOOL 3.3 V Target VCC Target VCC
3 TDI/VPP Hi-Z, pulled up to 3.3 V Out, TDI Hi-Z, pulled up to VCC
4 VCC_TARGET In, external VCC sense In, external VCC sense In, external VCC sense
5 TMS Hi-Z, pulled up to 3.3 V Out, TMS Hi-Z, pulled up to VCC
6 N/C N/C N/C N/C
7 TCK Hi-Z, pulled up to 3.3 V Out, TCK Out, SBWTCK
8 TEST/VPP Out, Ground Out, TEST Hi-Z, pulled up to VCC
9 GND Ground Ground Ground
10 N/C N/C N/C N/C
11 RST Out, VCC Out, RST Ground
12 N/C N/C N/C N/C
13 N/C N/C N/C N/C
14 N/C N/C N/C N/C

5.7.3.3 Schematics
Figure 26. MSP-FET430UIF USB Interface, Schematic (1 of 4)




Figure 30. MSP-FET430UIF USB Interface, PCB

5.8 eZ-FET and eZ-FET Lite Onboard Emulation

The eZ-FET and eZ-FET Lite are powerful onboard flash emulation debug probes for application
development on MSP430 microcontrollers (see Figure 31). The eZ-FET and eZ-FET Lite onboard
emulation are the successors of the legacy eZ430.
Both eZ-FETs provide a USB interface to program and debug the MSP430 devices in-system through the
pin-saving Spy-Bi-Wire (2-wire JTAG) protocol. Furthermore, the USB interface can be used for
backchannel UART communication.
Both development tools support development with all MSP430 devices. They are designed as onboard
emulation that is available on several LaunchPad kits. (Only MSP430 devices that implement the SBW2
protocol are supported.)
Figure 31. eZ-FET and eZ-FET Lite (Top View)
Figure 32 shows revision 1.3 of the eZ-FET.
Figure 32. eZ-FET Rev1.3 (Top View)


The following features are provided by the eZ-FET and eZ-FET Lite debug probes.
Features:
• eZ-FET and eZ-FET Lite supported since:
– CCS v5.4.0
– IAR EW430 v5.52.1 and v5.51.6
• Fixed supply voltage between 3.3 or 3.6 V at 75 mA
• Support Spy-Bi-Wire (2-wire JTAG) debug protocol
• Software breakpoint in flash, FRAM, and RAM support
• Backchannel UART
• eZ-FET only – EnergyTrace and EnergyTrace++ support
• EnergyTrace technology accuracy
– Current < 25 µA: Error range = ±500 nA
– Current ≥ 25 µA and ≤ 75 mA: Error range = ±5%
• Software field update is possible

Supported baud rates depend on the target configuration and the debug settings. Table 9 shows which
baud rates are supported with certain configuration combinations.
Table 9. eZ-FET and eZ-FET Lite Backchannel UART Implementation

Target MCLK
1 MHz 8 MHz 1 MHz 8 MHz
Frequency:
Debugger: Active Inactive
Flow Control: No Yes No Yes No Yes No Yes
4800 baud ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
9600 baud ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
19200 baud ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
28800 baud ✗ ✓ ✓ ✓ ✓ ✓ ✓ ✓
38400 baud ✗ ✓ ✗ ✓ ✗ ✓ ✗ ✓
57600 baud ✗ ✓ ✗ ✓ ✗ ✓ ✗ ✓
115200 baud ✗ ✗ ✗ ✓ ✗ ✗ ✗ ✓
5.8.2.1 eZ-FET and eZ-FET Lite UART Backchannel Activation Commands

The eZ-FET supports two different backchannel UART modes, one with flow control and one without. The
different modes can be selected by opening the corresponding COM port with a dedicated baud rate. See
Table 10 for the specific baud rates for each command.
NOTE: The baud rates used by these commands cannot be used for communication.
If none of the specified commands are transferred before setting the communication baud rate,
communication starts with these default settings: VCC on, no flow control mechanism.
Table 10. eZ-FET and eZ-FET Lite Backchannel UART Activation Commands
Baud Rate Command
9620 Set all backchannel UART pins to high impedance – no current flow into target device
9621 Configure backchannel UART communication without handshake (default start behavior)
Configure backchannel UART communication with handshake
9622
NOTE: Available on Rev. 1.2 only.
9623 Voltage configuration command. When this command is received, target VCC switched on.
Configure backchannel UART communication without handshake and even parity (available starting with
9625
MSPDebugStack version 3.8.0.2)
5.8.3 LED Signals

eZ-FET emulators show their operating states using two LEDs, one green and one red. Table 11 lists all
Table 11. eZ-FET LED Signals

Power
Mode LED Function
LED
eZ-FET not connected to PC, or eZ-FET not ready; for example, after a major firmware update. Connect
or reconnect eZ-FET to PC.
eZ-FET connected and ready
eZ-FET waiting for data transfer
An error has occurred; for example, target VCC over current. Unplug eZ-FET from target, and cycle the
power off and on. Check target connection, and reconnect eZ-FET.
Firmware update in progress. Do not disconnect eZ-FET while both LEDs are blinking.
5.8.4 Hardware
This section describes the pinout of the eZ-FET and eZ-FET Lite debug connector. It includes a list of all
debugger pin states after power up and the eZ-FET and eZ-FET Lite schematics.

Figure 33 shows the pinout of the eZ-FET debug connector.
Figure 33. eZ-FET or eZ-FET Lite Debug Connector

5.8.4.2 Connecting MSP-FET to LaunchPad Development Kit

Figure 34 and Figure 35 show how to connect an MSP-FET to the target MSP430 device that is solders
onto the LaunchPad, using an F5529 LaunchPad as an example.
Figure 34. MSP-FET to LaunchPad Development Kit Pin Figure 35. MSP-FET to LaunchPad Wiring Diagram
Assignments

Table 12. eZ-FET and eZ-FET Lite Pin States

Signal Name After Power-Up When Spy-Bi-Wire Protocol is Active
SBWTDIO Hi-Z, pulled up to 3.3 V In and Out, SBWTDIO
SBWTCK Hi-Z, pulled up to 3.3 V Out, SBWTCK
TXD Hi-Z, pulled up to 3.3 V In, Target UART TXD output
RXD Hi-Z, pulled up to 3.3 V Out, Target UART RXD input
CTS Hi-Z, pulled up to 3.3 V Out, Target UART Clear-To- Send Handshake input
RTS Hi-Z, pulled up to 3.3 V In, Target UART Ready-to Send Handshake output
3V3 Target VCC Target VCC
5V USB VCC USB VCC
GND Ground Ground

5.8.4.4 Schematics
Figure 36. eZ-FET Schematic (USB Connection)

Figure 37. eZ-FET Schematic (Emulation MCU)

Figure 38. eZ-FET Schematic DCDC (No eZ-FET Lite)

5.9 eZ430 Onboard Emulation

The eZ430 onboard emulation is the legacy onboard flash emulation for application development on
MSP430 microcontrollers. The eZ-FET and eZ-FET Lite onboard emulation are the successors of the
legacy eZ430.
The eZ430 provides a USB interface to program and debug the MSP430 devices in-system through the
pin-saving Spy-Bi-Wire (2-wire JTAG) protocol. Furthermore, the USB interface can be used for
Backchannel UART communication.
NOTE: The eZ430 does not support all MSP430 device families. See Table 1 for more details about
device support.
The eZ430 onboard emulation and its backchannel UART might fail to enumerate on USB
3.0 computer ports. If enumeration fails, reconfigure the USB 3.0 port to USB 2.0 mode in
your computer BIOS.
If the eZ430 onboard emulation is used with active software breakpoints, the RUN to MAIN
function might fail. Disable software breakpoints to enable RUN to MAIN.
Figure 39. eZ430 Emulation

USB debug interface to connect a MSP430 MCU to a PC for real-time in-system programming and
debugging.
Features:
• Operating systems: Windows
• Fixed supply voltage between 3.6 V at 75 mA
• Support Spy-Bi-Wire (2-wire JTAG) debug protocol
• Software Breakpoint in Flash, FRAM, and RAM support
• Backchannel UART
• Software field update is not possible (see Table 1 for device support details)
• Limited device support


The baud rates that are supported depend on the target configuration and the debug settings. Table 13
shows which baud rates are supported with certain configuration combinations.
Table 13. eZ430 Backchannel UART Implementation

Target MCLK Frequency: 1 MHz 8 MHz
Debugger: Active Active
4800 baud ✓ ✓
9600 baud ✓ ✓
19200 baud ✗ ✗
28800 baud ✗ ✗
38400 baud ✗ ✗
57200 baud ✗ ✗
115200 baud ✗ ✗
5.9.3 Hardware
This section describes the pinout of the eZ430 debug connector. It includes a list of all debugger pin
states after power up and the ez430 schematics.

Figure 40 shows the pinout of the eZ430 debug connector.
Figure 40. eZ430 Debug Connector on MSP-EXP430G2 LaunchPad

Table 14. eZ430 Pin States

Signal Name After Power-Up When Spy-Bi-Wire Protocol is Active
VCC Target VCC Target VCC
RST In and Out, SBWTDIO In and Out, SBWTDIO
TST Out, SBWTCK Out, SBWTCK
TXD In, Target UART TXD output In, Target UART TXD output
RXD Out, Target UART RXD input Out, Target UART RXD input

5.9.3.3 Schematics
Figure 41. eZ430 Schematic (Emulation MCU)

Figure 42. eZ430 Schematic (USB Connection)

5.10 MSP-FET430PIF
The MSP-FET430PIF is a parallel port interface that is used to program and debug MSP430 boards
through the JTAG interface. This interface uses a parallel PC port to communicate with the IDE (CCS,
EW430, or the MSP Flasher) running on the PC. The interface uses the standard 14-pin JTAG header to
communicate with the MSP430 device using the standard JTAG protocol.
The flash memory can be erased and programmed in seconds with only a few keystrokes, and because
the MSP430 flash is extremely low power, no external power supply is required. The tool has an
integrated software environment and connects directly to the PC which greatly simplifies the setup and
use of the tool.
Figure 43. MSP-FET430PIF

• Operating systems: Windows XP
• Fixed supply voltage between 3.3 V at 25 mA
• Software Breakpoint in Flash, FRAM, and RAM support
• Supports JTAG protocol only (1)
NOTE: The MSP-FET430PIF is for legacy device support only. This emulation tool does not support
any devices released after 2011.
(1)
Spy-Bi-Wire (2-wire JTAG) is supported

5.10.2 Schematics
Figure 44. MSP-FET430PIF FET Interface Module, Schematic

Figure 45. MSP-FET430PIF FET Interface Module, PCB

Revision History www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from March 10, 2017 to April 6, 2017 ............................................................................................................... Page
• Removed Windows XP from supported operating systems in Section 5.1, MSPDebugStack ................................ 13
• Added the NOTE that starts "The MSP-FET supply voltage is generated by..." in Section 5.6.1, General Features ...... 15
• Added the NOTE "MSP-FET BSL I2C pullup resistors must not exceed 2-kΩ resistance." in Section 5.6.3, Target BSL
Connection and BSL-Scripter Support ................................................................................................ 17
50 Revision History SLAU647H – July 2015 – Revised April 2017

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est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:

Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables

Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】開発キットの中には技術基準適合証明を受けて
いないものがあります。技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
2. 実験局の免許を取得後ご使用いただく。
3. 技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union

3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
4 EVM Use Restrictions and Warnings:

4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6. Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8. Limitations on Damages and Liability:

8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are
developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you
(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of
this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources.
You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your
applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications
(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You
represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)
anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that
might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you
will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any
testing other than that specifically described in the published documentation for a particular TI Resource.
You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include
the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO
ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS.
TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT
LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF
DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL,
COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR
ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your non-
compliance with the terms and provisions of this Notice.
This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation
modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated

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User's Guide

SLAU647H – July 2015 – Revised April 2017

SLAU647H – July 2015 – Revised April 2017 MSP Debuggers 1

29 MSP-FET430UIF USB Interface, Schematic (4 of 4) .................................................................. 34

2 MSP Debuggers SLAU647H – July 2015 – Revised April 2017

1.1 Related Documentation From Texas Instruments

MSP430™ Hardware Tools User's Guide

1.2 Terms and Abbreviations

1.3 If You Need Assistance

SLAU647H – July 2015 – Revised April 2017 MSP Debuggers 3

2 MSP Debug Probe Overview

eZ-FET Lite Emulation IP

4 MSP Debuggers SLAU647H – July 2015 – Revised April 2017

eZ-FET Lite Emulation IP

SLAU647H – July 2015 – Revised April 2017 MSP Debuggers 5

3.1 How to Determine If Your Hardware is Based on eZ-FET or eZ-FET Lite

Figure 1. eZ-FET Windows Enumeration

Figure 2. eZ-FET Emulation IP

Figure 3. eZ-FET Lite Emulation IP

6 MSP Debuggers SLAU647H – July 2015 – Revised April 2017

3.2 How to Determine If Your Hardware is Based on eZ430

Figure 4. eZ430 Emulation IP

Figure 5. eZ430 Windows Enumeration

3.3 Signal Connections for In-System Programming and Debugging

SLAU647H – July 2015 – Revised April 2017 MSP Debuggers 7

NOTE: MSP-FET430PIF only

4.2 MSP-FET430UIF, MSP-FET, eZ-FET, and eZ-FET Lite

8 MSP Debuggers SLAU647H – July 2015 – Revised April 2017

Installation steps for the MSP-FET430UIF, MSP-FET, eZ-FET or eZ-FET Lite:

4.3 eZ430-Based Experimenter Boards and LaunchPad Kits

SLAU647H – July 2015 – Revised April 2017 MSP Debuggers 9

4.4 Hardware Installation Using the MSP Flasher

Figure 6. MSP Flasher Driver Install Notification

10 MSP Debuggers SLAU647H – July 2015 – Revised April 2017

4.5 Hardware Installation Using CCS Cloud

Figure 7. CCS Cloud Agent Installation

Figure 8. Successful CCS Cloud Agent Installation

SLAU647H – July 2015 – Revised April 2017 MSP Debuggers 11

5 Debug Probes Hardware and Software

Figure 9. MSP Ecosystem

12 MSP Debuggers SLAU647H – July 2015 – Revised April 2017

5.2 Ultra-Low-Power (ULP) Debug Support

5.3 EnergyTrace™ Technology

SLAU647H – July 2015 – Revised April 2017 MSP Debuggers 13

5.4 Unlimited Software Breakpoints in Flash, FRAM, and RAM

5.5 JTAG Access Protection (Fuse Blow)

14 MSP Debuggers SLAU647H – July 2015 – Revised April 2017

5.6 MSP-FET Stand-Alone Debug Probe

5.6.1 General Features

• External voltage detection

SLAU647H – July 2015 – Revised April 2017 MSP Debuggers 15

• Target BSL communication mode available

5.6.2 Backchannel UART

Table 2. MSP-FET Backchannel UART Implementation

5.6.2.1 UART Backchannel Activation Commands

16 MSP Debuggers SLAU647H – July 2015 – Revised April 2017

Table 3. MSP-FET Backchannel UART Activation Commands

5.6.3 Target BSL Connection and BSL-Scripter Support