A B C D E

COMPAL CONFIDENTIAL
MODEL NAME : NLM01
1 1

PCB NO : LA-6132P ( DA80000I500) DAZ0DD00200

BOM P/N : 43185331L01 (K325)
43185331L02 (K125)
43185331L03 (V105)

M10 Andros
AMD ASB2/ RS880M / SB820M
2 2

2010-05-11
REV : 1.0(A00)
@ : Nopop Component
3 WWAN@: WWAN function 3

NONWWAN@: NON WWAN function

CONN@: Connector only

4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 11, 2010 Sheet 1 of 45
A B C D E
 A B C D E

Thermal Sensor Clock Generator Spread Spectrum

EMC1402 x 2 SB820M ECS2P8211
AMD ASB2 DDR3-SO-DIMM X2
(CPU/NB) K325 / 2C / 1.3G / 2M
1
Internal CKG K125 / 1C / 1.7G / 1M Page 10, 11 1

Page 8/13 Page 16 Page 18 DDR3 BUS

Dual Channel
Page 6,7,8,9
DDRIII 800MHz
Hyper Transport Link
HT3 16x16 1.0GHz up to 1.6GHz

LVDS SidePort DDR3 64x16Mb

LVDS conn. Page 27
128MB LFB Page 14
TMDS
AMD-RS880M
HDMI conn. Page 22
BGA 528
USB port2
VGA USB conn.
Page 33
CRT conn. Page 24 Page 12,13,14,15

USB port0,1
PCI Express USB conn. x 2
A-Link Express Sub/B & Page 23
2 2
4 x PCIE
GPP PCIE0 GPP PCIE1 GPP PCIE2 USB port4 Mini Card
WLAN Page 28
LAN Mini Card Mini Card
Atheros AR8132 WLAN WWAN AMD-SB820M USB2.0 USB port5 Mini Card
WWAN Page 28 SIM conn.
Page 20 Page 28 Page 28 Page 28
BGA 605
USB port6
Bluetooth conn.
Page 28
RJ45 conn.
Page 16,17,18,19
Page 20 Page 21
USB port8 CardBus 3 in 1 conn.
Realtek RTS5138 Page 21

LPC BUS USB port9

Camera
Page 27
DC/DC Power Button
3
(Power Control) Page 30 Sub/B 3

Power Circuit EC ENE KB926 CODEC Audio Jack x 2

Sub/B
+3VALW / +5VALW Page 26 AZ-Audio I/F Realtek ALC259
BATT IN &OTP
+1.1VALW
Page 33 Sub/B
+0.75VS Digital MIC
Camera side
+1.5V
+1.8V DC IN & DECTOR Int. KBD
+2.5VDDA / +CPU_VDDR Page 26
Page 34
+CPU_CORE / +VDDNB T/P conn.
+NB_CORE Page 31
SPI ROM
CHARGER
Page 31
Page 36~43 Page 35

4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Block Diagram
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Monday, May 03, 2010 Sheet 2 of 45
A B C D E
 5 4 3 2 1

SB820M
POWER STATES USB PORT# DESTINATION
Signal SLP SLP SLP S4 SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# STATE# M# PLANE PLANE PLANE PLANE 0 USB (Right)

D
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON 1 USB (Right) D

S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH HIGH ON ON ON OFF ON 2 USB (Left)

S4 (Suspend to DISK) / M1 LOW LOW HIGH LOW HIGH ON ON OFF OFF ON 3 None

S5 (SOFT OFF) / M1 LOW LOW LOW LOW HIGH ON ON OFF OFF ON 4 MINI CARD - WLAN

S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH HIGH LOW ON OFF ON OFF OFF 5 MINI CARD - WWAN

S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF OFF 6 Bloetooth

S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF OFF 7 None

8 Card Reader

C
PM TABLE 9 Camera C

B+ +1.5V +5VS 10 None

+5VALW +3VS
+3VALW +1.8VS
power +1.1VALW +1.5VS 11 None
plane +1.1VS
+0.75VS
+2.5VDDA 12 None
+CPU_VDDR
+NB_CORE
+CPU_CORE
13 None
State +VDDNB

RS880M
S0 ON ON ON PCIE DESTINATION
S3 ON ON OFF Lane 1 10 / 100 LAN
B
S5 S4/AC ON OFF OFF Lane 2 MINI CARD - WLAN B

S5 S4/AC don't exist OFF OFF OFF Lane 3 MINI CARD - WWAN

Lane 4 None

Lane 5 None

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Index and Config.
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Monday, May 03, 2010 Sheet 3 of 45
5 4 3 2 1
 5 4 3 2 1

EN_INVPWR
ADAPTER
SI3457 INVPWR_B+
(QV6)
D D

VR_ON
ISL6265 +CPU_CORE
(PU14)
BATTERY +PWR_SRC
+VDDNB

CHARGER TPS51427
(PU2)
MAINPWON

C C

+5VALW +3VALW

TPS51218 TPS2062 TPS2062 TPS2062 NTMS4920 TPS51218 TPS51218 NTMS4920 SI3456DY APL5912
(PU15) (UI13) (UI14) (UI15) (QZ3) (PU10) (PU7) (QZ8) (QZ11) (PU11)

EN_WOL#
USB_EN#

USB_EN#

SYSON

POK
SUSP

SUSP
SUSP#

SUSP#
USB_PWR_EN#

B B
+USB_SIDE
+NB_CORE +USB_VCCA +5V_ESAUSB +5VS +1.5V +1.1VALW +3VS +3V_LAN +1.8VS
_PWR

SI2301 SI4634DY APL5912 APL5331 SI4634DY APL5508 AO3413

(QO4) (QZ12) (PU12) (PU8) (QZ15) (PU13) (QV8)

ENVDD
SUSP

SUSP

SUSP
SUSP#

CAM_ON/OFF# LCD_VCC_TEST_EN

+5VS_CAM +1.5VS +CPU_VDDR +0.75VS +1.1VS +2.5VDDA +LCD_VDD

A (0.9V) A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Monday, May 03, 2010 Sheet 4 of 45
5 4 3 2 1
 5 4 3 2 1

+1.5V
1K
D 1K D

MMBT3904 UT5 @
AN4 CPU_SIC 8 SMBUS Address [TBD]
ASB2 AN5 CPU_SID
MMBT3904 7
(CPU_Thermal)

+3VS
2.2K
2.2K

AD22 MEM_SMBCLK 202 JDIMMA SMBUS Address [TBD]

AE22 MEM_SMBDATA 200
C +3VALW C
10K
10K 202 JDIMMB SMBUS Address [TBD]
200
F5 SB_SMB_CLK1
F4 SB_SMB_DAT1
UT7
SB 820M +3VALW 8
(NB_Thermal) SMBUS Address [TBD]
10K 7
10K

D25 SB_SMB_CLK2
F23 SB_SMB_DAT2

+1.5V
1K
1K

B26 SB_SMB_CLK3
0R @
F26 SB_SMB_DAT3
0R @
B B

+5VALW
4.7K
4.7K
0R @ WWAN_SMB_CK_R 30 JWLAN1 SMBUS Address [TBD]
100R PJBATT 0R @
77 EC_SMB_CK1 7 SMBUS Address [TBD] WWAN_SMB_DA_R 32
(BattERy conn)
78 EC_SMB_DA1
100R 6

0R @ WWAN_SMB_CK_R 30
+3VALW +3VS JWWAN1 SMBUS Address [TBD]
KB 926 2.2K @ 2.2K 0R @ WWAN_SMB_DA_R 32
2.2K @ 2.2K

79 EC_SMB_CK2
0R @ LAN_SMB_CK_R 30 UL10 (LAN) SMBUS Address [TBD]
80 EC_SMB_DA2
0R @ LAN_SMB_DA_R 32

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SMBus Topology
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Monday, May 03, 2010 Sheet 5 of 45
5 4 3 2 1
 5 4 3 2 1

D D

UU1A K325@

H_CADIP0 H2 AK1 H_CADOP0 H_CADOP0 <12>

<12> H_CADIP0 L0_CADIN_H0 L0_CADOUT_H0
H_CADIN0 H1 AK2 H_CADON0 H_CADON0 <12>
<12> H_CADIN0 L0_CADIN_L0 L0_CADOUT_L0
H_CADIP1 K2 AF4 H_CADOP1 H_CADOP1 <12>
<12> H_CADIP1 L0_CADIN_H1 L0_CADOUT_H1
H_CADIN1 K1 AF3 H_CADON1 H_CADON1 <12>
<12> H_CADIN1 L0_CADIN_L1 L0_CADOUT_L1
H_CADIP2 K3 AF1 H_CADOP2 H_CADOP2 <12>
<12> H_CADIP2 L0_CADIN_H2 L0_CADOUT_H2
H_CADIN2 K4 AF2 H_CADON2 H_CADON2 <12>
<12> H_CADIN2 L0_CADIN_L2 L0_CADOUT_L2
H_CADIP3 M2 AD4 H_CADOP3 H_CADOP3 <12>
<12> H_CADIP3 L0_CADIN_H3 L0_CADOUT_H3
H_CADIN3 M1 AD3 H_CADON3 H_CADON3 <12>
<12> H_CADIN3 L0_CADIN_L3 L0_CADOUT_L3
H_CADIP4 P2 AB4 H_CADOP4 H_CADOP4 <12>
<12> H_CADIP4 L0_CADIN_H4 L0_CADOUT_H4
H_CADIN4 P1 AB3 H_CADON4 H_CADON4 <12>
<12> H_CADIN4 L0_CADIN_L4 L0_CADOUT_L4
H_CADIP5 P3 AB1 H_CADOP5 H_CADOP5 <12>
<12> H_CADIP5 L0_CADIN_H5 L0_CADOUT_H5
H_CADIN5 P4 AB2 H_CADON5 H_CADON5 <12>
<12> H_CADIN5 L0_CADIN_L5 L0_CADOUT_L5
H_CADIP6 T2 Y4 H_CADOP6 H_CADOP6 <12>
C <12> H_CADIP6 L0_CADIN_H6 L0_CADOUT_H6 C
H_CADIN6 T1 Y3 H_CADON6 H_CADON6 <12>
<12> H_CADIN6 L0_CADIN_L6 L0_CADOUT_L6
H_CADIP7 T3 Y1 H_CADOP7 H_CADOP7 <12>
<12> H_CADIP7 L0_CADIN_H7 L0_CADOUT_H7
H_CADIN7 T4 Y2 H_CADON7 H_CADON7 <12>
<12> H_CADIN7 L0_CADIN_L7 L0_CADOUT_L7
H_CADIP8 G6 AH1 H_CADOP8 H_CADOP8 <12>
<12> H_CADIP8 L0_CADIN_H8 L0_CADOUT_H8
H_CADIN8 G5 AH2 H_CADON8 H_CADON8 <12>
<12> H_CADIN8 L0_CADIN_L8 L0_CADOUT_L8
H_CADIP9 H4 AK3 H_CADOP9 H_CADOP9 <12>
<12> H_CADIP9 L0_CADIN_H9 L0_CADOUT_H9

HT LINK
H_CADIN9 H3 AK4 H_CADON9 H_CADON9 <12>
<12> H_CADIN9 L0_CADIN_L9 L0_CADOUT_L9
H_CADIP10 J6 AH3 H_CADOP10 H_CADOP10 <12>
<12> H_CADIP10 L0_CADIN_H10 L0_CADOUT_H10
H_CADIN10 J5 AH4 H_CADON10 H_CADON10 <12>
<12> H_CADIN10 L0_CADIN_L10 L0_CADOUT_L10
H_CADIP11 L6 AE9 H_CADOP11 H_CADOP11 <12>
<12> H_CADIP11 L0_CADIN_H11 L0_CADOUT_H11
H_CADIN11 L5 AE8 H_CADON11 H_CADON11 <12>
<12> H_CADIN11 L0_CADIN_L11 L0_CADOUT_L11
H_CADIP12 P6 AE6 H_CADOP12 H_CADOP12 <12>
<12> H_CADIP12 L0_CADIN_H12 L0_CADOUT_H12
H_CADIN12 P5 AE5 H_CADON12 H_CADON12 <12>
<12> H_CADIN12 L0_CADIN_L12 L0_CADOUT_L12
H_CADIP13 R7 AC7 H_CADOP13 H_CADOP13 <12>
<12> H_CADIP13 L0_CADIN_H13 L0_CADOUT_H13
H_CADIN13 R6 AC6 H_CADON13 H_CADON13 <12>
<12> H_CADIN13 L0_CADIN_L13 L0_CADOUT_L13
H_CADIP14 U6 AB9 H_CADOP14 H_CADOP14 <12>
<12> H_CADIP14 L0_CADIN_H14 L0_CADOUT_H14
H_CADIN14 U5 AB8 H_CADON14 H_CADON14 <12>
<12> H_CADIN14 L0_CADIN_L14 L0_CADOUT_L14
H_CADIP15 W7 AB6 H_CADOP15 H_CADOP15 <12>
<12> H_CADIP15 L0_CADIN_H15 L0_CADOUT_H15
H_CADIN15 W6 AB5 H_CADON15 H_CADON15 <12>
<12> H_CADIN15 L0_CADIN_L15 L0_CADOUT_L15

H_CLKIP0 M3 AD1 H_CLKOP0 H_CLKOP0 <12>

<12> H_CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0
H_CLKIN0 M4 AD2 H_CLKON0 H_CLKON0 <12>
<12> H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0
H_CLKIP1 M8 AF6 H_CLKOP1 H_CLKOP1 <12>
<12> H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1
H_CLKIN1 M7 AF5 H_CLKON1 H_CLKON1 <12>
<12> H_CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1

H_CTLIP0 V2 V4 H_CTLOP0 H_CTLOP0 <12>

<12> H_CTLIP0 L0_CTLIN_H0 L0_CTLOUT_H0
H_CTLIN0 V1 V3 H_CTLON0 H_CTLON0 <12>
<12> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0
H_CTLIP1 Y6 Y8 H_CTLOP1 H_CTLOP1 <12>
<12> H_CTLIP1 L0_CTLIN_H1 L0_CTLOUT_H1
H_CTLIN1 Y5 Y9 H_CTLON1 H_CTLON1 <12>
<12> H_CTLIN1 L0_CTLIN_L1 L0_CTLOUT_L1
B B

ASB2_BGA812

UU1 K125@ UU1 V105@

ASB2_BGA812 ASB2_BGA812
SA00003RI0L SA00003TL0L

V105 PART NO. need apply again

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ASB2 HT I/F & FAN
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 6 of 45
5 4 3 2 1
 5 4 3 2 1

UU1B K325@ Processor DDR3 Memory Interface UU1C K325@

DDR_A_MA0 AC26 F11 DDR_A_D0 DDR_B_MA0 AC33 A14 DDR_B_D0

<10> DDR_A_MA0 MA_ADD0 MA_DATA0 DDR_A_D0 <10> <11> DDR_B_MA0 MB_ADD0 MB_DATA0 DDR_B_D0 <11>
DDR_A_MA1 W29 E11 DDR_A_D1 DDR_B_MA1 Y32 C14 DDR_B_D1
<10> DDR_A_MA1 MA_ADD1 MA_DATA1 DDR_A_D1 <10> <11> DDR_B_MA1 MB_ADD1 MB_DATA1 DDR_B_D1 <11>
DDR_A_MA2 AB29 E14 DDR_A_D2 DDR_B_MA2 Y33 A17 DDR_B_D2
<10> DDR_A_MA2 MA_ADD2 MA_DATA2 DDR_A_D2 <10> <11> DDR_B_MA2 MB_ADD2 MB_DATA2 DDR_B_D2 <11>
DDR_A_MA3 Y30 E15 DDR_A_D3 DDR_B_MA3 Y31 B18 DDR_B_D3
<10> DDR_A_MA3 MA_ADD3 MA_DATA3 DDR_A_D3 <10> <11> DDR_B_MA3 MB_ADD3 MB_DATA3 DDR_B_D3 <11>
DDR_A_MA4 U27 H12 DDR_A_D4 DDR_B_MA4 W33 A13 DDR_B_D4
<10> DDR_A_MA4 MA_ADD4 MA_DATA4 DDR_A_D4 <10> <11> DDR_B_MA4 MB_ADD4 MB_DATA4 DDR_B_D4 <11>
DDR_A_MA5 V30 G12 DDR_A_D5 DDR_B_MA5 V31 B14 DDR_B_D5
<10> DDR_A_MA5 MA_ADD5 MA_DATA5 DDR_A_D5 <10> <11> DDR_B_MA5 MB_ADD5 MB_DATA5 DDR_B_D5 <11>
DDR_A_MA6 U28 H14 DDR_A_D6 DDR_B_MA6 V33 A16 DDR_B_D6
<10> DDR_A_MA6 MA_ADD6 MA_DATA6 DDR_A_D6 <10> <11> DDR_B_MA6 MB_ADD6 MB_DATA6 DDR_B_D6 <11>
DDR_A_MA7 R27 H15 DDR_A_D7 DDR_B_MA7 U33 C16 DDR_B_D7
D <10> DDR_A_MA7 MA_ADD7 MA_DATA7 DDR_A_D7 <10> <11> DDR_B_MA7 MB_ADD7 MB_DATA7 DDR_B_D7 <11> D
DDR_A_MA8 R26 E17 DDR_A_D8 DDR_B_MA8 V32 A19 DDR_B_D8
<10> DDR_A_MA8 MA_ADD8 MA_DATA8 DDR_A_D8 <10> <11> DDR_B_MA8 MB_ADD8 MB_DATA8 DDR_B_D8 <11>
DDR_A_MA9 P27 D16 DDR_A_D9 DDR_B_MA9 T33 C20 DDR_B_D9
<10> DDR_A_MA9 MA_ADD9 MA_DATA9 DDR_A_D9 <10> <11> DDR_B_MA9 MB_ADD9 MB_DATA9 DDR_B_D9 <11>
DDR_A_MA10 AC28 F22 DDR_A_D10 DDR_B_MA10 AD32 C24 DDR_B_D10
<10> DDR_A_MA10 MA_ADD10 MA_DATA10 DDR_A_D10 <10> <11> DDR_B_MA10 MB_ADD10 MB_DATA10 DDR_B_D10 <11>
DDR_A_MA11 T30 D20 DDR_A_D11 DDR_B_MA11 T31 A25 DDR_B_D11
<10> DDR_A_MA11 MA_ADD11 MA_DATA11 DDR_A_D11 <10> <11> DDR_B_MA11 MB_ADD11 MB_DATA11 DDR_B_D11 <11>
DDR_A_MA12 P28 F15 DDR_A_D12 DDR_B_MA12 T32 A18 DDR_B_D12
<10> DDR_A_MA12 MA_ADD12 MA_DATA12 DDR_A_D12 <10> <11> DDR_B_MA12 MB_ADD12 MB_DATA12 DDR_B_D12 <11>
DDR_A_MA13 AG28 G15 DDR_A_D13 DDR_B_MA13 AJ33 C18 DDR_B_D13
<10> DDR_A_MA13 MA_ADD13 MA_DATA13 DDR_A_D13 <10> <11> DDR_B_MA13 MB_ADD13 MB_DATA13 DDR_B_D13 <11>
DDR_A_MA14 M29 G20 DDR_A_D14 DDR_B_MA14 P31 B24 DDR_B_D14
<10> DDR_A_MA14 MA_ADD14 MA_DATA14 DDR_A_D14 <10> <11> DDR_B_MA14 MB_ADD14 MB_DATA14 DDR_B_D14 <11>
DDR_A_MA15 P30 G22 DDR_A_D15 DDR_B_MA15 P33 A24 DDR_B_D15
<10> DDR_A_MA15 MA_ADD15 MA_DATA15 DDR_A_D15 <10> <11> DDR_B_MA15 MB_ADD15 MB_DATA15 DDR_B_D15 <11>
G23 DDR_A_D16 C26 DDR_B_D16
MA_DATA16 DDR_A_D16 <10> MB_DATA16 DDR_B_D16 <11>
D22 DDR_A_D17 A27 DDR_B_D17
MA_DATA17 DDR_A_D17 <10> MB_DATA17 DDR_B_D17 <11>
DDR_A_BS0 AE28 G26 DDR_A_D18 DDR_B_BS0 AE33 A30 DDR_B_D18
<10> DDR_A_BS0 MA_BANK0 MA_DATA18 DDR_A_D18 <10> <11> DDR_B_BS0 MB_BANK0 MB_DATA18 DDR_B_D18 <11>
DDR_A_BS1 AC29 F26 DDR_A_D19 DDR_B_BS1 AD33 B30 DDR_B_D19
<10> DDR_A_BS1 MA_BANK1 MA_DATA19 DDR_A_D19 <10> <11> DDR_B_BS1 MB_BANK1 MB_DATA19 DDR_B_D19 <11>
DDR_A_BS2 R29 E22 DDR_A_D20 DDR_B_BS2 R33 A26 DDR_B_D20

DDRIII CHANNEL B
<10> DDR_A_BS2 MA_BANK2 MA_DATA20 DDR_A_D20 <10> <11> DDR_B_BS2 MB_BANK2 MB_DATA20 DDR_B_D20 <11>
H22 DDR_A_D21 B26 DDR_B_D21

DDRIII CHANNEL A
MA_DATA21 DDR_A_D21 <10> MB_DATA21 DDR_B_D21 <11>
D24 DDR_A_D22 A29 DDR_B_D22
MA_DATA22 DDR_A_D22 <10> MB_DATA22 DDR_B_D22 <11>
H27 H25 DDR_A_D23 G33 C30 DDR_B_D23
MA_CHECK0 MA_DATA23 DDR_A_D23 <10> MB_CHECK0 MB_DATA23 DDR_B_D23 <11>
H29 H26 DDR_A_D24 H31 B32 DDR_B_D24
MA_CHECK1 MA_DATA24 DDR_A_D24 <10> MB_CHECK1 MB_DATA24 DDR_B_D24 <11>
L29 F27 DDR_A_D25 K32 C32 DDR_B_D25
MA_CHECK2 MA_DATA25 DDR_A_D25 <10> MB_CHECK2 MB_DATA25 DDR_B_D25 <11>
L28 E29 DDR_A_D26 L33 F31 DDR_B_D26
MA_CHECK3 MA_DATA26 DDR_A_D26 <10> MB_CHECK3 MB_DATA26 DDR_B_D26 <11>
F29 F30 DDR_A_D27 F32 F33 DDR_B_D27
MA_CHECK4 MA_DATA27 DDR_A_D27 <10> MB_CHECK4 MB_DATA27 DDR_B_D27 <11>
G29 E26 DDR_A_D28 G32 A31 DDR_B_D28
MA_CHECK5 MA_DATA28 DDR_A_D28 <10> MB_CHECK5 MB_DATA28 DDR_B_D28 <11>
J29 D26 DDR_A_D29 K31 B31 DDR_B_D29
MA_CHECK6 MA_DATA29 DDR_A_D29 <10> MB_CHECK6 MB_DATA29 DDR_B_D29 <11>
K30 G28 DDR_A_D30 K33 D31 DDR_B_D30
MA_CHECK7 MA_DATA30 DDR_A_D30 <10> MB_CHECK7 MB_DATA30 DDR_B_D30 <11>
D28 DDR_A_D31 E33 DDR_B_D31
MA_DATA31 DDR_A_D31 <10> MB_DATA31 DDR_B_D31 <11>
AJ28 DDR_A_D32 AM32 DDR_B_D32
MA_DATA32 DDR_A_D32 <10> MB_DATA32 DDR_B_D32 <11>
DDR_A_DQS0 E12 AJ26 DDR_A_D33 DDR_B_DQS0 B16 AM31 DDR_B_D33
<10> DDR_A_DQS0 MA_DQS_H0 MA_DATA33 DDR_A_D33 <10> <11> DDR_B_DQS0 MB_DQS_H0 MB_DATA33 DDR_B_D33 <11>
DDR_A_DQS#0 F12 AG25 DDR_A_D34 DDR_B_DQS#0 A15 AN29 DDR_B_D34
<10> DDR_A_DQS#0 MA_DQS_L0 MA_DATA34 DDR_A_D34 <10> <11> DDR_B_DQS#0 MB_DQS_L0 MB_DATA34 DDR_B_D34 <11>
DDR_A_DQS1 G17 AJ25 DDR_A_D35 DDR_B_DQS1 A21 AK28 DDR_B_D35
<10> DDR_A_DQS1 MA_DQS_H1 MA_DATA35 DDR_A_D35 <10> <11> DDR_B_DQS1 MB_DQS_H1 MB_DATA35 DDR_B_D35 <11>
DDR_A_DQS#1 H17 AK30 DDR_A_D36 DDR_B_DQS#1 B20 AL33 DDR_B_D36
<10> DDR_A_DQS#1 MA_DQS_L1 MA_DATA36 DDR_A_D36 <10> <11> DDR_B_DQS#1 MB_DQS_L1 MB_DATA36 DDR_B_D36 <11>
DDR_A_DQS2 E25 AH27 DDR_A_D37 DDR_B_DQS2 B28 AL32 DDR_B_D37
<10> DDR_A_DQS2 MA_DQS_H2 MA_DATA37 DDR_A_D37 <10> <11> DDR_B_DQS2 MB_DQS_H2 MB_DATA37 DDR_B_D37 <11>
DDR_A_DQS#2 F25 AF25 DDR_A_D38 DDR_B_DQS#2 A28 AL30 DDR_B_D38
<10> DDR_A_DQS#2 MA_DQS_L2 MA_DATA38 DDR_A_D38 <10> <11> DDR_B_DQS#2 MB_DQS_L2 MB_DATA38 DDR_B_D38 <11>
DDR_A_DQS3 E28 AF23 DDR_A_D39 DDR_B_DQS3 D33 AM29 DDR_B_D39
C <10> DDR_A_DQS3 MA_DQS_H3 MA_DATA39 DDR_A_D39 <10> <11> DDR_B_DQS3 MB_DQS_H3 MB_DATA39 DDR_B_D39 <11> C
DDR_A_DQS#3 F28 AG23 DDR_A_D40 DDR_B_DQS#3 D32 AM28 DDR_B_D40
<10> DDR_A_DQS#3 MA_DQS_L3 MA_DATA40 DDR_A_D40 <10> <11> DDR_B_DQS#3 MB_DQS_L3 MB_DATA40 DDR_B_D40 <11>
DDR_A_DQS4 AG26 AJ23 DDR_A_D41 DDR_B_DQS4 AN30 AN27 DDR_B_D41
<10> DDR_A_DQS4 MA_DQS_H4 MA_DATA41 DDR_A_D41 <10> <11> DDR_B_DQS4 MB_DQS_H4 MB_DATA41 DDR_B_D41 <11>
DDR_A_DQS#4 AH26 AF20 DDR_A_D42 DDR_B_DQS#4 AM30 AN25 DDR_B_D42
<10> DDR_A_DQS#4 MA_DQS_L4 MA_DATA42 DDR_A_D42 <10> <11> DDR_B_DQS#4 MB_DQS_L4 MB_DATA42 DDR_B_D42 <11>
DDR_A_DQS5 AH22 AF19 DDR_A_D43 DDR_B_DQS5 AN26 AL24 DDR_B_D43
<10> DDR_A_DQS5 MA_DQS_H5 MA_DATA43 DDR_A_D43 <10> <11> DDR_B_DQS5 MB_DQS_H5 MB_DATA43 DDR_B_D43 <11>
DDR_A_DQS#5 AG22 AK24 DDR_A_D44 DDR_B_DQS#5 AM26 AL28 DDR_B_D44
<10> DDR_A_DQS#5 MA_DQS_L5 MA_DATA44 DDR_A_D44 <10> <11> DDR_B_DQS#5 MB_DQS_L5 MB_DATA44 DDR_B_D44 <11>
DDR_A_DQS6 AG15 AF22 DDR_A_D45 DDR_B_DQS6 AL20 AN28 DDR_B_D45
<10> DDR_A_DQS6 MA_DQS_H6 MA_DATA45 DDR_A_D45 <10> <11> DDR_B_DQS6 MB_DQS_H6 MB_DATA45 DDR_B_D45 <11>
DDR_A_DQS#6 AH15 AJ20 DDR_A_D46 DDR_B_DQS#6 AM20 AL26 DDR_B_D46
<10> DDR_A_DQS#6 MA_DQS_L6 MA_DATA46 DDR_A_D46 <10> <11> DDR_B_DQS#6 MB_DQS_L6 MB_DATA46 DDR_B_D46 <11>
DDR_A_DQS7 AJ11 AG20 DDR_A_D47 DDR_B_DQS7 AM14 AM25 DDR_B_D47
<10> DDR_A_DQS7 MA_DQS_H7 MA_DATA47 DDR_A_D47 <10> <11> DDR_B_DQS7 MB_DQS_H7 MB_DATA47 DDR_B_D47 <11>
DDR_A_DQS#7 AK12 AG19 DDR_A_D48 DDR_B_DQS#7 AN14 AN23 DDR_B_D48
<10> DDR_A_DQS#7 MA_DQS_L7 MA_DATA48 DDR_A_D48 <10> <11> DDR_B_DQS#7 MB_DQS_L7 MB_DATA48 DDR_B_D48 <11>
J27 AF17 DDR_A_D49 J33 AL22 DDR_B_D49
MA_DQS_H8 MA_DATA49 DDR_A_D49 <10> MB_DQS_H8 MB_DATA49 DDR_B_D49 <11>
J26 AG14 DDR_A_D50 H32 AN18 DDR_B_D50
MA_DQS_L8 MA_DATA50 DDR_A_D50 <10> MB_DQS_L8 MB_DATA50 DDR_B_D50 <11>
AF14 DDR_A_D51 AM18 DDR_B_D51
MA_DATA51 DDR_A_D51 <10> MB_DATA51 DDR_B_D51 <11>
AK20 DDR_A_D52 AN24 DDR_B_D52
MA_DATA52 DDR_A_D52 <10> MB_DATA52 DDR_B_D52 <11>
E20 AH19 DDR_A_D53 A22 AM24 DDR_B_D53
MA_CLK_H0 MA_DATA53 DDR_A_D53 <10> MB_CLK_H0 MB_DATA53 DDR_B_D53 <11>
E19 AF15 DDR_A_D54 A23 AN19 DDR_B_D54
MA_CLK_L0 MA_DATA54 DDR_A_D54 <10> MB_CLK_L0 MB_DATA54 DDR_B_D54 <11>
D18 AK14 DDR_A_D55 C22 AL18 DDR_B_D55
MA_CLK_H1 MA_DATA55 DDR_A_D55 <10> MB_CLK_H1 MB_DATA55 DDR_B_D55 <11>
F19 AH12 DDR_A_D56 B22 AN16 DDR_B_D56
MA_CLK_L1 MA_DATA56 DDR_A_D56 <10> MB_CLK_L1 MB_DATA56 DDR_B_D56 <11>
P26 AG12 DDR_A_D57 AD31 AM16 DDR_B_D57
MA_CLK_H2 MA_DATA57 DDR_A_D57 <10> MB_CLK_H2 MB_DATA57 DDR_B_D57 <11>
M26 AF12 DDR_A_D58 AD30 AM12 DDR_B_D58
MA_CLK_L2 MA_DATA58 DDR_A_D58 <10> MB_CLK_L2 MB_DATA58 DDR_B_D58 <11>
W27 AF11 DDR_A_D59 AB31 AN12 DDR_B_D59
MA_CLK_H3 MA_DATA59 DDR_A_D59 <10> MB_CLK_H3 MB_DATA59 DDR_B_D59 <11>
W26 AJ14 DDR_A_D60 AB30 AN17 DDR_B_D60
MA_CLK_L3 MA_DATA60 DDR_A_D60 <10> MB_CLK_L3 MB_DATA60 DDR_B_D60 <11>
M_CLK_DDR1 AB27 AJ12 DDR_A_D61 M_CLK_DDR3 AB33 AL16 DDR_B_D61
<10> M_CLK_DDR1 MA_CLK_H4 MA_DATA61 DDR_A_D61 <10> <11> M_CLK_DDR3 MB_CLK_H4 MB_DATA61 DDR_B_D61 <11>
M_CLK_DDR#1 AB26 AH11 DDR_A_D62 M_CLK_DDR#3 AB32 AL14 DDR_B_D62
<10> M_CLK_DDR#1 MA_CLK_L4 MA_DATA62 DDR_A_D62 <10> <11> M_CLK_DDR#3 MB_CLK_L4 MB_DATA62 DDR_B_D62 <11>
M_CLK_DDR0 Y28 AG11 DDR_A_D63 M_CLK_DDR2 AA32 AN13 DDR_B_D63
<10> M_CLK_DDR0 MA_CLK_H5 MA_DATA63 DDR_A_D63 <10> <11> M_CLK_DDR2 MB_CLK_H5 MB_DATA63 DDR_B_D63 <11>
M_CLK_DDR#0 Y27 M_CLK_DDR#2 AA33
<10> M_CLK_DDR#0 MA_CLK_L5 <11> M_CLK_DDR#2 MB_CLK_L5
AH17 MA_CLK_H6 AN21 MB_CLK_H6
AG17 G14 DDR_A_DM0 AM21
MA_CLK_L6 MA_DM0 DDR_A_DM0 <10> MB_CLK_L6
AK18 H19 DDR_A_DM1 AN22 D14 DDR_B_DM0
MA_CLK_H7 MA_DM1 DDR_A_DM1 <10> MB_CLK_H7 MB_DM0 DDR_B_DM0 <11>
AJ17 E23 DDR_A_DM2 AM22 A20 DDR_B_DM1
MA_CLK_L7 MA_DM2 DDR_A_DM2 <10> MB_CLK_L7 MB_DM1 DDR_B_DM1 <11>
E27 DDR_A_DM3 C28 DDR_B_DM2
MA_DM3 DDR_A_DM3 <10> MB_DM2 DDR_B_DM2 <11>
AJ27 DDR_A_DM4 C33 DDR_B_DM3
MA_DM4 DDR_A_DM4 <10> MB_DM3 DDR_B_DM3 <11>
DDR_CKE0_DIMMA M28 AK22 DDR_A_DM5 DDR_CKE2_DIMMB P32 AN31 DDR_B_DM4
B <10> DDR_CKE0_DIMMA MA_CKE0 MA_DM5 DDR_A_DM5 <10> <11> DDR_CKE2_DIMMB MB_CKE0 MB_DM4 DDR_B_DM4 <11> B
DDR_CKE1_DIMMA M30 AK16 DDR_A_DM6 DDR_CKE3_DIMMB N33 AK26 DDR_B_DM5
<10> DDR_CKE1_DIMMA MA_CKE1 MA_DM6 DDR_A_DM6 <10> <11> DDR_CKE3_DIMMB MB_CKE1 MB_DM5 DDR_B_DM5 <11>
AL12 DDR_A_DM7 AN20 DDR_B_DM6
MA_DM7 DDR_A_DM7 <10> MB_DM6 DDR_B_DM6 <11>
H30 AN15 DDR_B_DM7
MA_DM8 MB_DM7 DDR_B_DM7 <11>
M_ODT0 AG29 M_ODT2 AH33 H33
<10> M_ODT0 MA0_ODT0 <11> M_ODT2 MB0_ODT0 MB_DM8
M_ODT1 AJ30 M_ODT3 AK32
<10> M_ODT1 MA0_ODT1 <11> M_ODT3 MB0_ODT1
AF27 MA1_ODT0 AH31 MB1_ODT0
AJ29 MA1_ODT1 AK31 MB1_ODT1

DDR_CS0_DIMMA# AF29 DDR_CS2_DIMMB# AF31

<10> DDR_CS0_DIMMA# MA0_CS_L0 <11> DDR_CS2_DIMMB# MB0_CS_L0
DDR_CS1_DIMMA# AH30 DDR_CS3_DIMMB# AJ32
<10> DDR_CS1_DIMMA# MA0_CS_L1 <11> DDR_CS3_DIMMB# MB0_CS_L1
AE29 MA1_CS_L0 AF33 MB1_CS_L0
AH29 MA1_CS_L1 AK33 MB1_CS_L1

DDR_A_RAS# AC27 +1.5V DDR_B_RAS# AF32

<10> DDR_A_RAS# MA_RAS_L <11> DDR_B_RAS# MB_RAS_L
DDR_A_CAS# AF30 DDR_B_CAS# AH32
<10> DDR_A_CAS# MA_CAS_L <11> DDR_B_CAS# MB_CAS_L
DDR_A_WE# AE27 DDR_A_EVENT# RU1 2 1 1K_0402_5% DDR_B_WE# AG33
<10> DDR_A_WE# MA_WE_L <11> DDR_B_WE# MB_WE_L
DDR_B_EVENT# 2 1
RU2 1K_0402_5%
<10> DDR_A_RST# DDR_A_RST# L27 <11> DDR_B_RST# DDR_B_RST# L32
DDR_A_EVENT# MA_RESET_L DDR_B_EVENT# MB_RESET_L
<10> DDR_A_EVENT# M32 FREE|MA_EVENT_L <11> DDR_B_EVENT# M33 FREE|MB_EVENT_L
+3VS

ASB2_BGA812 SB_MEMHOT# RU68 2 1 2.2K_0402_5% ASB2_BGA812

+1.5V +1.5V +3VS

1

RU64 RU65 RU66

2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
A A
2 2

QU6

<18> CPU_MEMHOT# 1 3
MMBT3904_NL_SOT23-3
DDR_A_EVENT#
DDR_A_EVENT# <10>
DELL CONFIDENTIAL/PROPRIETARY
2

QU7
Compal Electronics, Inc.
1 3 DDR_B_EVENT# PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
DDR_B_EVENT# <11> TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
MMBT3904_NL_SOT23-3
ASB2 DDRIII MEMORY I/F
2

QU8 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
SB_MEMHOT# PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
1 3
MMBT3904_NL_SOT23-3
SB_MEMHOT# <16> LA-6132P
Date: Tuesday, May 04, 2010 Sheet 7 of 45
5 4 3 2 1
 5 4 3 2 1

LAYOUT: ROUTE VDDA TRACE APPROX.

50 mils WIDE (USE 2x25 mil TRACES TO +1.5V +1.5V
EXIT BALL FIELD) AND 500 mils LONG.
+1.1VS

1K_0402_5%
1

1
LU1

3300P_0402_50V7K~D
0.22U_0603_10V7K~D
4.7U_0603_6.3V6K
+1.5V +2.5VDDA 1 2 +CPU_VDDA RU63
1 FBM_L11_201209_300L_0805 RU62
+CPU_VDDR 1K_0402_5%
1 1 1
1 2 CPU_VLDT_SENSE + CU1 UU1D K325@ 1 2 CPU_PROCHOT#_R
<17> SB_PROCHOT#

2
@ RU57
1 10_0402_5%
2 CPU_VDDIO_FB_H CU2 CU3 CU4 SB_SMB_CLK3 RU67 0_0402_5%
@ RU58
1 10_0402_5%
2 CPU_VDDR_SENSE 150U_B2_6.3VM_R45M SB_SMB_DAT3
@ RU59 10_0402_5% 2 2 2 2
A8 VDDA_1
B8 VDDA_2
+1.5V
D 1 2 3900P_0402_50V7K~D CPU_CLKIN_SC_P A6 +1.5V D
<16> CLK_HT_CPU_P CLKIN_H

2.2K_0402_5%
CU5 CPU_CLKIN_SC_N A7 M31 CPU_CORE_TYPE TU1
CLKIN_L RSVD|CORE_TYPE

1
+3VS

10K_0402_5%
4.7K_0402_5%
+1.5V

2
RU5 +1.5V
1K_0402_5%

RU3
RU4 169_0402_1%~D CPU_PWRGD D10 C1 CPU_SVC_R
PWROK SVC
1

MISC
@ LDT_STOP# E9 B2 CPU_SVD_R
LDTSTOP_L SVD

1K_0402_5%

300_0402_5%~D
LDT_RST# F9
2 2

2
RESET_L

1
RU6 RU7 <16> CLK_HT_CPU_N 1 2

2 1
CU6 3900P_0402_50V7K~D @ RU10 RU11
@ QU2 0_0402_5% 1 RU9 2 CPU_SIC AN4 AL6 THERMDC_CPU
<18> SB_SMB_CLK3
2

2
CPU_ALERT# SMB_ALERT# RU12 2 CPU_SID SIC THERMDC
3 1 SMB_ALERT# <13,18,26> <18> SB_SMB_DAT3
0_0402_5% 1 AN5 SID THERMDA AM5 THERMDA_CPU QU1
MMBT3904_NL_SOT23-3 @ AM2 3 1 H_THERMTRIP# <18>

2
CPU_ALERT# RSVD_SA0 MMBT3904_NL_SOT23-3
AN3 ALERT_L
TSI to SB SMBUS3 AK6 CPU_THERMTRIP#_R
THERMTRIP_L
+1.5V
PROCHOT_L AN6 CPU_PROCHOT#_R 1 2 CPU_PROCHOT# CPU_PROCHOT# <16>
+1.5V RU13 0_0402_5%
2.2K_0402_5%
1
1K_0402_5%

CPU_TDI AM8 AN7 CPU_TDO

TDI TDO
1

CPU_TRST# AL8
RU15 CPU_TCK TRST_L
AK8 TCK
RU14 CPU_TMS AN8 H9 CPU_DBRDY
CPU_DBREQ# TMS DBRDY
G9
2 2

DBREQ_L
2

QU4 CPU_VDD0_RUN_FB_L D2 AM6 RSVD3 TU2

<42> CPU_VDD0_RUN_FB_L VSS_SENSE RSVD3 +1.5V
CPU_SID 3 1 EC_SMB_DA2 EC_SMB_DA2 <20,26,28> CPU_VLDT_SENSE E2
MMBT3904_NL_SOT23-3 CPU_VDD0_RUN_FB_H VLDT_SENSE
<42> CPU_VDD0_RUN_FB_H E1 VDD_SENSE
2 1 CPU_VDDNB_RUN_FB_H D1 AJ9 CPU_PRESENT_L TU3 CPU_PRESENT_L RU61 1 2 1K_0402_5%
<42> CPU_VDDNB_RUN_FB_H VDDNB_SENSE CPU_PRESENT_L
DU1 CH751H-40PT_SOD323-2 EC is PU to 3VALW CPU_VDDIO_FB_H D3
CPU_VDDR_SENSE VDDIO_SENSE
C2 VDDR_SENSE
+1.5V EC_SMB_CK2 PLACE THEM CLOSE TO VLDT
EC_SMB_CK2 <20,26,28>
+CPU_M_VREF
CPU WITHIN 1"CU72
2.2K_0402_5%

C 0.1U_0402_16V7K A11 V10 CPU_HTREF1 44.2_0402_1%~D 1 RU18 2 C

M_VREF HTREF1 +1.1VS
1

+1.5V 2 1 M_ZP AM9 V9 CPU_HTREF0 44.2_0402_1%~D 1 RU19 2

M_ZN_H HTREF0
1 RU21 2 39.2_0402_1% M_ZN AN9 M_ZN_L place them to CPU within 1.5"
1K_0402_5%

RU20 @
1

CPU_TEST25_H_BYPASSCLK_H A9 B10 CPU_TEST29_H_FBCLKOUT_P route as differential

2 2

CPU_TEST25_L_BYPASSCLK_L B9 BYPASSCLK_H FBCLKOUT_H

RU22
BYPASSCLK_L FBCLKOUT_L A10 CPU_TEST29_L_FBCLKOUT_N RU23 1 2 as short as possible
TU21 CPU_VDD0_RUN_FB_L CPU_TEST19_PLLTEST0 A5 80.6_0402_1%~D testpoint under package
QU5 CPU_VDD0_RUN_FB_H CPU_TEST18_PLLTEST1 PLLTEST0 +1.5V
TU22 B6
2

CPU_SIC CPU_VDDNB_RUN_FB_H PLLTEST1 CPU_TEST24_SCANCLK1

3 1 TU23 SCANCLK1 AK7
MMBT3904_NL_SOT23-3 AG8 CPU_TEST23_TSTUPD CPU_TEST25_H_BYPASSCLK_HRU24 1 2 510_0402_1%
CPU_TEST9_ANALOGIN TSTUPD CPU_TEST22_SCANSHIFTEN CPU_TEST26_BURNIN_L RU25 1 1K_0402_5%
2 1 Place close to CPU G8 ANALOGIN SCANSHIFTEN AK9 2
DU2 CH751H-40PT_SOD323-2 AH9 CPU_TEST21_SCANEN
SCANEN CPU_TEST20_SCANCLK2
SCANCLK2 AM7
TU4 CPU_TEST17_BP3 F8 CPU_TEST27_SINGLECHAIN RU26 1 2 1K_0402_5%
+1.5VS CPU_TEST16_BP2 BP3
TU5 C8 BP2
CPU_TEST15_BP1 D9 G11 CPU_TEST28_H_PLLCHRZ_P TU6 RU27 1 @ 2 300_0402_5%~D
CPU_TEST14_BP0 BP1 PLLCHRZ_H CPU_TEST28_L_PLLCHRZ_N TU7
E8 BP0 PLLCHRZ_L H11
1

RU60 @ AJ8 CPU_TEST27_SINGLECHAIN

RU28 SINGLECHAIN CPU_TEST26_BURNIN_L
<26,42> VGATE 1 2 BURNIN_L AM4
0_0402_5% 300_0402_5%~D TU8 CPU_TEST7_ANALOG_T C6 D7 CPU_TEST10_ANALOGOUT CPU_TEST25_L_BYPASSCLK_L RU29 1 2 510_0402_1%
CPU_TEST6_DIECRACKMON ANALOG_T ANALOGOUT CPU_TEST8_DIG_T TU10 CPU_TEST21_SCANEN RU30 1K_0402_5%
TU9 AH7 DIECRACKMON DIG_T B5 1 2
TU11 CPU_TEST3 AK5 CPU_TEST20_SCANCLK2 RU31 1 2 1K_0402_5%
2

CPU_PWRGD CPU_TEST2 GATE0 CPU_TEST24_SCANCLK1 RU32 1K_0402_5%

<16> CPU_PWRGD TU12 AJ7 DRAIN0 1 2
CPU_TEST23_TSTUPD RU33 1 2 1K_0402_5%
AG9 CPU_TEST22_SCANSHIFTEN RU34 1 2 1K_0402_5%
+1.5VS M_TEST
+1.5VS
1

ASB2_BGA812 CPU_TEST15_BP1 RU35 1 @ 2 300_0402_5%~D

2.2K_0402_5%

RU36 CPU_TEST14_BP0 RU37 1 @ 2 300_0402_5%~D

1K_0402_5%

1K_0402_5%

300_0402_5%~D
1

B @ CPU_TEST18_PLLTEST1 RU41 1 2 1K_0402_5% B

CPU_TEST19_PLLTEST0 RU42 1 2 1K_0402_5%
2

LDT_STOP# RU38 RU39 RU40

<13,16> LDT_STOP#
CPU_TEST9_ANALOGIN RU43 1 2 0_0402_5%
2

+1.5VS CPU_SVC_R 1 RU44

2 CPU_SVC CPU_SVC <42>
0_0402_5%
CPU_SVD_R 1 RU45 2 CPU_SVD CPU_SVD <42>
1

0_0402_5% +1.1VS VLDT

RU46 CPU_PWRGD 1 RU47 2 CPU_PWRGD_SVID_REG CPU_PWRGD_SVID_REG <42>
300_0402_5%~D 0_0402_5% CPU_TEST10_ANALOGOUT RU48 1 @ 2 300_0402_5%~D
VID Override Circuit
2

LDT_RST#
<16> LDT_RST#
Layout : Resistor placed close to CPU, trace reference to GND, +1.5V LAYOUT:PLACE CLOSE TO CPU
keep spacing 15mil to other signal. +3VS

0.01U_0402_16V7K 0.1U_0402_16V7K
UT5 @
HDT Connector
2

1K_0402_1%~D

1
+3VALW

0.1U_0402_16V7K
1 THERMDA_CPU
+1.5V RU49 CU7 EC_SMB_CK2
Close to LDT_RST# trace 1 1 VDD SMCLK 8 EC_SMB_CK2 <20,26,28>
@ CT1
5

UU6 2 +CPU_M_VREF @ CT2 EC_SMB_DA2

2 7 EC_SMB_DA2 <20,26,28>
1

SB_PWRGD 2 @ 2 2200P_0402_50V7K DP SMDATA

P

<13,18,26> SB_PWRGD B 2
4 HDT_RST# THERMDC_CPU 3 6 SMB_ALERT#
Y DN ALERT# SMB_ALERT# <13,18,26>
RU50

RU51

RU52

RU53

RU54

RU55

@ @ @ @ @ LDT_RST# 1 A
G

1000P_0402_50V7K
1K_0402_1%~D

1 1 THERM# 4 5
THERM# GND
2

JPTU1 CONN@ NC7SZ08P5X_NL_SC70-5

3
1

1
220_0402_5%~D

220_0402_5%~D

220_0402_5%~D

220_0402_5%~D

300_0402_5%~D

300_0402_5%~D

@ CU8 CU9 RT1 @

1 2 RU56
3 4 +3VS 1 2
2 2 10K_0402_5%
A 5 6 EMC1402-1-ACZL-TR_MSOP8 A
CPU_DBREQ# RT2 @
1

CPU_DBRDY 7 8 THERM# CPU_PROCHOT#

1 2 SMBus Address: 1001110X (b)
2

CPU_TCK 9 10 0_0402_5%
CPU_TMS 11 12
CPU_DBREQ# CPU_TDI 13 14
CPU_DBRDY CPU_TRST# 15 16
CPU_TCK
CPU_TMS
CPU_TDO 17
19
18
20
DELL CONFIDENTIAL/PROPRIETARY
CPU_TDI +1.5V
21 22 HDT_RST# Compal Electronics, Inc.
CPU_TRST# 23 24 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
CPU_TDO 26 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ASB2 CTRL & EMC1402
SAMTEC_ASP-68200-07 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 8 of 45
5 4 3 2 1
 5 4 3 2 1

CPU BOTTOMSIDE DECOUPLING

+CPU_CORE UU1G K325@ UU1H K325@
+CPU_CORE

UU1E K325@ B1 W19 AM19 AK15

VSS_1 VSS_45 VSS_207 VSS_191

180P_0402_50V8J~D
0.22U_0603_10V7K~D
4.7U_0603_6.3V6K
18A N2 VSS_28 VSS_44 W1 AF7 VSS_167 VSS_192 AK17

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
1 1 1 1 1 1 1 N22 VSS_29 VSS_43 V20 AF26 VSS_166 VSS_193 AK19
D4 VDD_1 VDD_85 AE12 N23 VSS_30 VSS_42 V18 AE7 VSS_165 VSS_194 AK21
CU10 CU11 CU15 CU12 CU16 CU17 CU13 D5 AD9 B13 M11 AF8 AA2
+VDDNB VDD_2 VDD_84 VSS_2 VSS_26 VSS_168 VSS_126
D6 VDD_3 VDD_83 AE21 B15 VSS_3 VSS_25 L8 AF9 VSS_169 VSS_127 AA22
+CPU_CORE 2 2 2 2 2 2 2
E5 VDD_4 VDD_82 AD21 B17 VSS_4 VSS_41 V15 AG1 VSS_170 VSS_128 AA23
E6 VDD_5 VDD_81 AD18 M21 VSS_27 VSS_24 L4 AG2 VSS_171 VSS_195 AK23
D E7 AD14 B19 L30 AG27 AA4 D
VDD_6 VDD_80 VSS_5 VSS_23 VSS_172 VSS_129
330U_X_2VM_R6M

330U_X_2VM_R6M

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
1 1 1 F5 VDD_7 VDD_79 AD12 B21 VSS_6 VSS_22 L26 AG4 VSS_173 VSS_130 AA9
330U_X_2VM_R6M

1 1 1 F6 VDD_8 VDD_78 AD11 B23 VSS_7 VSS_68 L24 AG5 VSS_174 VSS_131 AB10
+CPU_CORE CU20 CU21 CU22 F7 AC5 B27 L23 AG6 AB12
+ + + VDD_9 VDD_77 VSS_8 VSS_69 VSS_175 VSS_132
CU18

CU14

CU19

H7 VDD_10 VDD_76 AE18 B29 VSS_9 VSS_70 L22 AG7 VSS_176 VSS_133 AB21
2 2 2
H8 VDD_11 VDD_75 AC24 B33 VSS_10 VSS_71 L21 AE4 VSS_164 VSS_134 AB22

180P_0402_50V8J~D
0.22U_0603_10V7K~D
4.7U_0603_6.3V6K
J8 VDD_12 VDD_74 AC12 C10 VSS_11 VSS_72 L2 AE25 VSS_163 VSS_135 AB23
2 2 @2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
1 1 1 1 1 1 1 E4 VDD_13 VDD_73 AC10 P10 VSS_31 VSS_73 L12 AE24 VSS_162 VSS_136 AB24
J10 VDD_14 VDD_72 AB13 P14 VSS_32 VSS_74 L10 AE22 VSS_161 VSS_196 AK25
CU23 CU24 CU25 CU26 CU27 CU28 CU29 J12 AB11 P16 L1 AE20 AK27
VDD_15 VDD_71 VSS_33 VSS_75 VSS_160 VSS_197
J14 VDD_16 VDD_70 AE14 P19 VSS_34 VSS_76 K9 AE2 VSS_159 VSS_198 AK29
2 2 2 2 2 2 2
J18 VDD_17 VDD_69 AA24 P7 VSS_35 VSS_77 M6 AE16 VSS_158 VSS_199 AJ5
J20 VDD_18 VDD_68 AA12 C31 VSS_12 VSS_78 K24 AE13 VSS_157 VSS_200 AH6
J21 VDD_19 VDD_67 AA10 D11 VSS_13 VSS_79 K22 AH14 VSS_177 VSS_201 AL31

POWER1
J23 VDD_20 VDD_66 Y19 D13 VSS_14 VSS_80 K16 AE11 VSS_156 VSS_202 AM1
J9 Y16 D15 M22 AE10 AM13

GND1
VDD_21 VDD_65 VSS_15 VSS_81 VSS_155 VSS_203
K10 VDD_22 VDD_64 Y14 R1 VSS_36 VSS_82 K13 AE1 VSS_154 VSS_137 AB7
+1.5V

GND2
K12 VDD_23 VDD_63 W5 D17 VSS_16 VSS_83 M24 AD24 VSS_153 VSS_138 AC1
K14 VDD_24 VDD_62 W20 D19 VSS_17 VSS_84 K11 AD23 VSS_152 VSS_205 AM15
K18 VDD_25 VDD_61 W18 D21 VSS_18 VSS_85 M23 AD22 VSS_151 VSS_206 AM17
10U_0603_6.3V6M

180P_0402_50V8J~D
0.1U_0402_16V7K

0.01U_0402_16V7K
0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D
K20 VDD_26 VDD_60 W15 D23 VSS_19 VSS_86 J7 AH20 VSS_178 VSS_139 AC11
22U_0805_6.3V6M~D

1 1 1 1 1 1 1 1 K21 VDD_27 VDD_59 AE23 D25 VSS_20 VSS_87 W16 AH23 VSS_179 VSS_140 AC13
K23 VDD_28 VDD_58 V24 D27 VSS_21 VSS_88 J4 AH25 VSS_180 VSS_141 AC2
CU30 CU31 CU32 CU33 CU34 CU35 CU36 CU37 N4 V19 R15 W14 AH28 AC21
@ VDD_29 VDD_57 VSS_37 VSS_89 VSS_181 VSS_142
L11 VDD_30 VDD_56 V16 R18 VSS_38 VSS_90 J32 AD20 VSS_150 VSS_143 AC22
2 2 2 2 2 2 2 2
L13 VDD_31 VDD_55 V14 R2 VSS_39 VSS_91 J30 AD16 VSS_149 VSS_208 AM23
L7 VDD_32 VDD_54 T20 R20 VSS_40 VSS_92 M13 AD13 VSS_148 VSS_209 AM27
L9 VDD_33 VDD_53 T18 D29 VSS_46 VSS_93 J28 AD10 VSS_147 VSS_210 AM33
M10 VDD_34 VDD_52 T15 D30 VSS_47 VSS_94 U8 AC9 VSS_146 VSS_211 AN2
M12 VDD_35 VDD_51 T10 D8 VSS_48 VSS_95 J25 AC8 VSS_145 VSS_212 AN32
R4 VDD_36 VDD_50 R5 E30 VSS_49 VSS_96 U4 A2 VSS_214 VSS_215 AM11
+1.5V M5 R19 E32 J24 AC23
C VDD_37 VDD_49 VSS_50 VSS_97 VSS_144 C
N11 VDD_38 VDD_48 R16 F14 VSS_51 VSS_98 U7 AH5 VSS_182
N24 VDD_39 VDD_47 R14 F17 VSS_52 VSS_99 U2 AJ1 VSS_183
10U_0603_6.3V6M

180P_0402_50V8J~D
0.1U_0402_16V7K
0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

W4 VDD_40 VDD_46 AC4 R8 VSS_53 VSS_100 J2 AJ15 VSS_184

22U_0805_6.3V6M~D

1 1 1 1 1 1 1 N9 VDD_41 VDD_45 P24 T14 VSS_54 VSS_101 J16 W2 VSS_116

P15 VDD_42 VDD_44 P20 T16 VSS_55 VSS_102 J13 A32 VSS_213
CU38 CU39 CU40 CU41 CU42 CU43 CU44 P18 F20 J11 W8
@ VDD_43 VSS_56 VSS_103 VSS_117
T19 VSS_57 VSS_104 J1 Y10 VSS_118
2 2 2 2 2 2 2
T24 VSS_58 VSS_105 H6 Y15 VSS_119
T9 VSS_59 VSS_106 H5 Y18 VSS_120
ASB2_BGA812 U1 H28 AJ19
VSS_60 VSS_107 VSS_185
F23 VSS_61 VSS_108 H23 AJ2 VSS_186
VLDT already check with N1 H20 AJ22
AMD need 1.1V VSS_62 VSS_109 VSS_187
G1 VSS_63 VSS_110 J22 AJ4 VSS_188
G19 VSS_64 VSS_111 M9 Y20 VSS_121
G2 VSS_65 VSS_112 G4 Y24 VSS_122
UU1F K325@ G25 G30 AK11
+1.5V +1.1VS VSS_66 VSS_113 VSS_189
G27 VSS_67 VSS_114 N12 AK13 VSS_190
N10 VSS_115 Y7 VSS_123
M27 VDDIO_1 VLDT_A_1 F1 AA1 VSS_124
3A Y26 F2 1.5A AA11
Place close to CPU U26
VDDIO_2
VDDIO_3
VLDT_A_2
VLDT_A_3 F3
ASB2_BGA812
VSS_125
N32 VDDIO_4 VLDT_A_4 F4
U32 VDDIO_5 VLDT_B_1 AL1
+CPU_VDDR N30 AL2 ASB2_BGA812
VDDIO_6 VLDT_B_2
P29 VDDIO_7 VLDT_B_3 AL3
0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

R28 VDDIO_8 VLDT_B_4 AL4

1 1 1 1 1 1 R30 VDDIO_9
R32 +CPU_VDDR
CU45 CU46 CU47 CU48 CU49 CU50 VDDIO_10
U29 VDDIO_11 VDDR_1 A12
U30 VDDIO_12 VDDR_2 B12
2 2 2 2 2 2
W28 VDDIO_13 VDDR_3 C12 0.9V, 1.5A
W30 VDDIO_14 VDDR_4 D12
B W32 AK10 B
VDDIO_15 VDDR_5
Y29 VDDIO_16 VDDR_6 AL10
+1.1VS +1.1VS AA30 AM10
VDDIO_17 VDDR_7
AB28 AN10

POWER2
VDDIO_18 VDDR_8
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

180P_0402_50V8J~D

180P_0402_50V8J~D
0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

AE32 +VDDNB
VDDIO_19
22U_0805_6.3V6M~D

1 1 1 1 1 1 1 1 1 1 1 AC30 VDDIO_20 0.9V,4A

AC32 VDDIO_21 VDDNB_1 A3
CU51 CU52 CU53 CU54 CU55 CU56 CU57 CU58 CU59 CU60 CU61 AE26 A4
@ @ @ @ VDDIO_22 VDDNB_2
AE30 VDDIO_23 VDDNB_3 B3
2 2 2 2 2 2 2 2 2 2 2
AF28 VDDIO_24 VDDNB_4 B4
AG30 VDDIO_25 VDDNB_5 C3
AG32 VDDIO_26 VDDNB_6 C4
AD25 VDDIO_27
AA25 +CPU_VDDR
VDDIO_28
AC25 VDDIO_29 PROGEN_L B11
V25 VDDIO_30
P25 VDDIO_31
Placement need check N25 G7
VDDIO_32 FREE_1
M25 VDDIO_33 FREE_2 B7
K25 VDDIO_34 FREE_3 AH8
L25 AJ6
DECOUPLING BETWEEN PROCESSOR AND DIMMs T25
VDDIO_35
VDDIO_36
FREE_4
FREE_5 B25
Y25 VDDIO_37 FREE_6 AM3
AB25 AN11
PLACE CLOSE TO PROCESSOR AS POSSIBLE VDDIO_38 FREE_7
FREE_8 P9
FREE_9 P8

+1.5V
180P_0402_50V8J~D

180P_0402_50V8J~D

180P_0402_50V8J~D

180P_0402_50V8J~D
0.22U_0603_10V7K~D

0.22U_0603_10V7K~D
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

ASB2_BGA812
1 1 1 1 1 1 1 1 1 1
CU68

CU69

CU70

CU71

A CU62 CU63 CU64 CU65 CU66 CU67 A

2 2 2 2 2 2 2 2 2 2

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
Need discuss with AMD TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ASB2 PWR & GND
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Monday, May 03, 2010 Sheet 9 of 45
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V
JDIMMA
DDR_A_MA0 +V_DDR_REF_DQ 1 2
<7> DDR_A_MA0 VREF_DQ VSS1 +1.5V +V_DDR_REF_DQ +1.5V +V_DDR_REF_CA
DDR_A_MA1 3 4 DDR_A_D4
<7> DDR_A_MA1 VSS2 DQ4

2.2U_0603_6.3V6K

0.01U_0402_16V7K

1000P_0402_50V7K
DDR_A_MA2 DDR_A_D0 5 6 DDR_A_D5
<7> DDR_A_MA2 DQ0 DQ5
DDR_A_MA3 DDR_A_D1 7 8
<7> DDR_A_MA3 DQ1 VSS3

1
DDR_A_MA4 1 1 1 9 10 DDR_A_DQS#0
<7> DDR_A_MA4 VSS4 DQS#0
DDR_A_MA5 DDR_A_DM0 11 12 DDR_A_DQS0 RD1 RD6
<7> DDR_A_MA5 DM0 DQS0

CD1

CD2

CD37
DDR_A_MA6 13 14 1K_0402_5% 1K_0402_5%
<7> DDR_A_MA6 VSS5 VSS6
DDR_A_MA7 DDR_A_D2 15 16 DDR_A_D6
<7> DDR_A_MA7 2 2 2 DQ2 DQ6
DDR_A_MA8 @ DDR_A_D3 17 18 DDR_A_D7
<7> DDR_A_MA8

2
DDR_A_MA9 DQ3 DQ7
<7> DDR_A_MA9 19 VSS7 VSS8 20
DDR_A_MA10 DDR_A_D8 21 22 DDR_A_D12
<7> DDR_A_MA10 DQ8 DQ12

1
DDR_A_MA11 DDR_A_D9 23 24 DDR_A_D13
D <7> DDR_A_MA11 DQ9 DQ13 D
DDR_A_MA12 25 26 RD7 RD8
<7> DDR_A_MA12 VSS9 VSS10
DDR_A_MA13 DDR_A_DQS#1 27 28 DDR_A_DM1 1K_0402_5% 1K_0402_5%
<7> DDR_A_MA13 DQS#1 DM1
DDR_A_MA14 DDR_A_DQS1 29 30 DDR_A_RST#
<7> DDR_A_MA14 DQS1 RESET# DDR_A_RST# <7>
DDR_A_MA15 31 32
<7> DDR_A_MA15

2
DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 DQ10 DQ14 34
DDR_A_D11 35 36 DDR_A_D15
DDR_A_DQS0 DQ11 DQ15
<7> DDR_A_DQS0 37 VSS13 VSS14 38
DDR_A_DQS#0 DDR_A_D16 39 40 DDR_A_D20
<7> DDR_A_DQS#0 DQ16 DQ20
DDR_A_DQS1 DDR_A_D17 41 42 DDR_A_D21
<7> DDR_A_DQS1 DQ17 DQ21
DDR_A_DQS#1 43 44
<7> DDR_A_DQS#1 VSS15 VSS16
DDR_A_DQS2 DDR_A_DQS#2 45 46 DDR_A_DM2
<7> DDR_A_DQS2 DQS#2 DM2
DDR_A_DQS#2 DDR_A_DQS2 47 48
<7> DDR_A_DQS#2 DQS2 VSS17
DDR_A_DQS3 49 50 DDR_A_D22
<7> DDR_A_DQS3 VSS18 DQ22
DDR_A_DQS#3 DDR_A_D18 51 52 DDR_A_D23
<7> DDR_A_DQS#3 DQ18 DQ23
DDR_A_DQS4 DDR_A_D19 53 54 DDR_A_D0
<7> DDR_A_DQS4 DQ19 VSS19 DDR_A_D0 <7>
DDR_A_DQS#4 55 56 DDR_A_D28 DDR_A_D1
<7> DDR_A_DQS#4 VSS20 DQ28 DDR_A_D1 <7>
DDR_A_DQS5 DDR_A_D24 57 58 DDR_A_D29 DDR_A_D2
<7> DDR_A_DQS5 DQ24 DQ29 DDR_A_D2 <7>
DDR_A_DQS#5 DDR_A_D25 59 60 DDR_A_D3
<7> DDR_A_DQS#5 DQ25 VSS21 DDR_A_D3 <7>
DDR_A_DQS6 61 62 DDR_A_DQS#3 DDR_A_D4
<7> DDR_A_DQS6 VSS22 DQS#3 DDR_A_D4 <7>
DDR_A_DQS#6 DDR_A_DM3 63 64 DDR_A_DQS3 DDR_A_D5
<7> DDR_A_DQS#6 DM3 DQS3 DDR_A_D5 <7>
DDR_A_DQS7 65 66 DDR_A_D6
<7> DDR_A_DQS7 VSS23 VSS24 DDR_A_D6 <7>
DDR_A_DQS#7 DDR_A_D26 67 68 DDR_A_D30 DDR_A_D7
<7> DDR_A_DQS#7 DQ26 DQ30 DDR_A_D7 <7>
DDR_A_D27 69 70 DDR_A_D31 DDR_A_D8
DQ27 DQ31 DDR_A_D8 <7>
71 72 DDR_A_D9
VSS25 VSS26 DDR_A_D9 <7>
DDR_A_D10
DDR_A_D10 <7>
DDR_A_D11
DDR_A_D11 <7>
DDR_A_D12
DDR_A_D12 <7>
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA DDR_A_D13
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7> DDR_A_D13 <7>
75 76 DDR_A_D14
VDD1 VDD2 DDR_A_D14 <7>
77 78 DDR_A_MA15 DDR_A_D15
NC1 A15 DDR_A_D15 <7>
Layout Note: DDR_A_BS2 79 80 DDR_A_MA14 DDR_A_D16
<7> DDR_A_BS2 BA2 A14 DDR_A_D16 <7>
81 82 DDR_A_D17
C Place near JDIMMA VDD3 VDD4 DDR_A_D17 <7> C
DDR_A_MA12 83 84 DDR_A_MA11 DDR_A_D18
A12/BC# A11 DDR_A_D18 <7>
DDR_A_MA9 85 86 DDR_A_MA7 DDR_A_D19
A9 A7 DDR_A_D19 <7>
87 88 DDR_A_D20
VDD5 VDD6 DDR_A_D20 <7>
DDR_A_MA8 89 90 DDR_A_MA6 DDR_A_D21
A8 A6 DDR_A_D21 <7>
DDR_A_MA5 91 92 DDR_A_MA4 DDR_A_D22
A5 A4 DDR_A_D22 <7>
93 94 DDR_A_D23
+1.5V +1.5V VDD7 VDD8 DDR_A_D23 <7>
DDR_A_MA3 95 96 DDR_A_MA2 DDR_A_D24
A3 A2 DDR_A_D24 <7>
DDR_A_MA1 97 98 DDR_A_MA0 DDR_A_D25
A1 A0 DDR_A_D25 <7>
99 100 DDR_A_D26
VDD9 VDD10 DDR_A_D26 <7>
M_CLK_DDR0 101 102 M_CLK_DDR1 DDR_A_D27
<7> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <7> DDR_A_D27 <7>
330U_X_2VM_R6M
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

M_CLK_DDR#0 103 104 M_CLK_DDR#1 DDR_A_D28

<7> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <7> DDR_A_D28 <7>
@ 1 @ 1 @ 1 @ 1 @ 1 @ 1 1 105 106 DDR_A_D29
VDD11 VDD12 DDR_A_D29 <7>
DDR_A_MA10 107 108 DDR_A_BS1 DDR_A_BS1 <7> DDR_A_D30
A10/AP BA1 DDR_A_D30 <7>
CD3

CD4

CD5

CD6

CD38

CD39

+
CD15

DDR_A_BS0 109 110 DDR_A_RAS# DDR_A_D31

<7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7> DDR_A_D31 <7>
111 112 DDR_A_D32
2 2 2 2 2 2 VDD13 VDD14 DDR_A_D32 <7>
DDR_A_WE# 113 114 DDR_CS0_DIMMA# DDR_A_D33
2 <7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7> DDR_A_D33 <7>
DDR_A_CAS# 115 116 M_ODT0 DDR_A_D34
<7> DDR_A_CAS# CAS# ODT0 M_ODT0 <7> DDR_A_D34 <7>
117 118 DDR_A_D35
VDD15 VDD16 DDR_A_D35 <7>
DDR_A_MA13 119 120 M_ODT1 DDR_A_D36
A13 ODT1 M_ODT1 <7> DDR_A_D36 <7>
DDR_CS1_DIMMA# 121 122 DDR_A_D37
<7> DDR_CS1_DIMMA# S1# NC2 DDR_A_D37 <7>
123 124 DDR_A_D38
VDD17 VDD18 DDR_A_D38 <7>
125 126 +V_DDR_REF_CA DDR_A_D39
NCTEST VREF_CA DDR_A_D39 <7>
127 128 DDR_A_D40
VSS27 VSS28 DDR_A_D40 <7>

1000P_0402_50V7K

0.01U_0402_16V7K

2.2U_0603_6.3V6K
DDR_A_D32 129 130 DDR_A_D36 DDR_A_D41
+1.5V +1.5V DQ32 DQ36 DDR_A_D41 <7>
DDR_A_D33 131 132 DDR_A_D37 DDR_A_D42
DQ33 DQ37 DDR_A_D42 <7>
133 134 1 1 1 DDR_A_D43
VSS29 VSS30 DDR_A_D43 <7>
DDR_A_DQS#4 135 136 DDR_A_DM4 DDR_A_D44
DQS#4 DM4 DDR_A_D44 <7>

CD40

CD7

CD8
DDR_A_DQS4 137 138 @ DDR_A_D45
DQS4 VSS31 DDR_A_D45 <7>
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

139 140 DDR_A_D38 DDR_A_D46

VSS32 DQ38 2 2 2 DDR_A_D46 <7>
1 1 1 1 1 1 1 1 DDR_A_D34 141 142 DDR_A_D39 DDR_A_D47
DQ34 DQ39 DDR_A_D47 <7>
CD41

CD42

CD43

CD44

CD45

CD46

CD47

CD48

DDR_A_D35 143 144 DDR_A_D48

DQ35 VSS33 DDR_A_D48 <7>
145 146 DDR_A_D44 DDR_A_D49
B VSS34 DQ44 DDR_A_D49 <7> B
DDR_A_D40 147 148 DDR_A_D45 DDR_A_D50
2 2 2 2 2 2 @ 2 2 DQ40 DQ45 DDR_A_D50 <7>
@ DDR_A_D41 149 150 DDR_A_D51
DQ41 VSS35 DDR_A_D51 <7>
151 152 DDR_A_DQS#5 DDR_A_D52
VSS36 DQS#5 DDR_A_D52 <7>
DDR_A_DM5 153 154 DDR_A_DQS5 DDR_A_D53
DM5 DQS5 DDR_A_D53 <7>
155 156 DDR_A_D54
VSS37 VSS38 DDR_A_D54 <7>
DDR_A_D42 157 158 DDR_A_D46 DDR_A_D55
DQ42 DQ46 DDR_A_D55 <7>
DDR_A_D43 159 160 DDR_A_D47 DDR_A_D56
DQ43 DQ47 DDR_A_D56 <7>
161 162 DDR_A_D57
VSS39 VSS40 DDR_A_D57 <7>
DDR_A_D48 163 164 DDR_A_D52 DDR_A_D58
DQ48 DQ52 DDR_A_D58 <7>
DDR_A_D49 165 166 DDR_A_D53 DDR_A_D59
DQ49 DQ53 DDR_A_D59 <7>
167 168 DDR_A_D60
VSS41 VSS42 DDR_A_D60 <7>
DDR_A_DQS#6 169 170 DDR_A_DM6 DDR_A_D61
DQS#6 DM6 DDR_A_D61 <7>
DDR_A_DQS6 171 172 DDR_A_D62
DQS6 VSS43 DDR_A_D62 <7>
Layout Note: 173 174 DDR_A_D54 DDR_A_D63
VSS44 DQ54 DDR_A_D63 <7>
DDR_A_D50 175 176 DDR_A_D55
Place near JDIMMA.203,204 DDR_A_D51 177
DQ50 DQ55
178
DQ51 VSS45 DDR_A_D60 DDR_A_DM0
179 VSS46 DQ60 180 DDR_A_DM0 <7>
DDR_A_D56 181 182 DDR_A_D61 DDR_A_DM1
DQ56 DQ61 DDR_A_DM1 <7>
DDR_A_D57 183 184 DDR_A_DM2
DQ57 VSS47 DDR_A_DM2 <7>
185 186 DDR_A_DQS#7 DDR_A_DM3
VSS48 DQS#7 DDR_A_DM3 <7>
DDR_A_DM7 187 188 DDR_A_DQS7 DDR_A_DM4
DM7 DQS7 DDR_A_DM4 <7>
189 190 DDR_A_DM5
VSS49 VSS50 DDR_A_DM5 <7>
+0.75VS DDR_A_D58 191 192 DDR_A_D62 DDR_A_DM6
DQ58 DQ62 DDR_A_DM6 <7>
DDR_A_D59 193 194 DDR_A_D63 DDR_A_DM7
DQ59 DQ63 DDR_A_DM7 <7>
195 VSS51 VSS52 196
+3VS 1 2 197 198 DDR_A_EVENT#
SA0 EVENT# DDR_A_EVENT# <7>
RD2 0_0402_5% 199 200 MEM_SMBDATA
VDDSPD SDA MEM_SMBDATA <11,13,18>
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M
0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

1 2 201 202 MEM_SMBCLK

SA1 SCL MEM_SMBCLK <11,13,18>
0.1U_0402_16V7K

2.2U_0603_6.3V6K

1 1 1 1 1 1 1 1 1 RD3 0_0402_5% 203 204 +0.75VS

VTT1 VTT2
CD52

CD53

CD16

+0.75VS
CD17

CD18

CU73 CU74 CU75 CU76 205 206

G1 G2
A 2 2 2 2 2 2 @ 2 2 2 FOX_AS0A626-U4RN-7F A
CONN@

SP07000J500
DELL CONFIDENTIAL/PROPRIETARY
REVERSE TYPE Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII DIMM A
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 10 of 45
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V
DDR_B_MA0 JDIMMB
<7> DDR_B_MA0
DDR_B_MA1 +V_DDR_REF_DQ 1 2 DDR_B_D0
<7> DDR_B_MA1 VREF_DQ VSS1 DDR_B_D0 <7>
DDR_B_MA2 3 4 DDR_B_D4 DDR_B_D1
<7> DDR_B_MA2 VSS2 DQ4 DDR_B_D1 <7>

2.2U_0603_6.3V6K

0.01U_0402_16V7K

1000P_0402_50V7K
DDR_B_MA3 DDR_B_D0 5 6 DDR_B_D5 DDR_B_D2
<7> DDR_B_MA3 DQ0 DQ5 DDR_B_D2 <7>
DDR_B_MA4 DDR_B_D1 7 8 DDR_B_D3
<7> DDR_B_MA4 DQ1 VSS3 DDR_B_D3 <7>
DDR_B_MA5 1 1 1 9 10 DDR_B_DQS#0 DDR_B_D4
<7> DDR_B_MA5 VSS4 DQS#0 DDR_B_D4 <7>
DDR_B_MA6 DDR_B_DM0 11 12 DDR_B_DQS0 DDR_B_D5
<7> DDR_B_MA6 DM0 DQS0 DDR_B_D5 <7>

CD19

CD20

CD55
DDR_B_MA7 13 14 DDR_B_D6
<7> DDR_B_MA7 VSS5 VSS6 DDR_B_D6 <7>
DDR_B_MA8 DDR_B_D2 15 16 DDR_B_D6 DDR_B_D7
<7> DDR_B_MA8 2 2 2 DQ2 DQ6 DDR_B_D7 <7>
DDR_B_MA9 DDR_B_D3 17 18 DDR_B_D7 DDR_B_D8
<7> DDR_B_MA9 DQ3 DQ7 DDR_B_D8 <7>
DDR_B_MA10 19 20 DDR_B_D9
<7> DDR_B_MA10 VSS7 VSS8 DDR_B_D9 <7>
DDR_B_MA11 @ DDR_B_D8 21 22 DDR_B_D12 DDR_B_D10
<7> DDR_B_MA11 DQ8 DQ12 DDR_B_D10 <7>
DDR_B_MA12 DDR_B_D9 23 24 DDR_B_D13 DDR_B_D11
<7> DDR_B_MA12 DQ9 DQ13 DDR_B_D11 <7>
DDR_B_MA13 25 26 DDR_B_D12
D <7> DDR_B_MA13 VSS9 VSS10 DDR_B_D12 <7> D
DDR_B_MA14 DDR_B_DQS#1 27 28 DDR_B_DM1 DDR_B_D13
<7> DDR_B_MA14 DQS#1 DM1 DDR_B_D13 <7>
DDR_B_MA15 DDR_B_DQS1 29 30 DDR_B_RST# DDR_B_D14
<7> DDR_B_MA15 DQS1 RESET# DDR_B_RST# <7> DDR_B_D14 <7>
31 32 DDR_B_D15
VSS11 VSS12 DDR_B_D15 <7>
DDR_B_D10 33 34 DDR_B_D14 DDR_B_D16
DQ10 DQ14 DDR_B_D16 <7>
DDR_B_DQS0 DDR_B_D11 35 36 DDR_B_D15 DDR_B_D17
<7> DDR_B_DQS0 DQ11 DQ15 DDR_B_D17 <7>
DDR_B_DQS#0 37 38 DDR_B_D18
<7> DDR_B_DQS#0 VSS13 VSS14 DDR_B_D18 <7>
DDR_B_DQS1 DDR_B_D16 39 40 DDR_B_D20 DDR_B_D19
<7> DDR_B_DQS1 DQ16 DQ20 DDR_B_D19 <7>
DDR_B_DQS#1 DDR_B_D17 41 42 DDR_B_D21 DDR_B_D20
<7> DDR_B_DQS#1 DQ17 DQ21 DDR_B_D20 <7>
DDR_B_DQS2 43 44 DDR_B_D21
<7> DDR_B_DQS2 VSS15 VSS16 DDR_B_D21 <7>
DDR_B_DQS#2 DDR_B_DQS#2 45 46 DDR_B_DM2 DDR_B_D22
<7> DDR_B_DQS#2 DQS#2 DM2 DDR_B_D22 <7>
DDR_B_DQS3 DDR_B_DQS2 47 48 DDR_B_D23
<7> DDR_B_DQS3 DQS2 VSS17 DDR_B_D23 <7>
DDR_B_DQS#3 49 50 DDR_B_D22 DDR_B_D24
<7> DDR_B_DQS#3 VSS18 DQ22 DDR_B_D24 <7>
DDR_B_DQS4 DDR_B_D18 51 52 DDR_B_D23 DDR_B_D25
<7> DDR_B_DQS4 DQ18 DQ23 DDR_B_D25 <7>
DDR_B_DQS#4 DDR_B_D19 53 54 DDR_B_D26
<7> DDR_B_DQS#4 DQ19 VSS19 DDR_B_D26 <7>
DDR_B_DQS5 55 56 DDR_B_D28 DDR_B_D27
<7> DDR_B_DQS5 VSS20 DQ28 DDR_B_D27 <7>
DDR_B_DQS#5 DDR_B_D24 57 58 DDR_B_D29 DDR_B_D28
<7> DDR_B_DQS#5 DQ24 DQ29 DDR_B_D28 <7>
DDR_B_DQS6 DDR_B_D25 59 60 DDR_B_D29
<7> DDR_B_DQS6 DQ25 VSS21 DDR_B_D29 <7>
DDR_B_DQS#6 61 62 DDR_B_DQS#3 DDR_B_D30
<7> DDR_B_DQS#6 VSS22 DQS#3 DDR_B_D30 <7>
DDR_B_DQS7 DDR_B_DM3 63 64 DDR_B_DQS3 DDR_B_D31
<7> DDR_B_DQS7 DM3 DQS3 DDR_B_D31 <7>
DDR_B_DQS#7 65 66 DDR_B_D32
<7> DDR_B_DQS#7 VSS23 VSS24 DDR_B_D32 <7>
DDR_B_D26 67 68 DDR_B_D30 DDR_B_D33
DQ26 DQ30 DDR_B_D33 <7>
DDR_B_D27 69 70 DDR_B_D31 DDR_B_D34
DQ27 DQ31 DDR_B_D34 <7>
71 72 DDR_B_D35
VSS25 VSS26 DDR_B_D35 <7>
DDR_B_D36
DDR_B_D36 <7>
DDR_B_D37
DDR_B_D37 <7>
DDR_B_D38
DDR_B_D38 <7>
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB DDR_B_D39
<7> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <7> DDR_B_D39 <7>
75 76 DDR_B_D40
VDD1 VDD2 DDR_B_D40 <7>
77 78 DDR_B_MA15 DDR_B_D41
NC1 A15 DDR_B_D41 <7>
DDR_B_BS2 79 80 DDR_B_MA14 DDR_B_D42
<7> DDR_B_BS2 BA2 A14 DDR_B_D42 <7>
Layout Note: 81 82 DDR_B_D43
VDD3 VDD4 DDR_B_D43 <7>
DDR_B_MA12 83 84 DDR_B_MA11 DDR_B_D44
C Place near JDIMMB A12/BC# A11 DDR_B_D44 <7> C
DDR_B_MA9 85 86 DDR_B_MA7 DDR_B_D45
A9 A7 DDR_B_D45 <7>
87 88 DDR_B_D46
VDD5 VDD6 DDR_B_D46 <7>
DDR_B_MA8 89 90 DDR_B_MA6 DDR_B_D47
A8 A6 DDR_B_D47 <7>
DDR_B_MA5 91 92 DDR_B_MA4 DDR_B_D48
A5 A4 DDR_B_D48 <7>
93 94 DDR_B_D49
VDD7 VDD8 DDR_B_D49 <7>
DDR_B_MA3 95 96 DDR_B_MA2 DDR_B_D50
A3 A2 DDR_B_D50 <7>
DDR_B_MA1 97 98 DDR_B_MA0 DDR_B_D51
A1 A0 DDR_B_D51 <7>
99 100 DDR_B_D52
+1.5V +1.5V VDD9 VDD10 DDR_B_D52 <7>
M_CLK_DDR2 101 102 M_CLK_DDR3 DDR_B_D53
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7> DDR_B_D53 <7>
M_CLK_DDR#2 103 104 M_CLK_DDR#3 DDR_B_D54
<7> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <7> DDR_B_D54 <7>
105 106 DDR_B_D55
VDD11 VDD12 DDR_B_D55 <7>
DDR_B_MA10 107 108 DDR_B_BS1 DDR_B_BS1 <7> DDR_B_D56
A10/AP BA1 DDR_B_D56 <7>
330U_X_2VM_R6M
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

DDR_B_BS0 109 110 DDR_B_RAS# DDR_B_D57

<7> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7> DDR_B_D57 <7>
@ 1 @ 1 @ 1 @ 1 @ 1 @ 1 1 111 112 DDR_B_D58
VDD13 VDD14 DDR_B_D58 <7>
DDR_B_WE# 113 114 DDR_CS2_DIMMB# DDR_B_D59
<7> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7> DDR_B_D59 <7>
CD21

CD22

CD23

CD24

CD56

CD57

+
CD33

DDR_B_CAS# 115 116 M_ODT2 DDR_B_D60

<7> DDR_B_CAS# CAS# ODT0 M_ODT2 <7> DDR_B_D60 <7>
117 118 DDR_B_D61
2 2 2 2 2 2 VDD15 VDD16 DDR_B_D61 <7>
DDR_B_MA13 119 120 M_ODT3 DDR_B_D62
2 A13 ODT1 M_ODT3 <7> DDR_B_D62 <7>
DDR_CS3_DIMMB# 121 122 DDR_B_D63
<7> DDR_CS3_DIMMB# S1# NC2 DDR_B_D63 <7>
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126 +V_DDR_REF_CA
127 VSS27 VSS28 128

1000P_0402_50V7K

0.01U_0402_16V7K

2.2U_0603_6.3V6K
DDR_B_D32 129 130 DDR_B_D36 DDR_B_DM0
DQ32 DQ36 DDR_B_DM0 <7>
DDR_B_D33 131 132 DDR_B_D37 DDR_B_DM1
DQ33 DQ37 DDR_B_DM1 <7>
133 134 1 1 1 DDR_B_DM2
VSS29 VSS30 DDR_B_DM2 <7>
DDR_B_DQS#4 135 136 DDR_B_DM4 DDR_B_DM3
+1.5V +1.5V DQS#4 DM4 DDR_B_DM3 <7>

CD58

CD25

CD26
DDR_B_DQS4 137 138 @ DDR_B_DM4
DQS4 VSS31 DDR_B_DM4 <7>
139 140 DDR_B_D38 DDR_B_DM5
VSS32 DQ38 2 2 2 DDR_B_DM5 <7>
DDR_B_D34 141 142 DDR_B_D39 DDR_B_DM6
DQ34 DQ39 DDR_B_DM6 <7>
DDR_B_D35 143 144 DDR_B_DM7
DQ35 VSS33 DDR_B_DM7 <7>
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

@ @ 145 146 DDR_B_D44

DDR_B_D40 VSS34 DQ44 DDR_B_D45
1 1 1 1 1 1 1 1 147 DQ40 DQ45 148
CD59

CD60

CD61

CD62

CD63

CD64

CD27

CD28

B DDR_B_D41 149 150 B

DQ41 VSS35 DDR_B_DQS#5
151 VSS36 DQS#5 152
DDR_B_DM5 153 154 DDR_B_DQS5
2 2 2 2 2 2 2 2 DM5 DQS5
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS45 DDR_B_D60
Layout Note: 179 VSS46 DQ60 180
DDR_B_D56 181 182 DDR_B_D61
Place near JDIMMB.203,204 DDR_B_D57 183
DQ56 DQ61
184
DQ57 VSS47 DDR_B_DQS#7
185 VSS48 DQS#7 186
+3VS DDR_B_DM7 187 188 DDR_B_DQS7
DM7 DQS7
189 VSS49 VSS50 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
195 VSS51 VSS52 196
+0.75VS 197 198 DDR_B_EVENT#
SA0 EVENT# DDR_B_EVENT# <7>
+3VS 199 200 MEM_SMBDATA
VDDSPD SDA MEM_SMBCLK MEM_SMBDATA <10,13,18>
1 2 201 SA1 SCL 202 MEM_SMBCLK <10,13,18>
RD4 4.7K_0402_5% +0.75VS 203 204 +0.75VS
VTT1 VTT2
1
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M
0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

RD5 205 206

G1 G2
0.1U_0402_16V7K

2.2U_0603_6.3V6K

1 1 1 1 1 1 1 0_0402_5% 1 1
CD68

CD69

CD29

FOX_AS0A626-U8RN-7F
CD35

CD36

A CU77 CU78 CU79 CU80 CONN@ A

2

2 2 2 2 2 2 @ 2 2 2
DC020811210

REVERSE TYPE DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII DIMM B
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 11 of 45
5 4 3 2 1
 5 4 3 2 1

UN2B
D4 A5 HDMI_TXD2P_C CN1 1 2 0.1U_0402_16V7K HDMI_TXD2P HDMI_TXD2P <22>
GFX_RX0P GFX_TX0P HDMI_TXD2N_C CN2 0.1U_0402_16V7K HDMI_TXD2N
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5
HDMI_TXD1P_C CN3
1 2
0.1U_0402_16V7K HDMI_TXD1P
HDMI_TXD2N <22>
A3 GFX_RX1P GFX_TX1P A4 1 2 HDMI_TXD1P <22>
B3 B4 HDMI_TXD1N_C CN4 1 2 0.1U_0402_16V7K HDMI_TXD1N HDMI_TXD1N <22>
GFX_RX1N GFX_TX1N HDMI_TXD0P_C CN5 0.1U_0402_16V7K HDMI_TXD0P
C2 GFX_RX2P GFX_TX2P C3 1 2 HDMI_TXD0P <22>
C1 B2 HDMI_TXD0N_C CN6 1 2 0.1U_0402_16V7K HDMI_TXD0N HDMI_TXD0N <22>
GFX_RX2N GFX_TX2N HDMI_CLKP_C CN7 0.1U_0402_16V7K HDMI_CLKP
E5 GFX_RX3P GFX_TX3P D1 1 2 HDMI_CLKP <22>
D F5 D2 HDMI_CLKN_C CN8 1 2 0.1U_0402_16V7K HDMI_CLKN D
GFX_RX3N GFX_TX3N HDMI_CLKN <22>
G5 GFX_RX4P GFX_TX4P E2
G6 GFX_RX4N GFX_TX4N E1
H5 GFX_RX5P GFX_TX5P F4
H6
J6
GFX_RX5N GFX_TX5N F3
F1
HDMI
GFX_RX6P GFX_TX6P
J5 GFX_RX6N GFX_TX6N F2
J7 GFX_RX7P GFX_TX7P H4
J8 GFX_RX7N GFX_TX7N H3
L5 GFX_RX8P GFX_TX8P H1
L6 GFX_RX8N GFX_TX8N H2
M8 GFX_RX9P GFX_TX9P J2
L8 GFX_RX9N GFX_TX9N J1

PCIE I/F GFX

P7 GFX_RX10P GFX_TX10P K4
M7 GFX_RX10N GFX_TX10N K3
P5 GFX_RX11P GFX_TX11P K1
M5 GFX_RX11N GFX_TX11N K2
R8 GFX_RX12P GFX_TX12P M4
P8 GFX_RX12N GFX_TX12N M3
R6 GFX_RX13P GFX_TX13P M1
R5 GFX_RX13N GFX_TX13N M2
P4 GFX_RX14P GFX_TX14P N2
P3 GFX_RX14N GFX_TX14N N1
T4 GFX_RX15P GFX_TX15P P1
T3 GFX_RX15N GFX_TX15N P2

<20> PCIE_NRX_LANTX_P0 PCIE_NRX_LANTX_P0 AE3 AC1 PCIE_NTX_LANRX_P0_C CN9 1 2 0.1U_0402_16V7K PCIE_NTX_LANRX_P0 PCIE_NTX_LANRX_P0 <20>
PCIE_NRX_LANTX_N0 GPP_RX0P GPP_TX0P PCIE_NTX_LANRX_N0_C CN10 0.1U_0402_16V7K PCIE_NTX_LANRX_N0
<20> PCIE_NRX_LANTX_N0 AD4 GPP_RX0N GPP_TX0N AC2 1 2 PCIE_NTX_LANRX_N0 <20>
<28> PCIE_NRX_WLANTX_P1 PCIE_NRX_WLANTX_P1 AE2 AB4 PCIE_NTX_WLANRX_P1_C CN11 1 2 0.1U_0402_16V7K PCIE_NTX_WLANRX_P1 PCIE_NTX_WLANRX_P1 <28>
PCIE_NRX_WLANTX_N1 GPP_RX1P GPP_TX1P PCIE_NTX_WLANRX_N1_C CN12 0.1U_0402_16V7K PCIE_NTX_WLANRX_N1
<28> PCIE_NRX_WLANTX_N1 AD3 GPP_RX1N GPP_TX1N AB3 1 2 PCIE_NTX_WLANRX_N1 <28>
<28> PCIE_NRX_WWANTX_P2 PCIE_NRX_WWANTX_P2 AD1 AA2 PCIE_NTX_WWANRX_P2_CCN13 1 2 0.1U_0402_16V7K PCIE_NTX_WWANRX_P2 PCIE_NTX_WWANRX_P2 <28>
PCIE_NRX_WWANTX_N2 GPP_RX2P GPP_TX2P PCIE_NTX_WWANRX_N2_CCN14 0.1U_0402_16V7K PCIE_NTX_WWANRX_N2
C
<28> PCIE_NRX_WWANTX_N2 AD2 GPP_RX2N PCIE I/F GPP GPP_TX2N AA1 1 2 PCIE_NTX_WWANRX_N2 <28> C
V5 GPP_RX3P GPP_TX3P Y1
W6 GPP_RX3N GPP_TX3N Y2
U5 GPP_RX4P GPP_TX4P Y4
U6 GPP_RX4N GPP_TX4N Y3
U8 GPP_RX5P GPP_TX5P V1
U7 GPP_RX5N GPP_TX5N V2

<16> PCIE_NRX_STX_P0 PCIE_NRX_STX_P0 AA8 AD7 PCIE_NTX_SRX_P0_C CN15 1 2 0.1U_0402_16V7K PCIE_NTX_SRX_P0 <16> UN2A
PCIE_NRX_STX_N0 SB_RX0P SB_TX0P PCIE_NTX_SRX_N0_C CN16 0.1U_0402_16V7K H_CADOP0 H_CADIP0
<16> PCIE_NRX_STX_N0 Y8 SB_RX0N SB_TX0N AE7 1 2 PCIE_NTX_SRX_N0 <16> <6> H_CADOP0 Y25 HT_RXCAD0P HT_TXCAD0P D24 H_CADIP0 <6>
<16> PCIE_NRX_STX_P1 PCIE_NRX_STX_P1 AA7 AE6 PCIE_NTX_SRX_P1_C CN20 1 2 0.1U_0402_16V7K PCIE_NTX_SRX_P1 <16> H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0 H_CADIN0 <6>
SB_RX1P SB_TX1P <6> H_CADON0 HT_RXCAD0N HT_TXCAD0N
<16> PCIE_NRX_STX_N1 PCIE_NRX_STX_N1 Y7 AD6 PCIE_NTX_SRX_N1_C CN17 1 2 0.1U_0402_16V7K PCIE_NTX_SRX_N1 <16> H_CADOP1 V22 E24 H_CADIP1 H_CADIP1 <6>
SB_RX1N SB_TX1N <6> H_CADOP1 HT_RXCAD1P HT_TXCAD1P
<16> PCIE_NRX_STX_P2 PCIE_NRX_STX_P2 AA5 PCIE I/F SB AB6 PCIE_NTX_SRX_P2_C CN18 1 2 0.1U_0402_16V7K PCIE_NTX_SRX_P2 <16> H_CADON1 V23 E25 H_CADIN1 H_CADIN1 <6>
SB_RX2P SB_TX2P <6> H_CADON1 HT_RXCAD1N HT_TXCAD1N
<16> PCIE_NRX_STX_N2 PCIE_NRX_STX_N2 AA6 AC6 PCIE_NTX_SRX_N2_C CN21 1 2 0.1U_0402_16V7K PCIE_NTX_SRX_N2 <16> H_CADOP2 V25 F24 H_CADIP2 H_CADIP2 <6>
SB_RX2N SB_TX2N <6> H_CADOP2 HT_RXCAD2P HT_TXCAD2P
<16> PCIE_NRX_STX_P3 PCIE_NRX_STX_P3 W5 AD5 PCIE_NTX_SRX_P3_C CN22 1 2 0.1U_0402_16V7K PCIE_NTX_SRX_P3 <16> H_CADON2 V24 F25 H_CADIN2 H_CADIN2 <6>
SB_RX3P SB_TX3P <6> H_CADON2 HT_RXCAD2N HT_TXCAD2N
<16> PCIE_NRX_STX_N3 PCIE_NRX_STX_N3 Y5 AE5 PCIE_NTX_SRX_N3_C CN19 1 2 0.1U_0402_16V7K PCIE_NTX_SRX_N3 <16> H_CADOP3 U24 F23 H_CADIP3 H_CADIP3 <6>
SB_RX3N SB_TX3N <6> H_CADOP3 HT_RXCAD3P HT_TXCAD3P
H_CADON3 U25 F22 H_CADIN3 H_CADIN3 <6>
<6> H_CADON3 HT_RXCAD3N HT_TXCAD3N
AC8 PCE_PCAL RN1 1 2 1.27K_0402_1%~D H_CADOP4 T25 H23 H_CADIP4 H_CADIP4 <6>
PCE_CALRP(PCE_BCALRP) <6> H_CADOP4 HT_RXCAD4P HT_TXCAD4P
AB8 PCE_NCAL RN2 1 2 +1.1VS H_CADON4 T24 H22 H_CADIN4 H_CADIN4 <6>
PCE_CALRN(PCE_BCALRN) <6> H_CADON4 HT_RXCAD4N HT_TXCAD4N
2K_0402_1%~D H_CADOP5 P22 J25 H_CADIP5 H_CADIP5 <6>
<6> H_CADOP5 HT_RXCAD5P HT_TXCAD5P

HYPER TRANSPORT CPU I/F

RS880M_FCBGA528 H_CADON5 P23 J24 H_CADIN5 H_CADIN5 <6>
<6> H_CADON5 HT_RXCAD5N HT_TXCAD5N
Place < 100mils from pin AC8 and AB8 H_CADOP6 P25 K24 H_CADIP6 H_CADIP6 <6>
<6> H_CADOP6 HT_RXCAD6P HT_TXCAD6P
H_CADON6 P24 K25 H_CADIN6 H_CADIN6 <6>
<6> H_CADON6 HT_RXCAD6N HT_TXCAD6N
H_CADOP7 N24 K23 H_CADIP7 H_CADIP7 <6>
<6> H_CADOP7 HT_RXCAD7P HT_TXCAD7P
H_CADON7 N25 K22 H_CADIN7 H_CADIN7 <6>
<6> H_CADON7 HT_RXCAD7N HT_TXCAD7N
H_CADOP8 AC24 F21 H_CADIP8 H_CADIP8 <6>
<6> H_CADOP8 HT_RXCAD8P HT_TXCAD8P
H_CADON8 AC25 G21 H_CADIN8 H_CADIN8 <6>
<6> H_CADON8 HT_RXCAD8N HT_TXCAD8N
H_CADOP9 AB25 G20 H_CADIP9 H_CADIP9 <6>
<6> H_CADOP9 HT_RXCAD9P HT_TXCAD9P
H_CADON9 AB24 H21 H_CADIN9 H_CADIN9 <6>
<6> H_CADON9 HT_RXCAD9N HT_TXCAD9N
H_CADOP10 AA24 J20 H_CADIP10 H_CADIP10 <6>
<6> H_CADOP10 HT_RXCAD10P HT_TXCAD10P
H_CADON10 AA25 J21 H_CADIN10 H_CADIN10 <6>
<6> H_CADON10 HT_RXCAD10N HT_TXCAD10N
H_CADOP11 Y22 J18 H_CADIP11 H_CADIP11 <6>
B <6> H_CADOP11 HT_RXCAD11P HT_TXCAD11P B
H_CADON11 Y23 K17 H_CADIN11 H_CADIN11 <6>
<6> H_CADON11 HT_RXCAD11N HT_TXCAD11N
H_CADOP12 W21 L19 H_CADIP12 H_CADIP12 <6>
<6> H_CADOP12 HT_RXCAD12P HT_TXCAD12P
H_CADON12 W20 J19 H_CADIN12 H_CADIN12 <6>
<6> H_CADON12 HT_RXCAD12N HT_TXCAD12N
H_CADOP13 V21 M19 H_CADIP13 H_CADIP13 <6>
<6> H_CADOP13 HT_RXCAD13P HT_TXCAD13P
H_CADON13 V20 L18 H_CADIN13 H_CADIN13 <6>
<6> H_CADON13 HT_RXCAD13N HT_TXCAD13N
H_CADOP14 U20 M21 H_CADIP14 H_CADIP14 <6>
<6> H_CADOP14 HT_RXCAD14P HT_TXCAD14P
H_CADON14 U21 P21 H_CADIN14 H_CADIN14 <6>
<6> H_CADON14 HT_RXCAD14N HT_TXCAD14N
H_CADOP15 U19 P18 H_CADIP15 H_CADIP15 <6>
<6> H_CADOP15 HT_RXCAD15P HT_TXCAD15P
H_CADON15 U18 M18 H_CADIN15 H_CADIN15 <6>
<6> H_CADON15 HT_RXCAD15N HT_TXCAD15N
H_CLKOP0 T22 H24 H_CLKIP0 H_CLKIP0 <6>
<6> H_CLKOP0 HT_RXCLK0P HT_TXCLK0P
H_CLKON0 T23 H25 H_CLKIN0 H_CLKIN0 <6>
<6> H_CLKON0 HT_RXCLK0N HT_TXCLK0N
H_CLKOP1 AB23 L21 H_CLKIP1 H_CLKIP1 <6>
<6> H_CLKOP1 HT_RXCLK1P HT_TXCLK1P
H_CLKON1 AA22 L20 H_CLKIN1 H_CLKIN1 <6>
<6> H_CLKON1 HT_RXCLK1N HT_TXCLK1N
H_CTLOP0 M22 M24 H_CTLIP0 H_CTLIP0 <6>
<6> H_CTLOP0 HT_RXCTL0P HT_TXCTL0P
H_CTLON0 M23 M25 H_CTLIN0 H_CTLIN0 <6>
<6> H_CTLON0 HT_RXCTL0N HT_TXCTL0N
H_CTLOP1 R21 P19 H_CTLIP1 H_CTLIP1 <6>
<6> H_CTLOP1 HT_RXCTL1P HT_TXCTL1P
H_CTLON1 R20 R18 H_CTLIN1 H_CTLIN1 <6>
<6> H_CTLON1 HT_RXCTL1N HT_TXCTL1N
1 RN3 2 301_0402_1%~D HT_RXCALP C23 HT_RXCALP HT_TXCALP B24 HT_TXCALP 1 RN4 2 301_0402_1%~D
HT_RXCALN A24 B25 HT_TXCALN
HT_RXCALN HT_TXCALN
Place < 100mils from pin C23 and A24 RS880M_FCBGA528 Place < 100mils from pin B25 and B24

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, RS880M HT / PCIE / HDMI
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 12 of 45
5 4 3 2 1
 5 4 3 2 1

STRAP_DEBUG_BUS_GPIO_ENABLEb RS880M: Enables Side port memory DFT_GPIO1: LOAD_EEPROM_STRAPS

+3VS LN1
Enables the Test Debug Bus using GPIO. Enables Memory SIDE PORT BLM18EG221SN1D_2P_0603 Selects Loading of STRAPS from EPROM
1 Disable 1 = Memory Side port Not available
3.3V 110mA 15mil
1 2 +AVDD 1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 Enable 0 = Memory Side port available
1 0 : I2C Master can load strap values from EEPROM if connected, or use
Register Readback of strap:
+3VS +3VS NB_CLKCFG:CLK_TOP_SPARE_D[1] CN23 default values if not connected
2.2U_0603_10V6K~D @ DN1
+1.8VS 2 SUS_STAT#_NB 2 1 PLT_RST# <16,20,26,28>
1

1
RN7 1.8V 20mA 15mil
RN5 RN6 @ 1 2 +AVDDDI CH751H-40PT_SOD323-2 SCHOTTKY BARRIER DIODE
3K_0402_5%~D 3K_0402_5%~D 1 1 2
0_0603_5%
CN24 UN2C RN8 @ 3K_0402_5%~D
2

2
D VGA_CRT_VSYNC VGA_CRT_HSYNC F12 A22 LVDS_A0+ D
0.1U_0402_16V7K AVDD1(NC) TXOUT_L0P(NC) LVDS_A0+ <27>
2 LVDS_A0-
E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 LVDS_A0- <27>
1

1
+1.8VS LN2 F14 A21 LVDS_A1+
AVDDDI(NC) TXOUT_L1P(NC) LVDS_A1+ <27>
RN55 RN9 BLM18EG221SN1D_2P_0603 1.8V 4mA 15mil G15 B21 LVDS_A1-
AVSSDI(NC) TXOUT_L1N(NC) LVDS_A1- <27>
3K_0402_5%~D 3K_0402_5%~D 1 2 +AVDDQ H15 AVDDQ(NC) TXOUT_L2P(NC) B20 LVDS_A2+
LVDS_A2+ <27>
1 H14 A20 LVDS_A2-
AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) LVDS_A2- <27>
@ A19
2

2
CN25 TXOUT_L3P(NC)
E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19

CRT/TVOUT
2.2U_0603_10V6K~D F17
2 Y(DFT_GPIO2)
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18
TXOUT_U0N(NC) A18
VGA_CRT_R G18 A17
<24> VGA_CRT_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17
VGA_CRT_G E18 D20
<24> VGA_CRT_G GREEN(DFT_GPIO1) TXOUT_U2P(NC)
F18 GREENb(NC) TXOUT_U2N(NC) D21
Need CIS symbol VGA_CRT_B E19 D18
<24> VGA_CRT_B BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5)
F19 BLUEb(NC) TXOUT_U3N(NC) D19
Check List: R=140 ohm
+1.1VS VGA_CRT_HSYNC LVDS_ACLK+ LN4 +1.8VS
LN3
1.1V 65mA VGA_CRT_R
<24> VGA_CRT_HSYNC
VGA_CRT_VSYNC
A11 DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) B16
LVDS_ACLK-
LVDS_ACLK+ <27>
BLM18EG221SN1D_2P_0603
15mil 1 2 <24> VGA_CRT_VSYNC B11 DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) A16 LVDS_ACLK- <27>
1 2 +NB_PLLVDD RN10 140_0402_1%~D VGA_DDC_CLK F8 D16 1 2
<24> VGA_DDC_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
MBK1608221YZF_2P_0603 1 1 2 VGA_CRT_G VGA_DDC_DATA E8 D17 1
<24> VGA_DDC_DATA DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1)
RN11 150_0402_1% 15mil
CN26 1 2 VGA_CRT_B RN13 1 2 715_0402_1% DAC_RST G14 1.8V 15mA CN27
2.2U_0603_10V6K~D RN12 150_0402_1% DAC_RSET(PWM_GPIO1) +LPVDD 2.2U_0603_10V6K~D
VDDLTP18(NC) A13
2 +NB_PLLVDD 2
A12 PLLVDD(NC) VSSLTP18(NC) B13
+NB_PLLVDD18 D14 LN5

PLL PWR
PLLVDD18(NC) BLM18EG221SN1D_2P_0603
1.8V 300mA

LVTM
B12 PLLVSS(NC) VDDLT18_1(NC) A15
B15 +LVDDR18D 1 2
+1.8VS +NB_HTPLL VDDLT18_2(NC)
LN6
1.8V 20mA H17 VDDA18HTPLL VDDLT33_1(NC) A14 1 1
15mil VDDLT33_2(NC) B14
1 2 +NB_PLLVDD18 +NB_PCIEPLL D7 CN28 CN29
C BLM18EG221SN1D_2P_0603 1 VDDA18PCIEPLL1 0.1U_0402_16V7K 4.7U_0603_6.3V6K C
E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
2 2
VSSLT2(VSS) D15
CN30 <16,20,26,28> PLT_RST# PLT_RST# D8 C16
2.2U_0603_10V6K~D NB_PWRGD SYSRESETb VSSLT3(VSS)

PM
<18> NB_PWRGD_SB 2 1 A10 POWERGOOD VSSLT4(VSS) C18
2 RN14 0_0402_5% NB_LDTSTOP# C10 LDTSTOPb VSSLT5(VSS) C20
NB_ALLOW_LDTSTOPC12 E20
ALLOW_LDTSTOP VSSLT6(VSS)
VSSLT7(VSS) C22
+1.8VS CLK_HTREFCLK_P
LN7
1.8V 120mA <16> CLK_HTREFCLK_P
CLK_HTREFCLK_N
C25 HT_REFCLKP
15mil <16> CLK_HTREFCLK_N C24 HT_REFCLKN
1 2 +NB_PCIEPLL
BLM18EG221SN1D_2P_0603 1 CLK_NB_REFCLK_P E11
<16> CLK_NB_REFCLK_P REFCLK_P/OSCIN(OSCIN)

CLOCKs
CLK_NB_REFCLK_N F11 E9 ENVDD ENVDD <27>
<16> CLK_NB_REFCLK_N REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP)
CN31 F7 NB_LCD_PWM NB_LCD_PWM <27>
2.2U_0603_10V6K~D CLK_NB_GFX_CLK_P CLK_NB_GFX_CLK_P LVDS_BLON(PCE_RCALRP) ENBKL
T2 GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) G12 ENBKL <27>
2

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
CLK_NB_GFX_CLK_N CLK_NB_GFX_CLK_N T1 GFX_REFCLKN

2
4.7K_0402_5%

4.7K_0402_5%

U1 RN16 RN17 RN18

GPP_REFCLKP
1

+1.8VS @ @ @
LN8
1.8V 20mA RN54 RN53
U2 GPP_REFCLKN
15mil
1 2 +NB_HTPLL <16> CLK_SB_CLK_P CLK_SB_CLK_P V4

1
BLM18EG221SN1D_2P_0603 1 CLK_SB_CLK_N GPPSB_REFCLKP(SB_REFCLKP)
<16> CLK_SB_CLK_N V3 GPPSB_REFCLKN(SB_REFCLKN)
2

CN33 <27> LDDC_CLK_MCH LDDC_CLK_MCH B9

2.2U_0603_10V6K~D LDDC_DATA_MCH I2C_CLK
2 <27> LDDC_DATA_MCH
HDMICLK_UMA
A9
A8
I2C_DATA MIS. TMDS_HPD(NC) D9
D10
HDMI_HPD <22>
<22> HDMICLK_UMA DDC_CLK0/AUX0P(NC) HPD(NC)
HDMIDAT_UMA B8
<22> HDMIDAT_UMA DDC_DATA0/AUX0N(NC)
B7 D12 SUS_STAT#_NB 2 RN19 1 0_0402_5%
DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) SUS_STAT# <18>
A7 DDC_DATA1/AUX1N(NC)
AE8 2 RN20 1 0_0402_5% NB_THRMDA
THERMALDIODE_P NB_THRMDC
B10 STRP_DATA THERMALDIODE_N AD8 2 RN21 1 0_0402_5%

G11 RSVD TESTMODE D13

B B

1
C8 AUX_CAL(NC) RN25
RS880M_FCBGA528 1.8K_0402_5%~D
+3VS
4.7K_0402_5%

2
RN23 1 2 LDDC_CLK_MCH +1.8VS

4.7K_0402_5%
1

RN26 1 2 LDDC_DATA_MCH +3VS

RN28
300_0402_5%~D

2
External Thermal Sensor EMC1402 for RS880M
RN29
2

+1.8VS NB_PWRGD 10K_0402_5% +3VS

1

D UT7

1
2

2 SB_PWRGD#

0.1U_0402_16V7K
RN30 QN1 G 1 NB_THRMDA
1K_0402_1%~D S SSM3K7002FU_SC70-3 1 1 8 MEM_SMBCLK
MEM_SMBCLK <10,11,18>
3

CT3 VDD SMCLK

CT4 2 7 MEM_SMBDATA
MEM_SMBDATA <10,11,18>
1

RN32 2 2200P_0402_50V7K DP SMDATA

1
NB_ALLOW_LDTSTOP D NB_THRMDC 2 SMB_ALERT#
<16> ALLOW_LDTSTOP 2 1 3 DN ALERT# 6 SMB_ALERT# <8,18,26>
SB_PWRGD 2 QN2
<8,18,26> SB_PWRGD
0_0402_5% G SSM3K7002FU_SC70-3 THERM#_NB 4 5
THERM# GND
1

S
3

RN33 RT3
+1.8VS +1.8VS 10K_0402_5% 1 2
+3VS
10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
2

1
1

A A
@ RN56 CN90 RN36
0.1U_0402_16V7K 2.2K_0402_5%
300_0402_5%~D 2 for NB_PWRGD glitch (panel flash issue)
5

UN5
DELL CONFIDENTIAL/PROPRIETARY
2

2
P

B NB_LDTSTOP#
Y 4
LDT_STOP#
<8,16> LDT_STOP# 1 A Compal Electronics, Inc.
G

NC7SZ08P5X_NL_SC70-5 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
3

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, RS880M SYSTEM I/F
@ NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
RN37 2 0_0402_5% PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
1 AMD suggest LA-6132P
Date: Tuesday, May 04, 2010 Sheet 13 of 45
5 4 3 2 1
 5 4 3 2 1

UN4
UN2D
+SPM_VREF1 M8 E3 SPM_DQ0 PAR 4 OF 6
+SPM_VREF2 VREFCA DQL0 SPM_DQ1 SPM_A0 SPM_DQ0
H1 VREFDQ DQL1 F7 AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
F2 SPM_DQ2 SPM_A1 AE16 AA20 SPM_DQ1
SPM_A0 DQL2 SPM_DQ3 SPM_A2 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) SPM_DQ2
N3 A0 DQL3 F8 V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
SPM_A1 P7 H3 SPM_DQ4 SPM_A3 AE15 Y19 SPM_DQ3
D SPM_A2 A1 DQL4 SPM_DQ5 SPM_A4 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) SPM_DQ4 D
P3 A2 DQL5 H8 AA12 MEM_A4(NC) MEM_DQ4(NC) V17
SPM_A3 N2 G2 SPM_DQ6 SPM_A5 AB16 AA17 SPM_DQ5
SPM_A4 A3 DQL6 SPM_DQ7 SPM_A6 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) SPM_DQ6
P8 A4 DQL7 H7 AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
SPM_A5 P2 SPM_A7 AD14 Y15 SPM_DQ7
SPM_A6 A5 SPM_A8 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) SPM_DQ8
R8 A6 AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
SPM_A7 R2 D7 SPM_DQ8 SPM_A9 AD15 AD19 SPM_DQ9

SBD_MEM/DVO_I/F
SPM_A8 A7 DQU0 SPM_DQ9 SPM_A10 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) SPM_DQ10
T8 A8 DQU1 C3 AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
SPM_A9 R3 C8 SPM_DQ10 SPM_A11 AE13 AC18 SPM_DQ11
SPM_A10 A9 DQU2 SPM_DQ11 SPM_A12 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) SPM_DQ12
L7 A10/AP DQU3 C2 AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
SPM_A11 R7 A7 SPM_DQ12 SPM_A13 Y14 AD22 SPM_DQ13
SPM_A12 A11 DQU4 SPM_DQ13 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) SPM_DQ14
N7 A12 DQU5 A2 MEM_DQ14/DVO_D10(NC) AC22
SPM_A13 T3 B8 SPM_DQ14 SPM_BA0 AD16 AD21 SPM_DQ15
A13 DQU6 SPM_DQ15 SPM_BA1 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC)
T7 A14 DQU7 A3 AE17 MEM_BA1(NC)
M7 SPM_BA2 AD17 Y17 SPM_DQS_P0
A15/BA3 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) SPM_DQS_N0
MEM_DQS0N/DVO_IDCKN(NC) W18
+1.5V_SPM_VDDQ SPM_RAS# W12 AD20 SPM_DQS_P1
SPM_BA0 SPM_CAS# MEM_RASb(NC) MEM_DQS1P(NC) SPM_DQS_N1
M2 BA0 VDD B2 Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21
SPM_BA1 N8 D9 SPM_WE# AD18
SPM_BA2 BA1 VDD SPM_CS# MEM_WEb(NC) SPM_DM0 LN9
M3 BA2 VDD G7 AB13 MEM_CSb(NC) MEM_DM0(NC) W17
K2 SPM_CKE AB18 AE19 SPM_DM1 BLM18EG221SN1D_2P_0603 +1.8VS
VDD SPM_ODT MEM_CKE(NC) MEM_DM1/DVO_D8(NC)
VDD K8 V14 MEM_ODT(NC) 1.8V 15mA
100_0402_5%~D

N1 AE23 +1.8V_IOPLLVDD 2 1
VDD IOPLLVDD18(NC)
1

SPM_CLKP J7 N9 SPM_CLKP V15 AE24 +VDD_MUX_IOPLLVDD 2 1 +1.1VS

SPM_CLKN CK VDD RN39 SPM_CLKN MEM_CKP(NC) IOPLLVDD(NC) BLM18EG221SN1D_2P_0603
K7 CK VDD R1 W14 MEM_CKN(NC) 1 1
RN38

SPM_CKE K9 R9 40.2_0402_1%~D AD23 LN10 1.1V 26mA

CKE/CKE0 VDD MEMCOMPP IOPLLVSS(NC) CN34 CN35
@ 1 2 AE12 MEM_COMPP(NC)
+1.5V_SPM_VDDQ 1 2 MEMCOMPN AD12 AE18 +SPM_VREF 2.2U_0603_10V6K~D 2.2U_0603_10V6K~D
2

SPM_ODT RN40 MEM_COMPN(NC) MEM_VREF(NC) 2 2

K1 ODT/ODT0 VDDQ A1
SPM_CS# L2 A8 40.2_0402_1%~D RS880M_FCBGA528
SPM_RAS# CS/CS0 VDDQ
J3 RAS VDDQ C1
SPM_CAS# K3 C9
SPM_WE# CAS VDDQ
L3 WE VDDQ D2
C E9 C
VDDQ
VDDQ F1
SPM_DQS_P0 F3 H2
SPM_DQS_P1 DQSL VDDQ
C7 DQSU VDDQ H9
+1.5V_SPM_VDDQ +1.5V_SPM_VDDQ +1.5V_SPM_VDDQ
SPM_DM0 E7 A9
SPM_DM1 DML VSS
D3 DMU VSS B3
VSS E1
VSS G8
SPM_DQS_N0 G3 J2
SPM_DQS_N1 DQSL VSS
B7 DQSU VSS J8

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
VSS M1

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D
VSS M9 1 1 1

1
+1.5V_SPM_VDDQ P1
VSS CN36 CN37 CN38
T2 RESET VSS P9
RN44 1 2 10K_0402_5% T1 RN41 RN42 RN43
VSS 2 2 2
<18> SP_DDR3_RST# L8 ZQ/ZQ0 VSS T9

2
1

243_0402_1%

J1 B1 +SPM_VREF1 +SPM_VREF2 +SPM_VREF

NC/ODT1 VSSQ
RN45

L1 NC/CS1 VSSQ B9

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
J9 NC/CE1 VSSQ D1

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D
L9 NCZQ1 VSSQ D8 1 1 1

1
E2
2

VSSQ CN39 CN40 CN41

VSSQ E8
F9 RN46 RN47 RN48
VSSQ 2 2 2
VSSQ G1
G9

2
VSSQ
96-BALL
SDRAM DDR3
B K4W1G1646E-HC12_FBGA96 B

SA00003570L

+1.5V_SPM_VDDQ +1.5VS

RN49
1 2
10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_16V7K

0.1U_0402_16V7K

0_0805_5%
1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1
CN42

CN43

CN44 CN45 CN46 CN47

2 2 2 2 2 2

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, RS880M SidePort DDR III
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 14 of 45
5 4 3 2 1
 5 4 3 2 1

+1.1VS

LN11 1.1V 600mA 40mil +1.1VS UN2F

1 2+1.1VS_VDDHT

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
0_0805_5% UN2E 1.1V 2.5A LN12
A25 VSSAHT1 VSSAPCIE1 A2
1 1 1 1 100mil
+1.1VS_VDDPCIE
D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
J17 VDDHT_1 VDDPCIE_1 A6 2 1 E22 VSSAHT3 VSSAPCIE3 D3

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_16V7K

0.1U_0402_16V7K

4.7U_0603_6.3V6K
CN48 CN49 CN50 CN51 K16 PART 5/6 B6 G22 D5
D VDDHT_2 VDDPCIE_2 0_1206_5% VSSAHT4 VSSAPCIE4 D
L16 VDDHT_3 VDDPCIE_3 C6 1 1 1 1 1 G24 VSSAHT5 VSSAPCIE5 E4
2 2 2 2
M16 VDDHT_4 VDDPCIE_4 D6 G25 VSSAHT6 VSSAPCIE6 G1
P16 E6 CN60 CN52 CN53 CN54 CN55 H19 G2
+1.1VS VDDHT_5 VDDPCIE_5 VSSAHT7 VSSAPCIE7
R16 VDDHT_6 VDDPCIE_6 F6 J22 VSSAHT8 VSSAPCIE8 G4
2 2 2 2 2
T16 VDDHT_7 VDDPCIE_7 G7 L17 VSSAHT9 VSSAPCIE9 H7
LN13 1.1V 700mA 40mil H8 L22 J4
VDDPCIE_8 VSSAHT10 VSSAPCIE10
1 2+1.1VS_VDDHTRX H18 VDDHTRX_1 VDDPCIE_9 J9 L24 VSSAHT11 VSSAPCIE11 R7

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
G19 VDDHTRX_2 VDDPCIE_10 K9 L25 VSSAHT12 VSSAPCIE12 L1
0_0805_5% 1 1 1 1 F20 M9 M20 L2
VDDHTRX_3 VDDPCIE_11 VSSAHT13 VSSAPCIE13
E21 VDDHTRX_4 VDDPCIE_12 L9 N22 VSSAHT14 VSSAPCIE14 L4
CN56 CN57 CN58 CN59 D22 P9 P20 L7
VDDHTRX_5 VDDPCIE_13 VSSAHT15 VSSAPCIE15
B23 VDDHTRX_6 VDDPCIE_14 R9 R19 VSSAHT16 VSSAPCIE16 M6
VDDHTTX already check with 2 2 2 2 +NB_CORE
A23 VDDHTRX_7 VDDPCIE_15 T9 R22 VSSAHT17 VSSAPCIE17 N4
AMD need 1.1V V9 R24 P6
VDDPCIE_16 VSSAHT18 VSSAPCIE18
AE25 VDDHTTX_1 VDDPCIE_17 U9 R25 VSSAHT19 VSSAPCIE19 R1
+1.1VS AD24 VDDHTTX_2 520mil 1.1V 12A H20 VSSAHT20 VSSAPCIE20 R2
AC23 VDDHTTX_3 VDDC_1 K12 U22 VSSAHT21 VSSAPCIE21 R4

10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
LN14 1.1V-1.2V 400mA 40mil AB22 J14 V19 V7
VDDHTTX_4 VDDC_2 VSSAHT22 VSSAPCIE22

GROUND
1 2 +1.1VS_VDDHTTX AA21 U16 1 1 1 1 1 1 1 1 1 W22 U4
VDDHTTX_5 VDDC_3 VSSAHT23 VSSAPCIE23
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K

Y20 VDDHTTX_6 VDDC_4 J11 W24 VSSAHT24 VSSAPCIE24 V8

0_0805_5% 1 1 1 1 1 W19 K15 CN66 CN67 CN68 CN69 CN70 CN71 CN72 CN73 CN74 W25 V6

POWER
VDDHTTX_7 VDDC_5 VSSAHT25 VSSAPCIE25
V18 VDDHTTX_8 VDDC_6 M12 Y21 VSSAHT26 VSSAPCIE26 W1
CN62 CN63 CN64 CN65 2 2 2 2 2 2 2 2 2
U17 VDDHTTX_9 VDDC_7 L14 AD25 VSSAHT27 VSSAPCIE27 W2
0805/220Ohm/2000mA CN61 T17 L11 W4
MPN:BLM21PG221SN1D 2 2 2 2 2 VDDHTTX_10 VDDC_8 VSSAPCIE28
R17 VDDHTTX_11 VDDC_9 M13 L12 VSS11 VSSAPCIE29 W7
CPN:SM010026280 P17 M15 M14 W8
220 ohm 2A VDDHTTX_12 VDDC_10 VSS12 VSSAPCIE30
M17 VDDHTTX_13 VDDC_11 N12 N13 VSS13 VSSAPCIE31 Y6
need SYMBOL N14 P12 AA4
VDDC_12 VSS14 VSSAPCIE32
J10 VDDA18PCIE_1 VDDC_13 P11 P15 VSS15 VSSAPCIE33 AB5
P10 VDDA18PCIE_2 VDDC_14 P13 R11 VSS16 VSSAPCIE34 AB1
+1.8VS K10 P14 R14 AB7
VDDA18PCIE_3 VDDC_15 VSS17 VSSAPCIE35
M10 VDDA18PCIE_4 VDDC_16 R12 T12 VSS18 VSSAPCIE36 AC3
C LN15 C
1.8V 700mA 60mil L10 VDDA18PCIE_5 VDDC_17 R15 U14 VSS19 VSSAPCIE37 AC4
2 1+1.8VS_VDDA18PCIE W9 VDDA18PCIE_6 VDDC_18 T11 U11 VSS20 VSSAPCIE38 AE1
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

H9 VDDA18PCIE_7 VDDC_19 T15 U15 VSS21 VSSAPCIE39 AE4

BLM21PG221SN1D_0805 1 1 1 1 1 1 T10 U12 V12 AB2
VDDA18PCIE_8 VDDC_20 +1.5VS VSS22 VSSAPCIE40
R10 VDDA18PCIE_9 VDDC_21 T14 W11 VSS23
CN75 CN76 CN77 CN78 CN79 CN80 Y9 J16 W15
VDDA18PCIE_10 VDDC_22 VSS24
2 2 2 2 2 2
AA9 VDDA18PCIE_11 20mil 1.5V 100mA +VDD_MEM
AC12 VSS25 VSS1 AE14
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10 1 RN50 2 AA14 VSS26 VSS2 D11

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

4.7U_0603_6.3V6K
AD9 AA11 0_0603_5% Y18 G8
VDDA18PCIE_13 VDD_MEM2(NC) VSS27 VSS3
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11 1 1 1 1 1 AB11 VSS28 VSS4 E14
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10 AB15 VSS29 VSS5 E15
1.8V 10mA 15mil AB10 CN82 CN83 CN81 CN84 CN85 AB17 J15
+1.8VS_VDD18NB VDD_MEM5(NC) VSS30 VSS6
1 RN51 2 F9 VDD18_1 VDD_MEM6(NC) AC10 AB19 VSS31 VSS7 J12
0_0603_5% 2 2 2 2 2
1.8V 25mA 15mil G9 VDD18_2 AE20 VSS32 VSS8 K14
1U_0402_6.3V6K

1 +1.8VS AE11 VDD18_MEM1(NC) VDD33_1(NC) H11 AB21 VSS33 VSS9 M11

1U_0402_6.3V6K

1 AD11 VDD18_MEM2(NC) VDD33_2(NC) H12 K11 VSS34 VSS10 L15

CN86 +3VS
CN87 RS880M_FCBGA528 15mil RS880M_FCBGA528
2 +3VS_VDD33NB 1 RN52 2
2

0.1U_0402_16V7K

0.1U_0402_16V7K
0_0603_5%
1 1 3.3V 60mA
CN88 CN89
2 2

B B

RS880M POWER TABLE

PIN NAME RS880M PIN NAME RS880M

VDDHT +1.1V IOPLLVDD +1.1V
VDDHTRX +1.1V AVDD +3.3V
VDDHTTX +1.2V AVDDDI +1.8V
VDDA18PCIE +1.8V AVDDQ +1.8V
VDD18 +1.8V PLLVDD +1.1V
VDD18_MEM +1.8V PLLVDD18 +1.8V
VDDPCIE +1.1V VDDA18PCIEPLL +1.8V
VDDC +1.1V VDDA18HTPLL +1.8V
VDD_MEM +1.5V(1.8V) VDDLTP18 +1.8V
VDD33 +3.3V VDDLT18 +1.8V
IOPLLVDD18 +1.8V VDDLT33 NC

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, RS880M Power/GND
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Monday, May 03, 2010 Sheet 15 of 45
5 4 3 2 1
 5 4 3 2 1

CS1
1 2 US3A

150P_0402_50V8J~D RS2 P1
SB820M Part 1 of 5
W2
A_RST# A_RST#_R PCIE_RST# PCICLK0 PCICLK1
2 1 33_0402_5%~D L1 A_RST# PCICLK1/GPO36 W1 PCICLK1 <17>
W3 PCICLK2

PCI CLKS
PCICLK2/GPO37 PCICLK2 <17>
CS2 1 2 0.1U_0402_16V7K PCIE_NRX_STX_P0_C AD26 W4 PCICLK3
<12> PCIE_NRX_STX_P0 A_TX0P PCICLK3/GPO38 PCICLK3 <17>
CS3 1 2 0.1U_0402_16V7K PCIE_NRX_STX_N0_C AD27 Y1 PCICLK4
<12> PCIE_NRX_STX_N0 A_TX0N PCICLK4/14M_OSC/GPO39 PCICLK4 <17>
CS4 1 2 0.1U_0402_16V7K PCIE_NRX_STX_P1_C AC28
<12> PCIE_NRX_STX_P1 PCIE_NRX_STX_N1_C A_TX1P PCIRST#
<12> PCIE_NRX_STX_N1
CS5 1 2 0.1U_0402_16V7K AC29 A_TX1N PCIRST# V2 RS3 1 2 33_0402_5%~D PCI_RST# PCI_RST#
CS6 1 2 0.1U_0402_16V7K PCIE_NRX_STX_P2_C AB29
<12> PCIE_NRX_STX_P2 CS8 0.1U_0402_16V7K PCIE_NRX_STX_N2_C A_TX2P
<12> PCIE_NRX_STX_N2 1 2 AB28 A_TX2N 1
CS9 1 2 0.1U_0402_16V7K PCIE_NRX_STX_P3_C AB26 AA1
<12> PCIE_NRX_STX_P3 CS10 0.1U_0402_16V7K PCIE_NRX_STX_N3_C A_TX3P AD0/GPIO0 CS7
<12> PCIE_NRX_STX_N3 1 2 AB27 A_TX3N AD1/GPIO1 AA4
D AA3 SB_GPIO2_R D
AD2/GPIO2 150P_0402_50V8J~D
PCIE_NTX_SRX_P0 2
<12> PCIE_NTX_SRX_P0 AE24 A_RX0P AD3/GPIO3 AB1
<12> PCIE_NTX_SRX_N0 PCIE_NTX_SRX_N0 AE23 AA5
PCIE_NTX_SRX_P1 A_RX0N AD4/GPIO4
<12> PCIE_NTX_SRX_P1 AD25 A_RX1P AD5/GPIO5 AB2

PCI EXPRESS INTERFACES

<12> PCIE_NTX_SRX_N1 PCIE_NTX_SRX_N1 AD24 AB6
PCIE_NTX_SRX_P2 A_RX1N AD6/GPIO6
<12> PCIE_NTX_SRX_P2 AC24 A_RX2P AD7/GPIO7 AB5
<12> PCIE_NTX_SRX_N2 PCIE_NTX_SRX_N2 AC25 AA6
PCIE_NTX_SRX_P3 A_RX2N AD8/GPIO8
<12> PCIE_NTX_SRX_P3 AB25 A_RX3P AD9/GPIO9 AC2
<12> PCIE_NTX_SRX_N3 PCIE_NTX_SRX_N3 AB24 AC3
A_RX3N AD10/GPIO10
AD11/GPIO11 AC4
+PCIE_VDDR RS1 2 1 590_0402_1% PCIE_CAL_P AD29 AC1
PCIE_CALRP AD12/GPIO12 NB GPP PORT 0 LAN
RS4 2 1 2K_0402_1%~D PCIE_CAL_N AD28 PCIE_CALRN AD13/GPIO13 AD1 PCI_AD27 1 2 SB_GPIO27# SB_GPIO27# <20>
AD2 RS108 0_0402_5%
AD14/GPIO14 PCI_AD26 SB_GPIO26# NB GPP PORT 1 WLAN
AA28 GPP_TX0P AD15/GPIO15 AC6 1 2 SB_GPIO26# <28>
CS11 AA29 AE2 RS109 0_0402_5%
0.1U_0402_16V7K +3VALW GPP_TX0N AD16/GPIO16 SB_GPIO2_R SB_GPIO2# NB GPP PORT 2 WWAN
Y29 GPP_TX1P AD17/GPIO17 AE1 1 2 SB_GPIO2# <28>
RS110 0_0402_5%
it can be swap if need 2 1
Y28
Y26
GPP_TX1N AD18/GPIO18 AF8
AE3
GPP_TX2P AD19/GPIO19
Y27 GPP_TX2N AD20/GPIO20 AF1
W28 GPP_TX3P AD21/GPIO21 AG1
W29 GPP_TX3N AD22/GPIO22 AF2
5
AMD AE9 PCI_AD23
AD23/GPIO23 PCI_AD23 <17>
SB_GPIO_PCIE_RST# 2 US8 AA22 AD9 PCI_AD24
P

<18> SB_GPIO_PCIE_RST# B GPP_RX0P AD24/GPIO24 PCI_AD24 <17>

Y 4 PLT_RST# PLT_RST# <13,20,26,28> Y21 GPP_RX0N AD25/GPIO25 AC11 PCI_AD25
PCI_AD25 <17>
A_RST# 1 AA25 AF6 PCI_AD26
A GPP_RX1P AD26/GPIO26 PCI_AD26 <17>
G

AA24 AF4 PCI_AD27

GPP_RX1N AD27/GPIO27 PCI_AD27 <17>
NC7SZ08P5X_NL_SC70-5 W23 AF3 PCI_AD28 PCI_AD29 1 2 SB_MEMHOT# SB_MEMHOT# <7>
PCI_AD28 <17>
3

GPP_RX2P AD28/GPIO28
1
100K_0402_5%

V24 AH2 PCI_AD29 RS99 0_0402_5%

GPP_RX2N AD29/GPIO29 PCI_AD29 <17>
W24 GPP_RX3P AD30/GPIO30 AG2
RS5 W25 AH3
@ RS6 GPP_RX3N AD31/GPIO31
2 1 0_0402_5% CBE0# AA8
AD5
2

C CBE1# C
@ CBE2# AD8

PCI INTERFACE
CBE3# AA10
AE8 CS14
FRAME# 18P_0402_50V8J
DEVSEL# AB9
CLK_SB_CLK_P RS9 1 2 0_0402_5% CLK_SB_CLK_P_R M23 AJ3 2 1 SB_32KHI
<13> CLK_SB_CLK_P CLK_SB_CLK_N RS10 1 CLK_SB_CLK_N_R PCIE_RCLKP/NB_LNK_CLKP IRDY#
<13> CLK_SB_CLK_N 2 0_0402_5% P23 PCIE_RCLKN/NB_LNK_CLKN TRDY# AE7
AC5 YS1
PAR

1
CLK_NB_REFCLK_P RS94 1 2 0_0402_5% CLK_NB_REFCLK_P_R U29 AF5 4 3
<13> CLK_NB_REFCLK_P CLK_NB_REFCLK_N RS95 1 CLK_NB_REFCLK_N_R U28 NB_DISP_CLKP STOP# OUT NC
<13> CLK_NB_REFCLK_N 2 0_0402_5% NB_DISP_CLKN PERR# AE6 RS17
AE4 20M_0402_5%~D 1 2
CLK_HTREFCLK_P RS13 1 CLK_HTREFCLK_P_R SERR# IN NC
<13> CLK_HTREFCLK_P 2 0_0402_5% T26 NB_HT_CLKP REQ0# AE11
CLK_HTREFCLK_N RS14 1 2 0_0402_5% CLK_HTREFCLK_N_R T27 AH5 32.768KHZ_12.5PF_1TJS125BJ4A421P

2
<13> CLK_HTREFCLK_N NB_HT_CLKN REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41 AH4
CLK_HT_CPU_P RS15 1 2 0_0402_5% CLK_HT_CPU_P_R V21 AC12 PCI_ROM_DAT TS10 2 1 SB_32KH0
<8> CLK_HT_CPU_P CLK_HT_CPU_N RS16 1 CLK_HT_CPU_N_R CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42 need check foot print and
<8> CLK_HT_CPU_N 2 0_0402_5% T21 CPU_HT_CLKN GNT0# AD12
AJ5 CS15 replace to SJ100003P00
GNT1#/GPO44 18P_0402_50V8J
V23 SLT_GFX_CLKP GNT2#/GPO45 AH6
T23 AB12 PCI_ROM_CLK TS11
SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 EC_CLKRUN#
CLKRUN# AB11 EC_CLKRUN# <26>
CLK_PCIE_LAN_P RS18 1 2 0_0402_5% CLK_PCIE_LAN_P_R L29 AD7 LOCK# TS1
<20> CLK_PCIE_LAN_P CLK_PCIE_LAN_N RS19 1 CLK_PCIE_LAN_N_R GPP_CLK0P LOCK#
<20> CLK_PCIE_LAN_N 2 0_0402_5% L28 GPP_CLK0N
INTE#/GPIO32 AJ6
CLK_PCIE_WLAN_P RS20 1 2 0_0402_5% CLK_PCIE_WLAN_P_R N29 AG6 GPIO33 RS100 1 2 20K_0402_5%
<28> CLK_PCIE_WLAN_P GPP_CLK1P INTF#/GPIO33 CLK_DEBUG_PORT <17>
CLK_PCIE_WLAN_N RS21 1 2 0_0402_5% CLK_PCIE_WLAN_N_R N28 AG4
<28> CLK_PCIE_WLAN_N GPP_CLK1N INTG#/GPIO34 PCI_PIRQH#
INTH#/GPIO35 AJ4 TS2
CLK_PCIE_WWAN_P RS22 1 2 0_0402_5% CLK_PCIE_WWAN_P_R M29 CLK_DEBUG_PORT 1 2 CLK_DEBUG_PORT_1
<28> CLK_PCIE_WWAN_P GPP_CLK2P CLK_DEBUG_PORT_1 <28>
CLK_PCIE_WWAN_N RS23 1 2 0_0402_5% CLK_PCIE_WWAN_N_R M28 RS113 0_0402_5%
<28> CLK_PCIE_WWAN_N GPP_CLK2N @
T25 RS24
GPP_CLK3P CLK_PCI_ECLPC_CLK0_R 1
V25 GPP_CLK3N LPCCLK0 H24 2 22_0402_5%~D CLK_PCI_EC CLK_PCI_EC <17,26>
H25 CLK_DEBUG_PORT
LPCCLK1

CLOCK GENERATOR
L24 J27 LPC_AD0
B GPP_CLK4P LAD0 LPC_LAD0 <26,28> B
L23 J26 LPC_AD1
GPP_CLK4N LAD1 LPC_LAD1 <26,28>
H29 LPC_AD2
LAD2 LPC_LAD2 <26,28>
LPC_AD3

LPC
P25 GPP_CLK5P LAD3 H28 LPC_LAD3 <26,28>
M25 G28 LPC_FRAME#
GPP_CLK5N LFRAME#
LDRQ0# J25 LDRQ0#
LPC_LFRAME# <26,28>
TS3
For Compal LPC debug card
P29 AA18 LDRQ1# TS4
GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 IRQ_SERIRQ
P28 GPP_CLK6N SERIRQ/GPIO48 AB19 IRQ_SERIRQ <26>
Place close to US3 N26
RF reserved GPP_CLK7P CLK_PCI_EC @CS12
@ CS12 1
N27 GPP_CLK7N 2 10P_0402_50V8J~D
CS13 @ 10P_0402_50V8J~D G21 ALLOW_LDTSTOP
ALLOW_LDTSTP/DMA_ACTIVE# ALLOW_LDTSTOP <13>
2 1 T29 GPP_CLK8P PROCHOT# H21 CPU_PROCHOT# <8>
T28 GPP_CLK8N LDT_PG K19 CPU_PWRGD <8>
CPU

LDT_STP# G22 LDT_STOP# <8,13>

RS7 J24 LDT_RST#
LDT_RST# LDT_RST# <8>
CLK_48M 1 33_0402_5%~D CLK_48M_R
<21> CLK_48M 2 L25 14M_25M_48M_OSC Place close to US3 EMI reserved
C1 SB_32KHI
CS16 32K_X1
2 1 SB25M_X1 L26 C2 SB_32KH0
25M_X1 32K_X2
1

12P_0402_50V8J D2 RTC_CLK RS26 1 @ 2 10K_0402_5%

RTCCLK
2

INTRUDER_ALERT# B2
YS2 RS27 L27 B1 +VBAT_IN 1 2 +RTC_CELL
RTC

25M_X2 VDDBT_RTC_G

0.1U_0402_16V7K
25MHz_12P_X5H025000FC1H-H 1M_0402_5%~D RS105 510_0402_1%

1U_0402_6.3V6K
1 1
1

1
CS17 SB820M_FCBGA605~D
2 1 SB25M_X2 CS18 CS19 PJP1

1
12P_0402_50V8J @ 2 2 @ JUMP_43X39

2
RTC RESET

2
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SB820M PCIE/PCI/LPC/CKG/RTC
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 16 of 45
5 4 3 2 1
 5 4 3 2 1

SB_HD CLK_DEBUG
_SDOUT PCICLK1 PCICLK2 PCICLK3 PCICLK4 CLK_PCI_EC _PORT GPIO200 GPIO199

PULL LOW POWER ALLOW Watchdog USE non_Fusion EC CLKGEN

HIGH MODE PCIE Gen2 Timer DEBUG CLOCK MODE ENABLED ENABLED H,H = Reserved
DEFAULT Enabled STRAP DEFAULT DEFAULT H,L = SPI ROM
L,H = LPC ROM (Default)
PULL PERFORMANCE FORCE Watchdog IGNORE FUSION EC CLKGEN L,L = FWH ROM
LOW MODE PCIE Gen1 Timer DEBUG CLOCK MODE DISABLED DISABLED
D Disabled STRAP DEFAULT D
DEFAULT DEFAULT DEFAULT

SATA HDD US3B

SB820M
<29> SATA_STX_DRX_P0
<29> SATA_STX_DRX_N0
CS20 1
CS21 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_STX_DRX_P0_C
SATA_STX_DRX_N0_C
AH9
AJ9
SATA_TX0P
SATA_TX0N Part 2 of 5
FC_CLK
FC_FBCLKOUT
AH28
AG28
REQUIRED STRAPS
FC_FBCLKIN AF26
<29> SATA_SRX_DTX_N0 SATA_SRX_DTX_N0 AJ8
SATA_SRX_DTX_P0 SATA_RX0N
<29> SATA_SRX_DTX_P0 AH8 SATA_RX0P FC_OE#/GPIOD145 AF28
AG29 +VDDIO_AZ +3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW
FC_AVD#/GPIOD146
AH10 SATA_TX1P FC_WE#/GPIOD148 AG26
AJ10 SATA_TX1N FC_CE1#/GPIOD149 AF27

1
FC_CE2#/GPIOD150 AE29
AG10 AF29 RS29 RS30 RS31 RS32 RS33 RS34 RS35 RS36 RS37
SATA_RX1N FC_INT1/GPIOD144 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
AF10 SATA_RX1P FC_INT2/GPIOD147 AH27
@ @ @ @ @
AG12 AJ27

2
SATA_TX2P FC_ADQ0/GPIOD128
AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26
FC_ADQ2/GPIOD130 AH25 <18> SB_HD_SDOUT
AJ12 SATA_RX2N FC_ADQ3/GPIOD131 AH24 <16> PCICLK1
AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23 <16> PCICLK2
FC_ADQ5/GPIOD133 AH23 <16> PCICLK3
AH14 SATA_TX3P FC_ADQ6/GPIOD134 AJ22 <16> PCICLK4
AJ14 SATA_TX3N FC_ADQ7/GPIOD135 AG21 <16,26> CLK_PCI_EC
FC_ADQ8/GPIOD136 AF21 <16> CLK_DEBUG_PORT
AG14 SATA_RX3N FC_ADQ9/GPIOD137 AH22 <18> GP199
AF14 SATA_RX3P FC_ADQ10/GPIOD138 AJ23 <18> GP200
FC_ADQ11/GPIOD139 AF23

1
+3VS AG17 AJ24

FLASH
SATA_TX4P FC_ADQ12/GPIOD140 RS38 RS39 RS40 RS41 RS42 RS43 RS44 RS45 RS46
AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25
C AG25 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% C
FC_ADQ14/GPIOD142
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26 @ @ @ @
1

AH17

2
RS111 SATA_RX4P

SERIAL ATA
10K_0402_5% AJ18 SATA_TX5P
AH18 SATA_TX5N FANOUT0/GPIO52 W5
W6
2

SATA_ACT#_R FANOUT1/GPIO53 SB_PROCHOT#_R check list: LCP ROM: GP199=NC, GP200=PD

AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19 +3VS Datasheet: LCP ROM: GP199=PU, GP200=PD
SATA_RX5P
FANIN0/GPIO56 W7
FANIN1/GPIO57 V9

10K_0402_5%

10K_0402_5%
RS47 2 1 1K_0402_1%~D SATA_CALP AB14 SATA_CALRP FANIN2/GPIO58 W8

1
+AVDD_SATA RS48 2 1 931_0402_1% SATA_CALN AA14 SATA_CALRN
TEMPIN0/GPIO171 B6

RS101

RS102
TEMPIN1/GPIO172 A6
SATA_ACT#_R AD11 A5
<25> SATA_ACT#_R SATA_ACT#/GPIO67 TEMPIN2/GPIO173
B5

2 2
TEMPIN3/TALERT#/GPIO174 TEMP_COMM
TEMP_COMM C7

@ CS24 A3 QS1
SATA_X1 VIN0/GPIO175 Connect C7 and D8, then go to GND directly. SB_PROCHOT#_R
2 1 AD16 SATA_X1 VIN1/GPIO176 B4 3 1 SB_PROCHOT# <8>
A4 MMBT3904_NL_SOT23-3
VIN2/GPIO177
1

HW MONITOR

22P_0402_50V8J C5
VIN3/GPIO178
2

VIN4/GPIO179 A7
@ YS3 RS50 @ B7 LOM_POWER 1 RS103 2 0_0402_5% EN_WOL# EN_WOL# <26,30>
25MHz_12P_X5H025000FC1H-H 1M_0402_5%~D VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181 B8
AC16 A8 @ +3VALW
CS26
1

@ CS25 SATA_X2 VIN7/GBE_LED3/GPIO182

2 1 SATA_X2 1 2

2
10K_0402_5%

10K_0402_5%
22P_0402_50V8J 0.1U_0402_16V7K
SB_SI_SPI_SO J5 G27 20mils
B SB_SO_SPI_SI SPI_DI/GPIO164 NC1 RS51 RS52 US9 B
E2 SPI_DO/GPIO163 NC2 Y2
SPI ROM

SB_SPI_CLK K4 @ @ 8 4
SB_SPI_CS# SPI_CLK/GPIO162 VCC VSS
K9

1
SPI_CS1#/GPIO165
G2 ROM_RST#/GPIO161 3 W
SPI_HOLD# 7
SB820M_FCBGA605~D HOLD
SB_SPI_CS# 1 S
SB_SPI_CLK 6 C
SB_SO_SPI_SI 5 2 SB_SI_SPI_SO
+3VS +3VS +3VS +3VS +3VS +3VS +3VS D Q
MX25L8005M2C-15G_SO8
@
DEBUG STRAPS
1

RS53 RS54 RS55 RS56 RS57 RS58 RS59

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
2

PULL USE PCI DISABLE ILA USE FC USE DEFAULT DISABLE PCI
PCI_AD29 HIGH PLL AUTORUN PLL PCIE STRAPS MEM BOOT
<16> PCI_AD29 PCI_AD28
<16> PCI_AD28 PCI_AD27 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
<16> PCI_AD27 PCI_AD26
<16> PCI_AD26 PCI_AD25
<16> PCI_AD25 PCI_AD24
<16> PCI_AD24 PULL BYPASS ENABLE ILA BYPASS FC USE EEPROM ENABLE PCI
PCI_AD23
<16> PCI_AD23 LOW PCI PLL AUTORUN PLL PCIE STRAPS MEM BOOT

A A
1

RS60 RS61 RS62 RS63 RS64

2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
@ @ @ @ @
DELL CONFIDENTIAL/PROPRIETARY
2

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SB820M SATA/FLASH/Strap
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23] PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 17 of 45
5 4 3 2 1
 5 4 3 2 1

SSIC circuit for EMI

+3VS +3VS_SSIC
NONWWAN@ US3D
1 2 WWAN@ RS104 1 2 0_0402_5% CPU_MEMHOT#_R J2 A10
<7> CPU_MEMHOT# PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
RS117 0_0402_5% HDA_BITCLK 1 2 SB_RI# K1
<26> SB_RI# RI#/GEVENT22#
SSEXTR RS112 0_0402_5% D3 G19 USB_RCOMP 1 2
SIO_SLP_S3# SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP 11.8K_0402_1%~D RS65
<26> SIO_SLP_S3# F1 SLP_S3#
1

HDA_BITCLK_SSIC <26> SIO_SLP_S5# SIO_SLP_S5# H1 SLP_S5#

ACPI / WAKE UP EVENTS

RS115 PBTN_OUT# F2
D <26> PBTN_OUT# PWR_BTN# D
Bypass Schematics SB_PWRGD
2.2K_0402_5% <8,13,26> SB_PWRGD
SUS_STAT#
H5
G6
PWR_GOOD SB820M J10
<13> SUS_STAT# SUS_STAT# USB_FSD1P/GPIO186
NONWWAN@ TS5 SB_TEST0 B3 Part 4 of 5 H11

USB MISC
2

TS6 SB_TEST1 TEST0 USB_FSD1N

C4 TEST1/TMS
NONWWAN@ TS7 SB_TEST2 F6 H9
CS81 GATEA20 TEST2 USB_FSD0P/GPIO185
<26> GATEA20 AD21 GA20IN/GEVENT0# USB_FSD0N J8
Use PCS3P73Z21BWG footprint for layout first 0.1U_0402_16V7K KB_RST# AE21

USB 1.1
<26> KB_RST# KBRST#/GEVENT1#
1 2 SIO_EXT_SCI# K2 B12
It modify pinout for ECS2P8211 +3VS_SSIC Need confirm with BIOS <26>
team SIO_EXT_SCI#
SIO_EXT_SMI# J29
LPC_PME#/GEVENT3# USB_HSD13P
A12
<26> SIO_EXT_SMI# LPC_SMI#/GEVENT23# USB_HSD13N
CS82 NONWWAN@ H2
US10 NONWWAN@ 0.01U_0402_16V7K AMD TS12 COLD_RST_TP GEVENT5#
J1 SYS_RESET#/GEVENT19# USB_HSD12P F11
HDA_BITCLK 1 8 1 2 PCIE_WAKE# H6 E11
CLKIN VDD <20,26,28> PCIE_WAKE# WAKE#/GEVENT8# USB_HSD12N
F3 IR_RX1/GEVENT20#
2 7 SSEXTR H_THERMTRIP# J6 E14
RESERVED SSEXTR <8> H_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P
<13> NB_PWRGD_SB NB_PWRGD_SB AC19 E12
NB_PWRGD USB_HSD11N
3 NC RESERVED 6
EC_RSMRST# G1 J12
<26> EC_RSMRST# RSMRST# USB_HSD10P
4 5 HDA_BITCLK_SSIC_R J14
GND MODOUT USB_HSD10N
AD19 CLK_REQ4#/SATA_IS0#/GPIO64
P3P8211 AMD AA16 A13
CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P USB20_P9 <27>
2 1 <16> SB_GPIO_PCIE_RST# SB_GPIO_PCIE_RST# AB21 B13 Camera
SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N USB20_N9 <27>
CLKREQ_LAN# AC18
<20> CLKREQ_LAN# CLK_REQ0#/SATA_IS3#/GPIO60
CS22 8.2P_0402_50V8D~D AF20 D13
SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P USB20_P8 <21>
NONWWAN@ AE19 C13 Card Reader (Sub-board)
SATA_IS5#/FANIN3/GPIO59 USB_HSD8N USB20_N8 <21>
Place CS22 closed to US10 <25> SB_SPKR SB_SPKR AF19
MEM_SMBCLK_R SPKR/GPIO66
AD22 SCL0/GPIO43 USB_HSD7P G12
MEM_SMBDATA_R AE22 G14

USB 2.0
NONWWAN@ SB_SMB_CLK1 SDA0/GPIO47 USB_HSD7N
F5 SCL1/GPIO227
HDA_BITCLK_SSIC_R 1 2 HDA_BITCLK_SSIC SB_SMB_DAT1 F4 G16
HDA_BITCLK_SSIC <25> SDA1/GPIO228 USB_HSD6P USB20_P6 <28>
RS119 33_0402_5%~D CLKREQ_WWAN# AH21 G18 Bluetooth
<28> CLKREQ_WWAN# CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N USB20_N6 <28>
CLKREQ_WLAN# AB18
<28> CLKREQ_WLAN# CLK_REQ1#/FANOUT4/GPIO61
E1 IR_LED#/LLB#/GPIO184 USB_HSD5P D16 USB20_P5 <28>
C SB_SHUTDOWN# AJ21 C
SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD5N C16 USB20_N5 <28> MiniCard- WWAN (Sub-board)
SP_DDR3_RST#
sideport <14> SP_DDR3_RST# H4

GPIO
DDR3_RST#/GEVENT7#
D5 GBE_LED0/GPIO183 USB_HSD4P B14 USB20_P4 <28>
D7 GBE_LED1/GEVENT9# USB_HSD4N A14 USB20_N4 <28> MiniCard- WLAN
G5 GBE_LED2/GEVENT10#
K3 GBE_STAT0/GEVENT11# USB_HSD3P E18
MEM_SMBCLK RS25 1 2 22_0402_5%~D MEM_SMBCLK_R AA20 E16
<10,11,13> MEM_SMBCLK CLK_REQG#/GPIO65/OSCIN/IDLEEXT# USB_HSD3N
MEM_SMBDATA RS28 1 2 22_0402_5%~D MEM_SMBDATA_R
<10,11,13> MEM_SMBDATA
USB_HSD2P J16 USB20_P2 <23>
H3 BLINK/USB_OC7#/GEVENT18# USB_HSD2N J18 USB20_N2 <23> USB Port 2
D1 USB_OC6#/IR_TX1/GEVENT6#
0_0402_5% 1 2 RS66 SMB_ALERT#_R E4 B17
<8,13,26> SMB_ALERT# USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P USB20_P1 <23>
EC_LID_OUT#

USB OC
<26> EC_LID_OUT# AMD TS13
D4 USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N A17 USB20_N1 <23> USB Port 1 (Sub-board)
USB_OC3#
Place CS80 close to US3 USB_OC2#
E8
F7
USB_OC3#/AC_PRES/TDO/GEVENT15#
A16
RF reserved <23> USB_OC2# USB_OC2#/TCK/GEVENT14# USB_HSD0P USB20_P0 <25>
@ USB_OC1# E7 B16 USB Port 0 (Sub-board)
<23> USB_OC1# USB_OC1#/TDI/GEVENT13# USB_HSD0N USB20_N0 <25>
2 1 USB_OC0# F8
<23> USB_OC0# USB_OC0#/TRST#/GEVENT12#
CS80 27P_0402_50V8J

HDA_BITCLK RS67 1 2 33_0402_5%~D SB_HD_BITCLK M3 D25 SB_SMB_CLK2

RS68 1 SB_HD_SDOUT AZ_BITCLK SCL2/GPIO193 SB_SMB_DAT2
<25> HDA_SDOUT 2 33_0402_5%~D N1 AZ_SDOUT SDA2/GPIO194 F23
RS96 1 2 33_0402_5%~D SB_HD_SDIN0 L2 B26 SB_SMB_CLK3
<25> HDA_SDIN0 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 SB_SMB_CLK3 <8>Low Voltage SMBUS for CPU TSI
<17> SB_HD_SDOUT SB_HD_SDOUT SB_HD_SDIN1 M2 E26 SB_SMB_DAT3
AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 SB_SMB_DAT3 <8>
SB_HD_SDIN2 M1 F25
SB_HD_SDIN3 AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197
M4 E22

HD AUDIO
RS69 1 SB_HD_SYNC AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198
<25> HDA_SYNC 2 33_0402_5%~D N2 AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199 F22 GP199 <17>
RS70 1 2 33_0402_5%~D SB_HD_RST# P2 E21
<25> HDA_RST# AZ_RST# EC_PWM3/EC_TIMER3/GPIO200 GP200 <17>
RS71 1 @ 2 10K_0402_5% SB_SPKR G24
GBE_COL KSI_0/GPIO201
T1 GBE_COL KSI_1/GPIO202 G25
RS72 1 @ 2 10K_0402_5% SB_HD_BITCLK GBE_CRS T4 E28
B GBE_CRS KSI_2/GPIO203 B
L6 GBE_MDCK KSI_3/GPIO204 E29
RS73 1 @ 2 10K_0402_5% SB_HD_SDIN0 GBE_MDIO L5 D29
GBE_MDIO KSI_4/GPIO205
T9 GBE_RXCLK KSI_5/GPIO206 D28
U1 GBE_RXD3 KSI_6/GPIO207 C29
RS98 1 2 10K_0402_5% SB_HD_SDIN1 U3 C28
GBE_RXD2 KSI_7/GPIO208
T2 GBE_RXD1

GBE LAN
RS106 1 2 10K_0402_5% SB_HD_SDIN2 U2 B28
GBE_RXD0 KSO_0/GPIO209
T5 GBE_RXCTL/RXDV KSO_1/GPIO210 A27
RS107 1 2 10K_0402_5% SB_HD_SDIN3 GBE_RXERR V5 B27
GBE_RXERR KSO_2/GPIO211
P5 GBE_TXCLK KSO_3/GPIO212 D26
+3VS M5 A26

EMBEDDED CTRL
GBE_TXD3 KSO_4/GPIO213
P9 GBE_TXD2 KSO_5/GPIO214 C26
RS79 1 @ 2 10K_0402_5% SB_SHUTDOWN# T7 A24
GBE_TXD1 KSO_6/GPIO215
P7 GBE_TXD0 KSO_7/GPIO216 B25
RS80 1 2 4.7K_0402_5% SUS_STAT# M7 A25
+3VALW GBE_TXCTL/TXEN KSO_8/GPIO217
P4 GBE_PHY_PD KSO_9/GPIO218 D24
M9 GBE_PHY_RST# KSO_10/GPIO219 B24
GBE_PHY_INTR V7 C24
GBE_PHY_INTR KSO_11/GPIO220
KSO_12/GPIO221 B23
RS81 1 2 10K_0402_5% SB_SMB_CLK1 TS8 PS2_DAT E23 A23
PS2_CLK PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222
TS9 E24 PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223 D22
RS82 1 2 10K_0402_5% SB_SMB_DAT1 RS84 1 2 2.2K_0402_5% MEM_SMBCLK F21 C22
SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224

EMBEDDED CTRL
G29 FC_RST#/GPO160 KSO_16/GPIO225 A22
RS83 1 2 10K_0402_5% SB_SMB_CLK2 RS86 1 2 2.2K_0402_5% MEM_SMBDATA B22
AC_OK# KSO_17/GPIO226
D27 PS2KB_DAT/GPIO189
RS85 1 2 10K_0402_5% SB_SMB_DAT2 F28 PS2KB_CLK/GPIO190
F29 PS2M_DAT/GPIO191
E27 PS2M_CLK/GPIO192
GbE Controller Disabled

RS77 1 2 10K_0402_5% GBE_MDIO AC_OK# SB820M_FCBGA605~D

A RS78 1 2 10K_0402_5% GBE_PHY_INTR A

RS74 1 2 10K_0402_5% GBE_COL

1

D
RS75 1 2 10K_0402_5% GBE_CRS ACIN 2 QS2

RS76 1 GBE_RXERR
<26,34> ACIN
G SSM3K7002FU_SC70-3 DELL CONFIDENTIAL/PROPRIETARY
2 10K_0402_5% S
3

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SB820M USB/ACPI/AZ/GPIO
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 11, 2010 Sheet 18 of 45
5 4 3 2 1
 5 4 3 2 1

US3C +1.1VS US3E

+3VS RS87 RS88
3.3V 78mA +3VS_VDDIO_SB SB820M Part 3 of 5 N13 +1.1VS_VDD_SB
1.1V 790mA
1 2 AH1 VDDIO_33_PCIGP_1 VDDCR_11_1 1 2 SB820M

10U_0603_6.3V6M
22U_0805_6.3V6M~D

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15 Y14 VSSIO_SATA_1 VSS_1 AJ2
0_0603_5% 1 1 1 1 Y19 N17 1 1 1 1 1 0_0805_5% Y16 A28
VDDIO_33_PCIGP_3 VDDCR_11_3 VSSIO_SATA_2 VSS_2
AE5 U13 AB16 A2

CORE S0
CS38 CS27 CS28 CS29 VDDIO_33_PCIGP_4 VDDCR_11_4 CS30 CS31 CS32 CS39 CS33 VSSIO_SATA_3 VSS_3
AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17 AC14 VSSIO_SATA_4 VSS_4 E5
AA2 VDDIO_33_PCIGP_6 VDDCR_11_6 V12 AE12 VSSIO_SATA_5 VSS_5 D23
2 2 2 2 2 2 2 2 2
AB4 VDDIO_33_PCIGP_7 VDDCR_11_7 V18 AE14 VSSIO_SATA_6 VSS_6 E25
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W12 AF9 VSSIO_SATA_7 VSS_7 E6

PCI/GPIO I/O
AA7 VDDIO_33_PCIGP_9 VDDCR_11_9 W18 AF11 VSSIO_SATA_8 VSS_8 F24
AA9 +1.1VS AF13 N15
D VDDIO_33_PCIGP_10 LS1 VSSIO_SATA_9 VSS_9 D
AF7 VDDIO_33_PCIGP_11 1.1V 382mA AF16 VSSIO_SATA_10 VSS_10 R13
AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 +1.1VS_CKVDD 2 1 AG8 VSSIO_SATA_11 VSS_11 R17

22U_0805_6.3V6M~D
0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
K29 FBMJ2125HS420-T_2P_0805 AH7 T10
VDDAN_11_CLK_2 New PART VSSIO_SATA_12 VSS_12
VDDAN_11_CLK_3 J28 1 1 1 1 1 AH11 VSSIO_SATA_13 VSS_13 P10
FBMJ2125HS420-T
RS89
0.15mA VDDAN_11_CLK_4 K26
CS34 CS35 CS40 CS36 CS37 42 ohm 4A
AH13 VSSIO_SATA_14 VSS_14 V11
VDDAN_11_CLK_5 J21 AH16 VSSIO_SATA_15 VSS_15 U15
1 2+VDDIO_18_FC AF22 VDDIO_18_FC_1 VDDAN_11_CLK_6 J20 AJ7 VSSIO_SATA_16 VSS_16 M18
2 2 2 2 2
AE25 K21 AJ11 V19

CLKGEN I/O
0_0603_5% VDDIO_18_FC_2 VDDAN_11_CLK_7 VSSIO_SATA_17 VSS_17
AF24 VDDIO_18_FC_3 VDDAN_11_CLK_8 J22 AJ13 VSSIO_SATA_18 VSS_18 M11

FLASH I/O
AC22 VDDIO_18_FC_4 AJ16 VSSIO_SATA_19 VSS_19 L12
VSS_20 L18
Not use Flash I/O V1 A9 J7
VDDRF_GBE_S VSSIO_USB_1 VSS_21
POWER 2mA B10 VSSIO_USB_2 VSS_22 P3
VDDIO_33_GBE_S M10 K11 VSSIO_USB_3 VSS_23 V4
B9 VSSIO_USB_4 VSS_24 AD6
+3VS_VDDPL_PCIE AE28 D10 AD4
+1.1VS +PCIE_VDDR VDDPL_33_PCIE VSSIO_USB_5 VSS_25

GBE LAN
D12 VSSIO_USB_6 VSS_26 AB7
LS2 1.1V 690mA D14 AC9
VSSIO_USB_7 VSS_27

PCI EXPRESS
1 2 U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 82mA D17 VSSIO_USB_8 VSS_28 V8
22U_0805_6.3V6M~D

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K
FBMJ2125HS420-T_2P_0805 V22 L9 E9 W9
New PART VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 Not use GBE LAN VSSIO_USB_9 VSS_29
1 1 1 1 1 V26 VDDAN_11_PCIE_3 F9 VSSIO_USB_10 VSS_30 W10
FBMJ2125HS420-T V27 F12 AJ28
42 ohm 4A CS41 CS42 CS43 CS44 CS45 VDDAN_11_PCIE_4 VSSIO_USB_11 VSS_31
V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6 F14 VSSIO_USB_12 VSS_32 B29
@ V29 P8 21mA F16 U4
2 2 2 2 2 VDDAN_11_PCIE_6 VDDIO_GBE_S_2 VSSIO_USB_13 VSS_33
W22 VDDAN_11_PCIE_7 C9 VSSIO_USB_14 VSS_34 Y18
W26 VDDAN_11_PCIE_8 G11 VSSIO_USB_15 VSS_35 Y10
F18 Y12

GROUND
VSSIO_USB_16 VSS_36
D9 VSSIO_USB_17 VSS_37 Y11
+3VALW_SB +3VALW H12 AA11
+1.1VS +AVDD_SATA +3VS_VDDPL_SATA RS90 VSSIO_USB_18 VSS_38
AD14 VDDPL_33_SATA H14 VSSIO_USB_19 VSS_39 AA12
LS3 1.1V 1.35A VDDIO_33_S_1 A21 +3VALW_SB 3.3V 49mA 1 2 H16 VSSIO_USB_20 VSS_40 G4

0.1U_0402_16V7K

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D
1 2 AJ20 VDDAN_11_SATA_1 VDDIO_33_S_2 D21 H18 VSSIO_USB_21 VSS_41 J4
22U_0805_6.3V6M~D

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

C FBMJ2125HS420-T_2P_0805 AF18 B21 0_0603_5% J11 G8 C

VDDAN_11_SATA_4 VDDIO_33_S_3 1 1 1 VSSIO_USB_22 VSS_42
1 1 1 1 1 AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10 J19 VSSIO_USB_23 VSS_43 G9
New PART AG19 L10 CS51 CS52 CS53 K12 M12

SERIAL ATA
FBMJ2125HS420-T CS46 CS47 CS48 CS49 CS50 VDDAN_11_SATA_3 VDDIO_33_S_5 VSSIO_USB_24 VSS_44
AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9 K14 VSSIO_USB_25 VSS_45 AF25
42 ohm 4A @ 2 2 2
AD18 T6 K16 H7

3.3V_S5 I/O
2 2 2 2 2 VDDAN_11_SATA_6 VDDIO_33_S_7 VSSIO_USB_26 VSS_46
AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8 K18 VSSIO_USB_27 VSS_47 AH29
H19 VSSIO_USB_28 VSS_48 V10
+1.1VALW_SB +1.1VALW P6
RS91 VSS_49
VSS_50 N4
F26 +1.1VALW_SB 1.1V 115mA 1 2 Y4 L4

CORE S5
+3VALW +3VALW_AVDDUSB VDDCR_11_S_1 EFUSE VSS_51

1U_0402_6.3V6K

1U_0402_6.3V6K
LS4 A18 VDDAN_33_USB_S_1 VDDCR_11_S_2 G26 VSS_52 L8
3.3V 534mA A19 1 1 0_0603_5% D8
+3VALW_AVDDUSB VDDAN_33_USB_S_2 +VDDIO_AZ VSSAN_HWM
1 2 A20 VDDAN_33_USB_S_3 VDDIO_AZ_S M8 +VDDIO_AZ 3.3V 15mA
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

BLM21PG221SN1D_0805 B18 CS58 CS59 M19 M20

VDDAN_33_USB_S_4 VSSXL VSSPL_SYS
1 1 1 1 B19 VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 A11 +1.1VALW_VDDCR_USB
0805/220Ohm/2000mA 2 2
B20 VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 B11 1.1V 58mA

USB I/O
MPN:BLM21PG221SN1D CS54 CS55 CS56 CS57 C18 P21 H23
CPN:SM010026280 VDDAN_33_USB_S_7 VSSIO_PCIECLK_1 VSSIO_PCIECLK_14
C20 VDDAN_33_USB_S_8 P20 VSSIO_PCIECLK_2 VSSIO_PCIECLK_15 H26
220 ohm 2A 2 2 2 2
D18 VDDAN_33_USB_S_9 VDDPL_33_SYS M21 +3VS_VDDPL 3.3V 46mA M22 VSSIO_PCIECLK_3 VSSIO_PCIECLK_16 AA21
need SYMBOL D19 M24 AA23
VDDAN_33_USB_S_10 +1.1VALW_VDDPL VSSIO_PCIECLK_4 VSSIO_PCIECLK_17
D20 VDDAN_33_USB_S_11 VDDPL_11_SYS_S L22 1.1V 65mA M26 VSSIO_PCIECLK_5 VSSIO_PCIECLK_18 AB23
E19 VDDAN_33_USB_S_12 P22 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19 AD23
+1.1VALW +3VALW_PLL_USB

PLL
LS5
1.1V 88mA VDDPL_33_USB_S F19 3.3V 16mA P24 VSSIO_PCIECLK_7 VSSIO_PCIECLK_20 AA26
P26 VSSIO_PCIECLK_8 VSSIO_PCIECLK_21 AC26
+1.1VALW_VDDAN_USB +3VALW_HWM +3VALW
1 2 C11 VDDAN_11_USB_S_1 VDDAN_33_HWM_S D6 3.3V 12mA T20 VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 Y20
0.1U_0402_16V7K
2.2U_0402_6.3V6M~D

D11 LS6 T22 W21

BLM18EG221SN1D_2P_0603 1 VDDAN_11_USB_S_2 +3VALW_VDDXL VSSIO_PCIECLK_10 VSSIO_PCIECLK_23
1 VDDXL_33_S L20 3.3V 5mA 1 2 T24 VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 W20

0.1U_0402_16V7K

2.2U_0402_6.3V6M~D
V20 VSSIO_PCIECLK_12 VSSIO_PCIECLK_25 AE26
CS60 CS61 1 1 BLM18EG221SN1D_2P_0603 J23 L21
SB820M_FCBGA605~D VSSIO_PCIECLK_13 VSSIO_PCIECLK_26
VSSIO_PCIECLK_27 K20
2 2 CS62 CS63
2 2
Part 5 of 5
B @ B
SB820M_FCBGA605~D

+3VALW
@ LS9
+3VS +3VALW_HWM
3.3V 11mA 1 2

0.1U_0402_16V7K

2.2U_0402_6.3V6M~D
LS7
1 2 +3VS_VDDPL_PCIE +3VALW_AVDDUSB +3VALW_PLL_USB BLM18EG221SN1D_2P_0603
1 1
+3VS
0.1U_0402_16V7K
2.2U_0402_6.3V6M~D

RS97
BLM18EG221SN1D_2P_0603 1 1 +3VALW_AVDDUSB 1 2 +3VALW_PLL_USB LS8 CS70 CS71
0.1U_0402_16V7K
2.2U_0402_6.3V6M~D

+3VS_VDDPL 1 2 @
2 2

0.1U_0402_16V7K

2.2U_0402_6.3V6M~D
CS64 CS65 0_0603_5% 1 1 @
1 1 BLM18EG221SN1D_2P_0603
2 @ 2 CS66 CS67 Not use HWM
CS68 CS69
2 2
@ 2 2
+3VS
LS10
3.3V 15mA +VDDIO_AZ +3VALW
1 2 +3VS_VDDPL_SATA RS92
+1.1VALW
0.1U_0402_16V7K
2.2U_0402_6.3V6M~D

+VDDIO_AZ 1 2

2.2U_0402_6.3V6M~D
BLM18EG221SN1D_2P_0603 1 1 LS12
+1.1VALW_VDDPL 1 2 1 0_0402_5%
+1.1VALW

0.1U_0402_16V7K

2.2U_0402_6.3V6M~D
CS72 CS73

1
LS11 1 1 BLM18EG221SN1D_2P_0603 CS79
2 @ 2 +1.1VALW_VDDCR_USB RS93
1 2
2
10U_0603_6.3V6M
0.1U_0402_16V7K

0.1U_0402_16V7K

CS77 CS78 150_0402_1%

1 1 1 BLM18EG221SN1D_2P_0603
@ 2 2 @

2
CS74 CS75 CS76

A 2 2 2 CODEC VDDIO=+3VS A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SB820M Power/GND
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Monday, May 03, 2010 Sheet 19 of 45
5 4 3 2 1
 A B C D E

+3VS Place Close to Chip

UL10 LAN_MDI0+ RL1 1 2 49.9_0402_1%
1 2 PLT_RST# 29 LAN_MDI0- RL2 1 2 49.9_0402_1%
@RL4
@ RL4 4.7K_0402_5% +1.8_VDD/LX TWSI_CLK LAN_MDI1+ RL3 49.9_0402_1%
1 LX TWSI_DATA 30 1 2
LAN_MDI1- RL5 1 2 49.9_0402_1%
Vendor suggest +3V_LAN 2 47 LAN_ACTIVITY 1 1
VDD3V LED0

0.1U_0402_16V7K

0.1U_0402_16V7K
48 LAN_SK_LAN_LINK100#
LED1
2 1 +2.5V_VDDH/VDD17 6 VDD17 LED2 26 LAN_SK_LAN_LINK10# CL1 CL4
CL49 0.1U_0402_16V7K
1 CLKREQ_LAN#_R CLKREQ_LAN# 2 2 1
+2.5V_VDDH 5 VDD25V CLKREQn 27 2 1 CLKREQ_LAN# <18>
RL15 0_0402_5%
LAN_RST# 3 13 LAN_MDI0+
PCIE_WAKE# PERSTn TRXP0 LAN_MDI0-
<18,26,28> PCIE_WAKE# 4 WAKEn TRXN0 14
17 LAN_MDI1+
TRXP1 LAN_MDI1-
7 SEL_25 MHz TRXN1 18

<16> CLK_PCIE_LAN_P CLK_PCIE_LAN_P RL10 1 2 0_0402_5% CLK_PCIE_LAN_P_C 41 11 AVDDVCO1

REFCLKP AVDD_ REG AVDDVCO2
AVDDL 42
CLK_PCIE_LAN_N RL9 1 2 0_0402_5% CLK_PCIE_LAN_N_C 40
<16> CLK_PCIE_LAN_N
PCIE_NTX_LANRX_P0
REFCLKN
Atheros +1.2_DVDDL
<12> PCIE_NTX_LANRX_P0 43 RX_P +1.2_AVDDL
PCIE_NTX_LANRX_N0
AR8132 10/100 LAN DVDDL 28
<12> PCIE_NTX_LANRX_N0 44 RX_N DVDDL 32
45 1 2 1 2 AVDDVCO1
PCIE_NRX_LANTX_P0 PCIE_NRX_LANTX_P0_C DVDD_REG RL23 0_0603_5% @RL24
@ RL24 0_0603_5%
<12> PCIE_NRX_LANTX_P0 2 1 38 TX_P DVDD_REG 46 1
CL8 0.1U_0402_16V7K +1.2_AVDDL
PCIE_NRX_LANTX_N0 2 1 PCIE_NRX_LANTX_N0_C 37 8 Closed to PIN11 CL18
<12> PCIE_NRX_LANTX_N0 CL6 0.1U_0402_16V7K TX_N VDD11_ REG +3V_LAN 0.1U_0402_16V7K
AVDDL 16
2
AVDDL 22
LAN_X1
Place Close to Chip LAN_X2
9
10
XTLO AVDDL 36
39 AVDDVCO2
XTLI AVDDL

1
+2.5V_VDDH
1
<8,26,28> EC_SMB_CK2 EC_SMB_CK2 @ RL12 1 2 0_0402_5% LAN_SMB_CK_R 31 15 RL25 Closed to PIN42
EC_SMB_DA2 LAN_SMB_DA_R SMCLK VDDHO DL2 10K_0402_5% CL48
<8,26,28> EC_SMB_DA2 1 2 33 SMDATA AVDDH 19
@ RL14 0_0402_5% 25 CH751H-40PT_SOD323-2 0.1U_0402_16V7K
AVDDH 2

2
RL13 2.37K_0402_1% 20 1 2 LAN_RST#
NC <16> SB_GPIO27#
2 1 12 RBIAS NC 21 If overclocking, RL24 stuffed and RL23 removed.
34 TESTMODE NC 23 If not overclocking, RL23 suffed and RL24 removed.
NC 24 <13,16,26,28> PLT_RST# 1 2 AR8132:CL48=0.1uF.
2 49 35 DL3 2
GND NC CH751H-40PT_SOD323-2
Place Close to Chip SC1H751H010
YL1 AR8132-AL1E_QFN48_6X6 SCHOTTKY BARRIER DIODE
25MHZ_12PF_X5H025000FC1H-H
SA000036Y00 +3V_LAN
LAN_X1 1 2 LAN_X2 Closed to PIN2

1 1

10U_0805_10V4Z

1U_0402_6.3V6K

0.1U_0402_16V7K
1 1 1
CL16 CL17

CL12

CL13

CL14
15P_0402_50V8J 15P_0402_50V8J
2 2
JLAN1 CONN@ 2 2 2

RL16 13 Unused
LAN_ACTIVITY 1 2 LAN_ACTIVITY_R 12 Yellow LED+
510_0402_1% 14 Yellow LED-

1
+1.2_AVDDL

100P_0402_50V8J
RL17 +1.2_DVDDL
2
5.1K_0402_5% CL36 8
@ PR4-
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1 1 1 1 1 1 7 Closed to PIN46

2
1 PR4+
1U_0402_6.3V6K
CL22

CL23

CL24

CL25

CL26

CL27

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K
RJ45_MIDI1- 6 1 1 1 1
PR2-
2 2 2 2 2 2

CL50

CL19

CL20

CL21
5 PR3-
3 3
2 2 2 2
4 PR3+
RJ45_MIDI1+ 3 PR2+
Closed to PIN8 Closed to Pin16, Pin36, Pin39,Pin22
RJ45_MIDI0- 2 Closed to Pin28, Pin32, Pin45
PR1-
GND 15
RJ45_MIDI0+ 1 PR1+ +2.5V_VDDH
GND 16

LAN_SK_LAN_LINK100# 11 Closed to PIN15

Orange LED-

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K
+1.8_VDD/LX 1 2 +2.5V_VDDH/VDD17 1 2 +AVDD_CEN +3V_LAN 1 2 +3V_LAN_LED 10 1 1 1 1
LL1 RL6 0_0603_5% RL22 510_0402_1% Green LED+
1 1 1
CL35

CL28

CL29

CL30

CL31
0.1U_0402_16V7K

1U_0402_6.3V6K
10U_0805_10V4Z

4.7UH_1008HC-472EJFS-A_5%_1008 LAN_SK_LAN_LINK10# 9 Green LED-

CL33

CL34

2 2 2 2
2 2 2 2 2
Closed to PIN40 @ CL46 CL47 FOX_JM3611A-R5A53-7F
100P_0402_50V8J 100P_0402_50V8J @
1 1 DC234004G00
Closed to transformer Closed to PIN5, PIN19, PIN25

TRL1

LAN_MDI1+ 1 16 RJ45_MIDI1+
4 LAN_MDI1- RD+ RX+ RJ45_MIDI1- RL18 75_0402_5% 4
2 RD- RX- 15
+AVDD_CEN 3 14 RJ45_CT0 1 2 +TRCT
CT CT
4 NC NC 13
5 12
6
NC
CT
NC
CT 11 RJ45_CT1 1 2 1 DELL CONFIDENTIAL/PROPRIETARY
0.1U_0402_16V7K

0.1U_0402_16V7K

LAN_MDI0+ 7 10 RJ45_MIDI0+ RL19 75_0402_5% CL45

LAN_MDI0- TD+ TX+ RJ45_MIDI0- 1000P_1206_2KV7K
1 1 8 TD- TX- 9
2 Compal Electronics, Inc.
CL38

CL40

350uH_NS0013LF PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
2 2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
SP050001210 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LAN_AR8132
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 20 of 45
A B C D E
 5 4 3 2 1

D D

+3VS +3VSIN
RB1
1 2
1 1
0_0805_5% +CARD_3V +CARD_3V
CB1 CB2
0.1U_0402_16V7K 4.7U_0603_6.3V6K
2 2 JCARD1 CONN@
2 1 +CARD_3V 3 21 +CARD_3V CB4 2 1 0.1U_0402_16V7K
CB3 0.1U_0402_16V7K XD-VCC SD-VCC +CARD_3V CB5
MS-VCC 28 2 1
SDCLK_MSD2_XD0 32 0.1U_0402_16V7K
SD5_MSD0_XD1 XD-D0 SDCLK_MSD2_XD0
10 XD-D1 7 IN 1 CONN SD_CLK 20
SDCMD_XD2 9 14 SD0_MSD7_XDCLE
SD4_MSD4_XD3 XD-D2 SD-DAT0 SD1_XDCE
8 XD-D3 SD-DAT1 12
SD3_MSD1_XD4 7 30 SD2_MSD5_XD5
@ SD2_MSD5_XD5 XD-D4 SD-DAT2 SD3_MSD1_XD4
6 XD-D5 SD-DAT3 29
1 2 +CRREFE MSBS_XD6 5 XD-D6 SD-DAT4 27 SD4_MSD4_XD3
CB6 100P_0402_50V8J UB11 XD7 4 23 SD5_MSD0_XD1
XD-D7 SD-DAT5 SD6_MSD6_XDWP
For EMI RB2
1 2
6.2K_0402_1%~D
1 REFE
SDCD_XDWE SD-DAT6 18
SD7_MSD3_XDALE
GPIO0 17 34 XD-WE SD-DAT7 16
<18> USB20_N8 RB6 1 2 0_0402_5% USB20_N8_R 2 DM SD6_MSD6_XDWP 33 25 SDCMD_XD2
RB7 USB20_P8_R CLK_48M SD7_MSD3_XDALE XD-WP SD-CMD SDCD_XDWE
C
<18> USB20_P8 1 2 0_0402_5% 3 DP CLK_IN 24 CLK_48M <16> 35 XD-ALE SD-CD-SW 1 C
XDCD 40
+3VSIN XD7 SDWP_MSCLK_XDRDY 39 XD-CD SDWP_MSCLK_XDRDY
+3VSIN 4 3V3_IN XD_D7 23 XD-R/B SD-WP-SW 2
+CARD_3V +CARD_3V 5 MSINS_XDRE 38
+V18CR CARD_3V3 MSBS_XD6 SD1_XDCE XD-RE
2 1 6 V18 SP14 22 37 XD-CE
CB7 1U_0402_6.3V6K 21 SD2_MSD5_XD5 SD0_MSD7_XDCLE 36 26 SDWP_MSCLK_XDRDY
XDCD SP13 SD3_MSD1_XD4 XD-CLE MS-SCLK SD5_MSD0_XD1
7 XD_CD# SP12 20 MS-DATA0 17
19 SD4_MSD4_XD3 11 15 SD3_MSD1_XD4
SDWP_MSCLK_XDRDY SP11 SDCMD_XD2 7IN1 GND MS-DATA1 SDCLK_MSD2_XD0
8 SP1 SP10 18 31 7IN1 GND MS-DATA2 19
MSINS_XDRE 9 16 SD5_MSD0_XD1 24 SD7_MSD3_XDALE
SD1_XDCE SP2 SP9 SDCLK_MSD2_XD0 MS-DATA3 MSINS_XDRE
10 SP3 SP8 15 MS-INS 22

EPAD
SD0_MSD7_XDCLE 11 14 SD6_MSD6_XDWP 13 MSBS_XD6
SD7_MSD3_XDALE SP4 SP7 SDCD_XDWE MS-BS
12 SP5 SP6 13 41 7IN1 GND
42 7IN1 GND
RTS5138-GR_QFN24_4X4
25

TAITW_R015-B10-LM_NR

SP07000GW00

USB20_N8_R

USB20_P8_R

1 1
AMD@ AMD@
CB10 CB11 CLK_48M Place close to JCARD1 for EMI
0.1U_0402_16V7K 0.1U_0402_16V7K
B 2 2 SDCLK_MSD2_XD0 SDWP_MSCLK_XDRDY B

1
@

1
Place close to UB11 for AMD RB8 @ RB4 @ RB5
22_0402_5%~D 10_0402_5% 10_0402_5%

2
@ 1 1 1
CB12 @ CB8 @ CB9
10P_0402_50V8J~D 22P_0402_50V8J 22P_0402_50V8J
2 2 2

Place closed to UB11

(For RF request)

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Card Reader RTS5138
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 21 of 45
5 4 3 2 1
 5 4 3 2 1

HDMI_TXD2P
<12> HDMI_TXD2P
HDMI_TXD2N +5VS
<12> HDMI_TXD2N
D HDMI_TXD1P D
<12> HDMI_TXD1P
+3VS

1
HDMI_TXD1N
<12> HDMI_TXD1N
@ RV53 RV2 2 1 715_0402_1% HDMI_OUT_CLK-_CONN
HDMI_TXD0P
<12> HDMI_TXD0P
0_0402_5% RV4 2 1 715_0402_1% HDMI_OUT_CLK+_CONN
HDMI_TXD0N
<12> HDMI_TXD0N

2
RV1 RV6 2 1 715_0402_1% HDMI_OUT_D0-_CONN

1
HDMI_CLKP C 91K_0402_5%~D D
<12> HDMI_CLKP
2 1 2 HDMI_HPD_SINK HDMI_HPD_SINK 1 2 2 QV2 RV7 2 1 715_0402_1% HDMI_OUT_D0+_CONN
HDMI_CLKN B RV54 0_0402_5% G SSM3K7002FU_SC70-3
<12> HDMI_CLKN E QV1 S RV8 2 1 715_0402_1% HDMI_OUT_D1-_CONN

3
1
MMBT3904_SOT23-3~D

1
RV9 RV10 2 1 715_0402_1% HDMI_OUT_D1+_CONN
<13> HDMI_HPD
RV3 100K_0402_5%
200K_0402_5% RV11 2 1 715_0402_1% HDMI_OUT_D2-_CONN

2
RV5 @ RV12 2 1 715_0402_1% HDMI_OUT_D2+_CONN

2
2.7K_0402_5%~D
PLACE PULL DOWN RESISTORS CLOSE TO
DIFFERENTIAL PAIRS CONNECTED TO SOLID

2
GROUND FLOOD WHICH IS CONTROLLED
BY THE FET
AVOID STUBS TO ALL DIFFERENTIAL TRACES

C C

+5VS

+3VS +5VS

@
1

1
@ PJP61

2
RV13
QV3A PAD-OPEN 43x79 FV1
2N7002DW-7-F_SOT363-6~D
4.7K_0402_5% Place close JHDMI1 2A_8VDC_SMD1812P200TF
2

1
1 6 HDMI_SCL_SINK @RV14 1
@RV14 2 0_0402_5%
<13> HDMICLK_UMA
CV9
HDMI_CLKP 1 LV1 2 HDMI_OUT_CLK+_CONN 1U_0402_6.3V6K JHDMI1 CONN@
1 2 +5VS_HDMI TV1
1 2 18 +5V
WCM-2012-900T_4P HDMI_SDA_SINK 16 13
HDMI_CLKN HDMI_OUT_CLK-_CONN HDMI_SCL_SINK SDA CEC PAD
1 2 4 4 3 3 15 SCL Reserved 14
RV16 0_0402_5% HDMI_HPD_SINK 19 HP_DET
1 2 GND 2
@ RV15 0_0402_5% HDMI_OUT_CLK-_CONN 12 5
HDMI_OUT_CLK+_CONN CK- GND
10 CK+ GND 8
@RV17
@ RV171 20_0402_5% HDMI_OUT_D0-_CONN 9 11
HDMI_OUT_D0+_CONN D0- GND
7 D0+ GND 20
B +3VS +5VS HDMI_TXD2P 1 LV2 2 HDMI_OUT_D2+_CONN HDMI_OUT_D1-_CONN 6 21 B
1 2 HDMI_OUT_D1+_CONN D1- GND
4 D1+ GND 22
WCM-2012-900T_4P HDMI_OUT_D2-_CONN 3 23
D2- GND
1

@ HDMI_TXD2N 4 3 HDMI_OUT_D2-_CONN HDMI_OUT_D2+_CONN 1 17

RV18 4 3 D2+ DDC/CEC_GND
QV3B 4.7K_0402_5% 1 2
2N7002DW-7-F_SOT363-6~D @ RV19 0_0402_5% SUYIN_100042MR019S153ZL
5

1 2 HDMI_HPD_SINK
2

@CV10
@ CV10 1U_0603_10V6K DC232000900
4 3 HDMI_SDA_SINK @RV20
@ RV201 20_0402_5%
<13> HDMIDAT_UMA
HDMI_TXD1P 1 LV3 2 HDMI_OUT_D1+_CONN
1 2
WCM-2012-900T_4P
1 2 HDMI_TXD1N 4 3 HDMI_OUT_D1-_CONN
RV21 0_0402_5% 4 3
1 2
@ RV22 0_0402_5%

@RV23 1 0_0402_5%
2

HDMI_TXD0P 1 LV4 2 HDMI_OUT_D0+_CONN

1 2
WCM-2012-900T_4P
HDMI_TXD0N 4 3 HDMI_OUT_D0-_CONN
4 3
1 2
@ RV24 0_0402_5%

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HDMI Conn.
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 22 of 45
5 4 3 2 1
 5 4 3 2 1

+USB_SIDE_PWR
USB CONN +USB_VCCA

150U_B2_6.3VM_R35M
CI1
0.1U_0402_16V7K

75K_0402_1%
RI2

0.1U_0402_16V7K
UI12 1 2 <18> USB20_N2 USB20_N2 1

2
1 2 <18> USB20_P2 USB20_P2 1
1 10 RI3 100K_0402_5% +
<18> USB20_P1 1D+ VCC +3VALW
RI1 CI2 CI3
D 43.2K_0402_1% 2 9 PWRSHARE_OE# D
<18> USB20_N1 1D- S PWRSHARE_OE# <26> 2 2
1

1
USB_CHARGE_D+ 3 8 PWSUSB_P1 <25> 1 2
2D+ D+ RI7 0_0402_5%
USB_CHARGE_D- 4 7 PWSUSB_N1 <25>
2D- D- @ LI1 JUSB1 CONN@
2

5 GND OE# 6 1 1 2 2 4 VCC

RI4 RI5 USB20_N2 USB20_N2_R 3
49.9K_0402_1% 49.9K_0402_1% USB20_P2 USB20_P2_R D-
2 D+
4 4 3 3 1 GND
TS3USB221RSER_QFN10_2x1P5~D
1

WCM2012F2S-900T04_0805 5 GND
6 GND

3
0.1U_0402_16V7K

0.1U_0402_16V7K
S OE# Function 1 2 7 GND

PJDLC05_SOT23-3
RI6 0_0402_5% 1 1 AMD@ 8 GND
X H Disconnect CI12 CI13
L L D=1D AMD@ DL1 SUYIN_020173MR004S50TZL
2 2
H L D=2D
DC233003W00

1
(For ESD request)

RTCVREF RTCVREF RTCVREF RTCVREF @ FUSEI1

80 mils
5A_32V_0467005.NR~D
C 1 2 2.0A +USB_VCCA
C

1
1

UI13
220K_0402_5%

SDMK0340L-7-F

CI10 +5VALW PJP62 @

RI8 0.1U_0402_16V7K PAD-OPEN 43x79
80 mils 1 8 USB_OC2#
RI9 DI1 51ON# +5VALW_F1 GND OC1# USB_OC2# <18>
51ON# <31,34> 1 2 2 IN OUT1 7
10K_0402_5% 2 CLOSE TO UI16
3 EN1# OUT2 6
<26> USB_EN# 4 5
2

EN2# OC2#

10U_1206_16V4Z

0.1U_0402_16V7K
1 1
5

CI4 CI5 TPS2062ADR_SO8~D

CI11

1
D
1
P

USB_DETECT# NC QI1
2 1 2 A Y 4 2
2 2 SA00002AS0L
G 2N7002LT1G_SOT23-3
CIS LINK OK
G

2.2U_0603_10V7K~D 3 S
UI16
3

TC7SZ14FU_SSOP5~D RI11
USB_DETECT# <25>
100K_0402_5%

@FUSEI2
@ FUSEI2
2

From connector detect 1

5A_32V_0467005.NR~D
2 ESATA
2 1 1 2 USB_DET#_DELAY
RI10 0_0402_5% USB_DET#_DELAY <26> +5VALW PJP63 @
DI2 JUMP_43X79
SDMK0340L-7-F 1 2 +5V_ESAUSB

UI14

10U_1206_16V4Z
B B

0.1U_0402_16V7K
1 8 USB_OC0#
Power share 1 1 +5VALW_F2 2
GND
IN
OC1#
OUT1 7
USB_OC0# <18>
3 EN1# OUT2 6
CI7 CI6 <26> USB_EN# 4 5
EN2# OC2#
2 2 TPS2062ADR_SO8~D

@FUSEI3
@ FUSEI3
5A_32V_0467005.NR~D
1 2 +USB_SIDE_PWR

+5VALW PJP64 @ UI15

PAD-OPEN 43x79 1 8 USB_OC1#
GND OC1# USB_OC1# <18>
1 2 +5VALW_F3 2 7
IN OUT1
3 EN1# OUT2 6
10U_1206_16V4Z

<26> USB_PWR_EN# 4 EN2# OC2# 5

0.1U_0402_16V7K
1 1
TPS2062ADR_SO8~D
CI8 CI9
2 2

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB/POWER Share
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 23 of 45
5 4 3 2 1
 5 4 3 2 1

D D
Place close to JCRT1 for AMD

AMD@ AMD@ AMD@

CV40 CV41 CV42

0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
CRT +3VS 1 2 1 2 1 2

Intel USE BLM15BB470SS1D (47 OHM BEAD)

2
DV1 DV2 DV3
FOOT PRINT is Different DAN217_SC59-3 DAN217_SC59-3 DAN217_SC59-3
AMD@ AMD@ AMD@

1
VGA_CRT_R RV25 1 2 0_0402_5% CRT_R_RL 1 2 CRT_R_L
<13> VGA_CRT_R
LV5 47NH_LQG15HN47NJ02D_5%

VGA_CRT_G RV26 1 2 0_0402_5% CRT_G_RL 1 2 CRT_G_L

<13> VGA_CRT_G
LV6 47NH_LQG15HN47NJ02D_5% W=40mils
VGA_CRT_B RV27 1 2 0_0402_5% CRT_B_RL 1 2 CRT_B_L
<13> VGA_CRT_B +5VS +5VS_CRT +CRT_VCC
4.7P_0402_50V8C

4.7P_0402_50V8C

4.7P_0402_50V8C
LV7 47NH_LQG15HN47NJ02D_5%
150_0402_1%
RV30

150_0402_1%
RV29

140_0402_1%~D
RV28

6P_0402_50V

6P_0402_50V

6P_0402_50V
1 1 1 1 1 1
1

CV33

CV34

CV35

CV12

CV13

CV14
1 1 1 W=40mils FV2 W=40mils

4.7P_0402_50V8C
CV15

4.7P_0402_50V8C
CV16

4.7P_0402_50V8C
CV17
C C
For EMI 2 1 1 2
3 NC 1
2 @ 2 @ 2 @ 2 @ 2 @ 2 @ DV4 5A_125V_R451005.MRL~D
2 2 2 RB491D_SC59-3~D CV11
2

1U_0603_10V6K
2

JCRT1 CONN@
AMD Check List: R=140 ohm 6
Need CIS symbol SE00000AY80 MSEN# 11
<26> MSEN#
CRT_R_L 1
change to 6P_0402 7
Need apply CIS symbol CRT_DDC_DATA_C 12
CRT_G_L 2
8 G 16
HSYNC_L 13 17
G
CRT_B_L 3
9
+3VS +3VS +3VS +CRT_VCC +CRT_VCC VSYNC_L 14
4
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

10
1

CRT_DDC_CLK_C 15
RV55

RV56

RV31

RV32

1 5

100P_0402_50V8J
CV18
SUYIN_070546FR015M21TZR
2

2
DC060004300
2
G

CV19 +CRT_VCC
VGA_DDC_DATA 3 1 CRT_DDC_DATA_C 0.1U_0402_16V7K
B <13> VGA_DDC_DATA B
S

1 2

5
1
QV4
2
G

OE#
P
SSM3K7002FU_SC70-3 VGA_CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 RV33 HSYNC_L
<13> VGA_CRT_HSYNC A Y
VGA_DDC_CLK 3 1 CRT_DDC_CLK_C 0_0603_5%
<13> VGA_DDC_CLK

G
UV18
S

74AHCT1G125GW_SOT353-5

3
D_CRT_VSYNC 1 2 RV34 VSYNC_L
QV5 0_0603_5%
SSM3K7002FU_SC70-3
+CRT_VCC 1 1

15P_0402_50V8J
CV21

15P_0402_50V8J
CV22
CV20
@ 0.1U_0402_16V7K RV35
VGA_DDC_DATA RV51 1 2 0_0603_5% CRT_DDC_DATA_C 1 2 1 2
2 2
10K_0402_5%
@
5
1

VGA_DDC_CLK RV52 1 2 0_0603_5% CRT_DDC_CLK_C

OE#
P

VGA_CRT_VSYNC 2 4
<13> VGA_CRT_VSYNC A Y
G

UV19
74AHCT1G125GW_SOT353-5
3

AMD@ AMD@

CV38 CV39
0.1U_0402_16V7K 0.1U_0402_16V7K

+3VS 1 2 1 2
3

A A
DV8 DV9
DAN217_SC59-3 DAN217_SC59-3
AMD@ AMD@
DELL CONFIDENTIAL/PROPRIETARY
1

CRT_DDC_DATA_C

CRT_DDC_CLK_C
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Place close to JCRT1 for AMD BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, VGA Conn.
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Monday, May 10, 2010 Sheet 24 of 45
5 4 3 2 1
 A B C D E

Power LED
BATT CHARGE
1 1
+5VALW
+5VALW

DO1
HT-210UD5-BP5_AMBER-WHITE BATT_LOW_LED#_D

100K_0402_5%
RO1 100K_0402_5%
White
RO3

1
1

100K_0402_5%
1 2 PWR_LED#_D 2 RO4 RO6

100K_0402_5%
RO5 300_0402_5%~D
820_0402_5% 1 +5VALW
BATT_LOW_LED#_D 3

2
2

2
RO2
Amber

3
QO1B D
5

3
G QO2B D
DMN66D0LDW-7_SOT363-6 5
S G

4
6
QO1A D
DMN66D0LDW-7_SOT363-6
<26> PWR_LED# 2 S

4
6
G QO2A D
DMN66D0LDW-7_SOT363-6 <26> BATT_LOW_LED# 2
1 S G
DMN66D0LDW-7_SOT363-6
S

1
2 2

JWTB1 CONN@
1 1
41 G1 2 2
42 G2 3 3
43 G3 4 4
44 G4 5 5
45 G5 6 6
46 G6 7 7 PWSUSB_N1 <23>
8 8 PWSUSB_P1 <23>
HD LED 9 9
10 10 USB20_N0 <18>
11 11 USB20_P0 <18>
12 12
13 13 DMIC_CLK <27>
+5VS 14 14 DMIC_DATA <27>
15 15
3 3

16 16 HDA_BITCLK_SSIC <18>
17 17 HDA_SYNC <18>
DO3 18 18 SB_SPKR <18>
19 19
100K_0402_5%

RO9 HDA_RST# <18>

20 20 HDA_SDIN0 <18>
1

1 2 SATA_LED#_D 1 2 +5VS 21 21 HDA_SDOUT <18>

22 22 BEEP# <26>
820_0402_5% HT-121BP_WHITE 23 23
24 24 EC_EAPD <26>
25 25 EC_MUTE# <26>
2

26 26
RO8

27 27 +5V_ESAUSB
3

QO3B D
28 28
5 29 29
G
30 30
DMN66D0LDW-7_SOT363-6
31 31 +USB_SIDE_PWR
S
32 32
4
6

QO3A D
33 33
<17> SATA_ACT#_R 2 34 34
G
35 35 +5VS
DMN66D0LDW-7_SOT363-6
36 36
S
37 37
1

38 38 +3VS
39 39
40 40 USB_DETECT# <23>
STARC_107K40-000001-G2

SP01000XE00

4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, WTB Conn/LED
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 25 of 45
A B C D E
 A B C D E

LE1
+3VALW
Board ID
+3VALW +3VALW
+EC_AVCC FBMA-L11-160808-601LMT_2P

2
CLK_PCI_EC 2 1
RE1
1 1 1 1 1 1 100K_0402_5% Ra

0.1U_0402_16V7K
CE2

0.1U_0402_16V7K
CE3

0.1U_0402_16V7K
CE4
CE1
4.7U_0603_6.3V6K
CE5 CE6
@ RE2

1
10_0402_5% 0.1U_0402_16V7K 4.7U_0603_6.3V6K AD_BID
2 2 2 2 2 2

1
0_0402_5%

33K_0402_5%

18K_0402_5%

8.2K_0402_5%
ECAGND 2 1

RE4

RE5

RE6

RE7
1 RE3 0_0402_5%
1 +3VALW 1
@ CE7 @ @ @ @
Rb

111
125
22P_0402_50V8J

22
33
96

67

2
UE20
1

9
2

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
47K_0402_5%
RE8
BOARD ID Table
2

GATEA20 1 21 DBC_ENABLE DBC_ENABLE <27>

EC_RST# <18> GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP#
2 23
<18> KB_RST#
<16> IRQ_SERIRQ
IRQ_SERIRQ 3
KBRST#/GPIO01
SERIRQ#
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12 26 USB_PWR_EN#
BEEP#
USB_PWR_EN#
<25>
<23>
ID BOARD ID Ra Rb Vab
LPC_LFRAME# ACOFF
2
<16,28> LPC_LFRAME#
<16,28> LPC_LAD3 LPC_LAD3
4
5
LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF <34,35> 0 0.1(X00) NC 0 0V
CE8 LPC_LAD2 LAD3
<16,28> LPC_LAD2 7 LAD2 PWM Output 1 0.2(X01) 100K 8.2K 0.25V
0.1U_0402_16V7K <16,28> LPC_LAD1 LPC_LAD1 8 63 BATT_TEMP
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <33>
LPC_LAD0 BATT_OVP
1 <16,28> LPC_LAD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP <33> 2 0.3(X02) 100K 18K 0.50V
ADP_I/AD2/GPIO3A 65 ADP_I <35>
CLK_PCI_EC AD Input AD_BID
12 66
3 1.0(A00) 100K NC 3.3V
<16,17> CLK_PCI_EC
<13,16,20,28> PLT_RST# PLT_RST#
EC_RST#
13
37
PCICLK
PCIRST#/GPIO05
ECRST#
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
75
76
MSEN#
VGATE
MSEN#
VGATE
<24>
<8,42>
*
SIO_EXT_SCI# 20
<18> SIO_EXT_SCI# EC_CLKRUN#_R SCI#/GPIO0E
38 CLKRUN#/GPIO1D
EC_CLKRUN# EC_CLKRUN#_R +5VS
<16> EC_CLKRUN# 1 2 DAC_BRIG/DA0/GPIO3C 68
RE33 0_0402_5% 70 EN_DFAN1 EN_DFAN1 <29>
EN_DFAN1/DA1/GPIO3D IREF
DA Output IREF/DA2/GPIO3E 71 IREF <35>
@ KSI0 55 72 CHGVADJ CHGVADJ <35>
KSI1 KSI0/GPIO30 DA3/GPIO3F
56 KSI1/GPIO31
KSI2 57 KSI2/GPIO32

1
KSI3 58 83 EC_MUTE# EC_MUTE# <25>
KSI4 KSI3/GPIO33 PSCLK1/GPIO4A USB_EN# RE9 RE10
59 KSI4/GPIO34 PSDAT1/GPIO4B 84 USB_EN# <23>
PLT_RST# KSI5 60 85 4.7K_0402_5% 4.7K_0402_5%
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C USB_DET#_DELAY
2
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 USB_DET#_DELAY <23> 2
KSI7 62 87 TP_CLK

2
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA
2 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88
@ CE25 KSO1 40
KSO2 KSO1/GPIO21 TP_CLK
0.1U_0402_16V7K 41 KSO2/GPIO22 TP_CLK <31>
KSO3 42 97 BT_OFF# BT_OFF# <28> TP_DATA
+3VALW 1 KSO3/GPIO23 SDICS#/GPXOA00 TP_DATA <31>
KSO4 43 98 EN_WOL# EN_WOL# <17,30>
KSO5 KSO4/GPIO24 SDICLK/GPXOA01
SIO_EXT_SMI# KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
1 2 45 109
@ RE11
1
8.2K_0402_5%
2 SIO_EXT_SCI#
Place close to EC
(For ESD request)
KSO7
KSO8
46
47
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
SPI Device Interface
SDIDI/GPXID0 LID_SW# <31>
KEYBOARD CONN.
@ RE12 8.2K_0402_5% KSO9 48 119 FRD#SPI_SO
KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO <31> ACES_88514-2401
KSO10 49 120 FWR#SPI_SI FWR#SPI_SI <31> ACIN
KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK
50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 SPI_CLK <31> 26 GND2

0.1U_0402_16V7K
KSO12 51 128 FSEL#SPICS# FSEL#SPICS# <31> 25
KSO13 KSO12/GPIO2C SPICS# GND1
52 KSO13/GPIO2D 1
KSO14 53 CE9 KSO15 24
KSO15 KSO14/GPIO2E WLAN_RADIO_OFF# KSO10 24
54 KSO15/GPIO2F CIR_RX/GPIO40 73 WLAN_RADIO_OFF# <28> 23 23
81 74 PS_ID KSO11 22
+3VALW KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG PS_ID <34> 2 KSO14 22
82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89 FSTCHG <35> 21 21
90 EN_INVPWR EN_INVPWR <27> KSO13 20
PCIE_WAKE# BATT_CHGI_LED#/GPIO52 PWRSHARE_OE# KSO12 20
1 2 CAPS_LED#/GPIO53 91 PWRSHARE_OE# <23> 19 19
RE13 10K_0402_5% <33> EC_SMB_CK1 EC_SMB_CK1 77 GPIO BATT_LOW_LED#/GPIO54 92 BATT_LOW_LED# BATT_LOW_LED# <25> KSO3 18
EC_MUTE# EC_SMB_DA1 SCL1/GPIO44 LCD_TEST KSO6 18
1 2 <33> EC_SMB_DA1 78 SDA1/GPIO45 SUSP_LED#/GPIO55 93 LCD_TEST <27> 17 17
@ RE14 10K_0402_5% <8,20,28> EC_SMB_CK2 EC_SMB_CK2 79 SM Bus 95 SYSON SYSON <39> KSO8 16
LID_SW# EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 VR_ON KSO7 16
1 2 <8,20,28> EC_SMB_DA2 80 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 121 VR_ON <42> 15 15
RE15 10K_0402_5% 127 ACIN_EC 2 1 ACIN KSO4 14
KSO1 AC_IN/GPIO59 DE2 CH751H-40PT_SOD323-2 ACIN <18,34> KSO2 14
1 2 13 13
RE16 47K_0402_5% KSI0 12
KSO2 SIO_SLP_S3# EC_RSMRST# KSO1 12
1 2 <18> SIO_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# <18> 11 11
RE17 47K_0402_5% <18> SIO_SLP_S5# SIO_SLP_S5# 14 101 EC_LID_OUT# EC_LID_OUT# <18> KSO5 10
MSEN# SIO_EXT_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON KSI3 10
1 2 <18> SIO_EXT_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON <31> 9 9
RE31 10K_0402_5% SMB_ALERT# 16 103 SB_RI# EC Team request KSI2 8
3 <8,13,18> SMB_ALERT# LID_SW#/GPIO0A EC_SWI#/GPXO06 SB_RI# <18> 8 3
BT_RADIO_OFF# 17 104 SB_PWRGD_EC KSO0 7
ACIN_EC <28> BT_RADIO_OFF# CE_ENABLE SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# KSI5 7
1 2 <27> CE_ENABLE 18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# <27> 6 6
RE32 10K_0402_5% 19 GPIO 106 WWAN_RADIO_OFF# WWAN_RADIO_OFF# <28> KSI4 5
INVT_PWM EC_PME#/GPIO0D WL_OFF#/GPXO09 LCD_VCC_TEST_EN KSO9 5
<27> INVT_PWM 25 EC_THERM#/GPIO11 GPXO10 107 LCD_VCC_TEST_EN <27> 4 4
<29> FAN_SPEED1 FAN_SPEED1 28 108 PSID_DISABLE# PSID_DISABLE# <34> KSI6 3
CAM_ON/OFF# FAN_SPEED1/FANFB1/GPIO14 GPXO11 KSI7 3
<27> CAM_ON/OFF# 29 FANFB2/GPIO15 2 2
EC_TX 30 KSI1 1
+5VALW <28> EC_TX EC_RX EC_TX/GPIO16 1
<28> EC_RX 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110
ON/OFF_EC# 32 112 EC_ENBKL EC_ENBKL <27>
EC_SMB_CK1 <31> ON/OFF_EC# PWR_LED# ON_OFF/GPIO18 ENBKL/GPXID2 EC_EAPD JKB1 CONN@
1 2 <25> PWR_LED# 34 PWR_LED#/GPIO19 GPXID3 114 EC_EAPD <25>
RE18 4.7K_0402_5% <28> BT_DET# BT_DET# 36 GPI 115 DC020906103
EC_SMB_DA1 NUMLED#/GPIO1A GPXID4 SUSP#
1 2 GPXID5 116 SUSP# <30,35,40,41,43>
RE19 4.7K_0402_5% 117 PBTN_OUT# PBTN_OUT# <18>
GPXID6 PCIE_WAKE# KSI1 KSI0
GPXID7 118 PCIE_WAKE# <18,20,28>
+3VALW XCLKI 122
@ XCLKO XCLK1 V18R
1 2 123 XCLK0 V18R 124 1 1
1 2 EC_SMB_CK2
AGND

RE21 @ 2.2K_0402_5% @ RE20 20M_0603_5% 1 1 @ CE20 @ CE21

GND
GND
GND
GND
GND

1 2 EC_SMB_DA2 CE10 CE11 22P_0402_50V8J 22P_0402_50V8J

RE22 2.2K_0402_5% 32.768KHZ_12.5P_1TJE125DP1A000M 2 2
1 2 KB926QFD3_LQFP128_14X14 0.1U_0402_16V7K 4.7U_0603_6.3V6K
11
24
35
94
113

69

+3VS 2 2 KSO7 KSO8

1 1
1 1
ECAGND

1 2 EC_SMB_CK2 CE12 XE1 CE13

RE23 2.2K_0402_5% 27P_0402_50V8J 27P_0402_50V8J @ CE22 @ CE23
EC_SMB_DA2 2 2 22P_0402_50V8J 22P_0402_50V8J
1 2
RE24 2.2K_0402_5% RE25 2 2
0_0402_5%
SB_PWRGD_EC 1 2 SB_PWRGD <8,13,18> KSO15
E0 version: SA00001J5A0 1 1
CE14 @ CE24
4 @ 0.47U_0603_16V7K 22P_0402_50V8J 4
2 2 For EMI
+3VS

1
RE26
2 BT_RADIO_OFF#
4.7K_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
BT_DET#
1
RE27
2
10K_0402_5% Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ENE-KB926/KB Conn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 26 of 45
A B C D E
 A B C D E

+5VALW INVPWR_B+
@ LV8
W=60mils FBMA-L11-201209-221LMA30T_0805

1
B+ 2 1
+LCDVDD +5VALW +3VS B+ INVPWR_B+
RV59 RV60
LCD POWER CIRCUIT 100K_0402_5% 820_0805_1%

1
1 1

1 2
RV36 RV37
QV6 D
100_0805_5% 47K_0402_5% SI3457BDV-T1-E3_TSOP6 QV11 2 QV12
QV8 40mil 2N7002W-7-F_SOT323-3 G
40mil

1 2

1
AO3413_SOT23-3 D 2N7002W-7-F_SOT323-3
6 S

S
INVPWR_B+

3
3
QV7 D S
EN_INVPWR
G 4 5 2
SSM3K7002FU_SC70-3 2 RV38 2 1 56K_0402_5% 2 2 G

1000P_0402_50V7K
G W=60mils 1 S

3
1

G
DV5 S 1
D
1 1

1
2 1 +LCDVDD RV39
<13> ENVDD

3
CV25
CV24 100K_0402_5% CV23
CH751H-40PT_SOD323-2 0.1U_0402_16V7K 0.1U_0603_50V4Z

1
D 2 2 2

2
4.7U_0805_10V4Z

0.1U_0402_16V7K
2
G QV9 1 1 PWR_SRC_ON QV10 Discharg Circuit
S SSM3K7002FU_SC70-3 2N7002W-7-F_SOT323-3

CV27

CV28

S
1 2 1 3

1
DV10 RV42 100K_0402_5%
LCD_VCC_TEST_EN 2 RV41 2 2
<26> LCD_VCC_TEST_EN 1
10K_0402_5%

G
2
CH751H-40PT_SOD323-2 +3VS
<26> EN_INVPWR
2

1 2
RV61 0_0402_5% 1
@ CV26

2 0.1U_0402_16V7K 2
2
Closed to JLVDS1

JLVDS1 CONN@
+3VS +3VS
@ USB20_P9_R
W=60mils 1 1
+LCDVDD 2 2 G1 41
CV29 2 1 0.1U_0402_16V7K RO10 1 2 0_0402_5% 3 42
USB20_N9_R 3 G2
+3VS 4 4 G3 43
1

1 2 RV43 BKOFF# <26> LCD_TEST 5 44

5 G4

2
0.1U_0402_16V7K

0.1U_0402_16V7K
4.7K_0402_5% @ LO1 <13> LDDC_CLK_MCH 6 45
6 G5

PJDLC05_SOT23-3
RV44 <18> USB20_N9 USB20_N9 1 1 2 USB20_N9_R 1 1 7 46
2 <13> LDDC_DATA_MCH 7 G6
4.7K_0402_5% <13> LVDS_A0- 8
DV6 CO6 CO7 8
<13> LVDS_A0+ 9
2

BKOFF# BL_OFF# USB20_P9 USB20_P9_R DO4 9

<26> BKOFF# 1 2 <18> USB20_P9 4 4 3 3 10 10
AMD@ 2 AMD@ 2 <13> LVDS_A1- 11 11
CH751H-40PT_SOD323-2 WCM2012F2S-900T04_0805 AMD@ <13> LVDS_A1+ 12 12
13 13
EC_ENBKL 1 2 <13> LVDS_A2- 14

1
<26> EC_ENBKL RO11 0_0402_5% 14
<13> LVDS_A2+ 15 15
16 16
@ DV7 <13> LVDS_ACLK- 17 17
<13> ENBKL
RV45
1 2
0_0402_5%
1 2
@ RO12
Place close to JLVDS1 for AMD <13> LVDS_ACLK+ 18 18
CH751H-40PT_SOD323-2 +5VS_CAM
W=20mils 19 19
3 +5VS 1 2 +5VS_CAM 20 20 3
0_0603_5% USB20_P9_R 21
USB20_N9_R 21
22 22
+5VS_CAM 23 23
LO2 1 2 DMIC_CLK_R 24
<25> DMIC_CLK 24
QO4 FBMA-L10-160808-301LMT_2P 25
+5VS SI2301BDS-T1-E3_SOT23-3 +5VS_CAM 25
<25> DMIC_DATA 26 26
W=20mils 1 27 27
S

CO3
D
3 1 1 28 28
1 CO2 29
100P_0402_50V8J 29
30 30
1

+3VS CO4 100P_0402_50V8J 2

G

1 31
2

@ CO5 0.1U_0402_16V7K 2 31
32 32
RV47 1 2
2 0_0402_5% RO13 @ 33 33
2

0.1U_0402_16V7K <26> CE_ENABLE CE_ENABLE 1 2 CE_ENABLE_R 34

+3VS RV48 2 100K_0402_5% RV57 0_0402_5% LCD_PWM 34
35
2

BL_OFF# 35
10K_0402_5% 1 2 BL_OFF#_R 36 36
@ <26> DBC_ENABLE DBC_ENABLE 1 2 DBC_ENABLE_R RV46 0_0402_5% 37 37
5

UO21 1 2 CAM_ON/OFF RV58 0_0402_5% 38

1

38

0.1U_0603_50V4Z
1 39
P

<26> INVT_PWM INA INVPWR_B+ 39

4 LCD_PWM RV49 1K_0402_5% 1 1 40
O 40
1

D
<13> NB_LCD_PWM 2 INB 1 CE_ENABLE Pin.34
G

CV32 <26> CAM_ON/OFF# 2 QO5 CV30 CV31 STARC_107K40-000001-G2

74AHC1G32GW_SOT353-5~D G 2N7002_SOT23-3 DBC_ENABLE Pin.37 68P_0402_50V8J
3

100P_0402_50V8J 2 2
S SP01000XE00
3

4 1 2 4
RV50 0_0402_5%
@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LVDS/Cam Conn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 27 of 45
A B C D E
 A B C D E

+1.5VS

SIM Card

WWAN@ CM1

WWAN@ CM2

WWAN@ CM3

WWAN@ CM4
0.1U_0402_16V7K
0.01U_0402_25V7K

4.7U_0805_10V4Z

0.047U_0402_16V4Z
1 1 1 1
WWAN PCIE MiniCard UM22 @

2 2 2 2 UIM_RESET UIM_VPP
1 6
+1.5VS
2 5 +UIM_PWR
JWWAN1 CONN@
PCIE_WAKE# 1 2 +3VS
<18,20,26> PCIE_WAKE# 1 2

CM5

CM6

CM7

CM8

WWAN@ CM9
0.01U_0402_25V7K
0.047U_0402_16V4Z
3 4 1 UIM_CLK 3 4 UIM_DATA
3 4
110 mils

0.1U_0402_16V7K

330U_D2E_6.3VM_R25M
4.7U_0805_10V4Z
5 5 6 6 1 1 1

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
1 7 8 + 1
<18> CLKREQ_WWAN# 7 8 +UIM_PWR +3VS

CM10

CM11

CM12

CM13
9 10 UIM_DATA 1 1 1 1
9 10

WWAN@

WWAN@

WWAN@

WWAN@
<16> CLK_PCIE_WWAN_N 11 12 UIM_CLK SRV05-4.TCT_SOT23-6~D
11 12 UIM_RESET 2 2 2 2
<16> CLK_PCIE_WWAN_P 13 13 14 14
15 16 UIM_VPP WWAN@ @ @ @ @
15 16

1
2 2 2 2
RM14
17 18 WWAN@ DM1 10K_0402_5%
17 18 WWAN_RADIO_OFF# CH751H-40PT_SOD323-2
19 19 20 20 WWAN_RADIO_OFF# <26>
21 22 WWAN_RST#

2
21 22 WWAN_RST# +UIM_PWR
<12> PCIE_NRX_WWANTX_N2 23 23 24 24 <16> SB_GPIO2# 1 2
<12> PCIE_NRX_WWANTX_P2 25 25 26 26

1U_0603_10V6K
27 28 @
27 28 WWAN_SMB_CK_R 1
29 29 30 30 2 0_0402_5% RM1 EC_SMB_CK2 <8,20,26> <13,16,20,26> PLT_RST# 1 2 1

CM14

WWAN@
<12> PCIE_NTX_WWANRX_N2 31 32 WWAN_SMB_DA_R 1 2 0_0402_5% RM2 EC_SMB_DA2 <8,20,26>
31 32 @ WWAN@ DM2
<12> PCIE_NTX_WWANRX_P2 33 33 34 34
35 36 USB20_N5_R CH751H-40PT_SOD323-2
35 36 USB20_P5_R 2
37 37 38 38
+3VS 39 39 40 40 SC1H751H010
SCHOTTKY BARRIER DIODE
41 41 42 42
43 44 JSIM1 CONN@
43 44

0.1U_0402_16V7K

0.1U_0402_16V7K
45 45 46 46 4 GND VCC 1
47 48 1 1 UIM_VPP 5 2 UIM_RESET
47 48 UIM_DATA VPP RST UIM_CLK
49 49 50 50 6 I/O CLK 3
51 52 CM23 CM24 WWAN@ 7
51 52 RM3 DET
1 2 0_0402_5%
AMD@ 2 AMD@ 2
53 GND1 GND2 54
55 56 @ LM1
NC NC USB20_P5 USB20_P5_R
check layout symbol <18> USB20_P5 1 1 2 2 GND 8
GND 9
BELLW_80052-1021
USB20_N5 4 3 USB20_N5_R
2 <18> USB20_N5 4 3 2
DC040006S00 Place close to JWWAN1 for AMD WCM2012F2S-900T04_0805

1 2 TAITW_PMPAT6-06GLBS7N14N0
RM4 0_0402_5%
WWAN@ SP07000FV00
WLAN/WIMAX PCIE Mini Card
Place close to JBT1 for AMD
Primary Power Aux Power
+3V_WLAN
40 mils +1.5VS
20 mils PWR
Rail
Voltage
Tolerance
0.01U_0402_25V7K

0.1U_0402_16V7K

4.7U_0805_10V4Z

0.047U_0402_16V4Z
+3VS 2 1 Peak Normal Normal USB20_P6_R
RM5 0_1206_5% 1 1 1 1 1 1 1 1
0.1U_0402_16V7K
0.01U_0402_25V7K

4.7U_0805_10V4Z
0.047U_0402_16V4Z

USB20_N6_R
+3.3V +-9% 1000 750
2 2 2 2 2 2 2 2
CM19

CM20

CM21

CM22

250 (Wake enable)

CM15

CM16

CM17

CM18

0.1U_0402_16V7K

0.1U_0402_16V7K
+3.3Vaux +-9% 330 250 5 (Not wake enable) AMD@
AMD@ 1 1

+1.5V +-5% 500 375 NA CO8 CO9

@ 2 2
<16> CLK_DEBUG_PORT_1 RM19 1 2 0_0402_5% BT_DISABLEB#

BT_RADIO_OFF# RM20 1 2 0_0402_5%

+3V_WLAN
+1.5VS RO14 1 2 0_0402_5%
3 @ JWLAN1 CONN@ 3
BT_ACTIVE RM16 1 2 0_0402_5% PCIE_WAKE# 1 2 @ LO3
@ COEX2_WLAN_ACTIVE 3
1
3
2
4 4 For Compal LPC debug card <18> USB20_P6
USB20_P6 1 1 2 2 USB20_P6_R
BT_RADIO_OFF# RM17 1 2 0_0402_5% BT_ACTIVE_OFF 5 6
CLKREQ_WLAN# 5 6 LPC_LFRAME#
<18> CLKREQ_WLAN# 7 7 8 8 LPC_LFRAME# <16,26>
9 10 LPC_LAD3 USB20_N6 4 3 USB20_N6_R
9 10 LPC_LAD3 <16,26> <18> USB20_N6 4 3
<16> CLK_PCIE_WLAN_N 11 12 LPC_LAD2
11 12 LPC_LAD2 <16,26>
<16> CLK_PCIE_WLAN_P 13 14 LPC_LAD1 WCM2012F2S-900T04_0805
13 14 LPC_LAD1 <16,26>
15 16 LPC_LAD0
15 16 LPC_LAD0 <16,26>
PLT_RST# 1 2 17 18 1 2
BT_DISABLEB# RM6 0_0402_5% 17 18 WLAN_RADIO_OFF# RO15 0_0402_5%
19 19 20 20 WLAN_RADIO_OFF# <26>
21 22 WLAN_RST#
PCIE_NRX_WLANTX_N1 21 22
<12> PCIE_NRX_WLANTX_N1 PCIE_NRX_WLANTX_P1
23
25
23 24 24
26
Bluetooth
<12> PCIE_NRX_WLANTX_P1 25 26 0_0402_5% @ JBT1 CONN@
27 27 28 28
29 30 WLAN_SMB_CLK_R 1 2 RM7 BT_DET# 1 BT_ACTIVE
PCIE_NTX_WLANRX_N1 29 30 WLAN_SMB_DAT_R
EC_SMB_CK2 <8,20,26> <26> BT_DET#
COEX2_WLAN_ACTIVE 1 2 2
<12> PCIE_NTX_WLANRX_N1 31 31 32 32 1 2 RM8 EC_SMB_DA2 <8,20,26> 3 3 4 4 +3VS
PCIE_NTX_WLANRX_P1 33 34 0_0402_5% @ BT_OFF# 5 USB20_P6_R
<12> PCIE_NTX_WLANRX_P1 33 34 USB20_N4_R <26> BT_OFF# BT_RADIO_OFF# 5 6 6 USB20_N6_R
35 35 36 36 <26> BT_RADIO_OFF# 7 7 8 8
37 38 USB20_P4_R 9
37 38 +3V_WLAN 9 10 10
+3V_WLAN 39 39 40 40 11 11 12 12
0.1U_0402_16V7K

41 41 42 42 13 13 14 14
0.1U_0402_16V7K

@ 43 44
43 44

1
BT_RADIO_OFF# RM18 1 2 0_0402_5% BT_DISABLE 45 46 1 1 15 16
45 46 AMD@ AMD@ RM15 GNDGND
47 47 48 48
<26> EC_TX RM10 1 2 0_0402_5% 49 50 CM25 CM26 DM3 2K_0402_1%~D
RM11 1 0_0402_5% 49 50 CH751H-40PT_SOD323-2
<26> EC_RX 2 51 51 52 52
2 2 TYCO_3-2041112-4~D

2
53 54 1 2 WLAN_RST# CIS LINK OK
GND1 GND2 <16> SB_GPIO26#
1 2 RM9 100K_0402_5% SP01000WS0L
ACES_88910-5204 1 2
4 SP01000MO0L <13,16,20,26> PLT_RST# 4
CIS LINK OK DM4
SP01000I100 Place close to JWLAN1 for AMD CH751H-40PT_SOD323-2
RM12 1 2 0_0402_5% DELL CONFIDENTIAL/PROPRIETARY
SC1H751H010
SCHOTTKY BARRIER DIODE
@ LM2
USB20_P4 USB20_P4_R
<18> USB20_P4 1 1 2 2 Compal Electronics, Inc.
Title
USB20_N4 USB20_N4_R PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
<18> USB20_N4 4 4 3 3
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT WLAN/WWAN/BT
WCM2012F2S-900T04_0805 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
1 2 PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6132P
RM13 0_0402_5% Date: Tuesday, May 04, 2010 Sheet 28 of 45

A B C D E
 5 4 3 2 1

+5VS
Pleace near HDD CONN (JHDD1)

HDD Connector

1000P_0402_50V7K
0.1U_0402_16V7K

0.1U_0402_16V7K
10U_0805_10V4Z
1 1 1 1
CONN@ JHDD1 Near CONN side. CH1 CH2 CH3 CH4
2 2 2 2
D
GND 1 D
A+ 2 SATA_STX_DRX_P0 <17>
A- 3 SATA_STX_DRX_N0 <17>
GND 4
5 SATA_SRX_DTX_N0_R CH5 1 2 0.01U_0402_16V7K SATA_SRX_DTX_N0 <17>
B- SATA_SRX_DTX_P0_R CH6
B+ 6 1 2 0.01U_0402_16V7K SATA_SRX_DTX_P0 <17>
GND 7

V33 8
9 +3VSHDD
V33
V33 10
11 +3VS +3VSHDD
GND
GND 12
13 PJP65
GND +5VS JUMP_43X118
V5 14
V5 15 1 1 2 2
V5 16
40 mils
GND 17
18
Open
DAS/DSS
GND 19

10U_0805_10V4Z

0.1U_0402_16V7K
23 GND V12 20

0.1U_0402_16V7K
24 GND V12 21
V12 22 1 1 1

@CH7
@

@CH8
@

@CH9
@
CH7

CH8

CH9
SUYIN_127043FR022G196ZR
2 2 2
DC010005A00
C C

FAN Control circuit

+FAN_POWER
40mil
+3VS
1000P_0402_50V7K

+FAN_POWER
10U_1206_16V4Z

1 1 CONN@
B CF1 CF2 B

1
JFAN1
2 2 +5VS RF1
40mil
1 1
CF3 10U_1206_16V4Z 10K_0402_5% 2 2
1 2 3 3

2
<26> FAN_SPEED1 4 GND
UF23 5 GND
1 VEN GND 8
2 VIN GND 7 1 ACES_85204-0300N
3 VO GND 6
<26> EN_DFAN1 EN_DFAN1 4 5 CF4
VSET GND 0.01U_0402_16V7K
2 SP02000JR00
RT9027BPS SO 8P
CIS SYMBOL OK

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, FAN/HDD
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 29 of 45
5 4 3 2 1
 5 4 3 2 1

DC/DC Interface
+5VRUN Source
RTCVREF +COINCELL
B+_BIAS +5VALW QZ3
NTMS4107NR2G_SO8~D +5VS
+COINCELL +RTC_CELL 8 1
SB00000N90L

1
7 2
@ RZ3 6 3
RZ28

1
(NTMS4920NR2G) 100K_0402_5% 5 1

CZ2
10U_0805_10V4Z
1 2 RZ6
20K_0402_5%

4
0_0402_5% 5V_RUN_ENABLE

2
D 2 D

2
DZ3
BAT54CW_SOT323-3~D

1
D

390K_0402_5%
QZ5

1
SUSP 2 SSM3K7002FU_SC70-3 1
+RTC_CELL G CZ4

1
S RZ29

3
@ 0.1U_0402_25V6
2

2
1
CZ24
1U_0603_10V6K +5VALW
2

+3.3V_RUN Source

1
RZ7 +3VALW QZ8 +3VS
100K_0402_5% B+_BIAS NTMS4107NR2G_SO8~D
8 1
7 2

1
6 3 1 @

10U_0805_10V4Z
SUSP SUSP <38> RZ10 5 RZ12

CZ5
100K_0402_5% 20K_0402_5%
+3VALW to +3LAN Transfer

4
2

SSM3K7002FU_SC70-3

2
1
D

QZ6
2 3.3V_RUN_ENABLE
<26,35,40,41,43> SUSP#
G

2M_0402_5%~D
S

1
D
W=40mils 1
RZ8
2
10K_0402_5% QZ10 RZ30
1
CZ8
2
C QZ11 G SSM3K7002FU_SC70-3 C
+3VALW SI3456BDV-T1-E3 1N TSOP6 S 0.01U_0402_25V7K

3
+3V_LAN 2
W=40mils

2
D

6
S
1U_0603_10V6K

5 4
2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0.1U_0402_16V7K
1 1
G
CZ11

B+_BIAS 1 1
3

CZ9

CZ10

CZ12
+1.5V_RUN Source
470K_0402_5%
1

2 @ 2
RZ13

QZ12 rDS=5.2mOHM
+1.5V +1.5VS
CZ15 B+_BIAS SI4634DY-T1-E3_SO8~D
2

EN_WOL 1 2 8 1
7 2
1

1
D 2200P_0402_50V7K 6 3 1
1

10U_0805_10V4Z
<17,26> EN_WOL# 2 QZ13 RZ15 5 RZ16

CZ18
G SSM3K7002FU_SC70-3 RZ14 100K_0402_5%

20K_0402_5%
S 1.5M_0402_5%
3

4
2

2
2

1.5V_RUN_ENABLE

2M_0402_5%~D
1
1

1
D RZ31 CZ19
2 QZ14
G SSM3K7002FU_SC70-3 0.1U_0402_25V6
B S 2 B

2
Discharg Circuit +1.1V_RUN Source
QZ15 rDS=5.2mOHM
+5VS +1.5VS +3VS +1.1VS +0.75VS B+_BIAS +1.1VALW
SI4634DY-T1-E3_SO8~D +1.1VS
8 1
1

1
@

@ @ 7 2
RZ19 RZ23 RZ24 RZ20 RZ18 RZ21 6 3

1
1K_0402_5% 1K_0402_5% 39_0402_5% 39_0402_5% 22_0603_5% 470K_0402_5% 5 1

10U_0805_10V4Z
RZ25

CZ20
20K_0402_5%
2

4
1.1V_RUN_ENABLE
+5V_RUN_CHG

+1.5V_RUN_CHG

+3.3V_RUN_CHG

+1.1V_RUN_CHG

2
+DDRVTT_CHG

2
1
D QZ16

2M_0402_5%~D
2 SSM3K7002FU_SC70-3

1
G 1
S RZ32 CZ21

3
SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

@ @ @ 0.1U_0402_25V6
1

D D D D D 2
QZ18

QZ19

QZ20

QZ21

QZ23

2
SUSP 2 SUSP 2 SUSP 2 SUSP 2 SUSP 2
G G G G G
S S S S S
3

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DC/DC (Power control)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 04, 2010 Sheet 30 of 45
5 4 3 2 1
 A B C D E

+3VALW
MB_Power On/Off SW

1
+3VALW RZ26

JPWR1 100K_0402_5%
H2 H3 H5 H6 H7 H8 H9 H19

2
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 CONN@ 1 DZ1
1 LID_SW#
2 2 LID_SW# <26> 2 ON/OFF_EC# <26>
3 ON/OFFBTN# 1
3
4 3 51ON# <23,34>

1
4
1 1
5 DAN202UT106_SC70-3
GND
GND 6
H10 H11 H12
H_3P2 H_3P2 H_3P2 1
ACES_88514-0401 CZ22

FD1 FD2 FD3 FD4 SP01000R400 0.1U_0402_25V6 QZ24

1

1
2

1000P_0402_50V7K
2N7002LT1G_SOT23-3 1

1
@ @ @ @ D CZ23 DZ2
CIS SYMBOL OK
<26> EC_ON 2

1
G

2
H13 S 2 RLZ20A_LL34

2
H_2P2 ON/OFFBTN# RZ27
+3VALW LID_SW#
10K_0402_5%

PJSOT24C_SOT23-3
1

1
1
ZZZ CZ25

DZ4
0.1U_0402_25V6
2

1
H15 H16
H_4P0 H_4P0
PCB
DAZ0DD00200 Place closed to JPWR1
1

(DA80000I510)
(For ESD request)

H17 H18
H_3P4x3P9 H_3P4
2 2
1

Touch/B Connector JTP1

CONN@ Vendor pin defined
+5VS 1 VCC
1. VDD
<26> TP_CLK 2
2 <26> TP_DATA 3
4
NC
Num_Lock 2. PS2CLK
GND
CE15 1 1 3. PS2DATA

100P_0402_50V8J

100P_0402_50V8J
1U_0402_6.3V6K CE16 CE17 5
1 GND

PJDLC05_SOT23-3
6 GND 4. GND
2 2 ACES_88514-0401

DE1
SP01000R400
@

1
3 3

System SPI Flash ROM (16Mb)

+3VALW
UE24
FSEL#SPICS# 1 8 RE29 10K_0402_5%
FSEL#SPICS# FRD#SPI_SO CS# VCC
<26> FSEL#SPICS# 2 SO HOLD# 7 1 2 1

0.1U_0402_16V7K
+3VALW 1 2 3 6 SPI_CLK_R
FWR#SPI_SI RE28 WP# SCLK FWR#SPI_SI CE18
<26> FWR#SPI_SI 4 GND SI 5
10K_0402_5%
FRD#SPI_SO MX25L1605DM2I-12G_SO8 2
<26> FRD#SPI_SO
SA00002TO00

<26> SPI_CLK SPI_CLK 2 1 SPI_CLK_R CIS symbol need apply

RE30 1
33_0402_5%~D CE19
33P_0402_50V8J
Close KB926 pin 126 2

4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SW/ROM/TP/PWR/SCREW
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 11, 2010 Sheet 31 of 45
A B C D E
 5 4 3 2 1

Power block
Battery OVP CPU OTP
Page 33 Page 33
D D

Turn Off Turn Off

Input B+
DC IN Switch Page 34 +3VALWP TDC= 5.47A Ipeak= 7.81A
+5VALWP TDC= 6.22A Ipeak= 8.88A MAINPWON

TPS51427 Page 36
CHARGER
CC:0A~3A
CV:14.8V(8cell) +3VALW for Vin +1.8VP TDC= 0.87A Ipeak= 1.25A
+5VALW for VCNTL SUSP#

C
ISL6251AHAZ-T Page 35 APL5912 Page 40 C

+3VS for Vin +2.5VDDAP TDC= 0.18A Ipeak= 0.25A

Battery
APL5508 Page 41

+1.1VALWP TDC= 6.7A Ipeak= 9.55A

SYSON

TPS51218DSCR Page 37

+1.5VP TDC= 6.95A Ipeak= 9.93A

SYSON
B B

TPS51218DSCR Page 39

+1.5VP for Vin

+3VALW for VCNTL
+0.75VSP TDC= 0.35A Ipeak= 0.5A SUSP

+CPU_CORE APL5331 Page 38

TDC=12.6A
Ipeak=18A +1.5V for Vin
VR_ON
+5VALW for VCNTL
+CPU_VDDRP TDC= 1.05A Ipeak= 1.5A SUSP#
+VDDNBP(0.9v)
APL5912 Page 41
TDC=2.8A
Ipeak=4A

ISL6265AHRTZ-T +NB_COREP TDC= 8.4A Ipeak= 12A SUSP#

A A
Page 42

TPS51218DSCR Page 43

Title
POWER BLOCK DIAGRAM
Size Document Number Rev
LA-6132P
Date: Tuesday, April 06, 2010 Sheet 32 of 45
5 4 3 2 1
 A B C D

1
@ PD1 @ PD2 CPU OTP
PJSOT24C_SOT23-3 PJSOT24C_SOT23-3
BATT+
BATT++ PH1 under CPU botten side :

3
CPU thermal protection at 90 +-3 degree C
BATT+

1
PL1 Recovery at 50 +-3 degree C 1

1 2 BATT++
+3VALWP

100P_0402_50V8J
SMB3025500YA_2P
100P_0402_50V8J

1
VL VS

PC4
PC3
1

1
PC1

PC2
1000P_0402_50V7K

2
0.01U_0402_25V7K

2
2

PR1
Place clsoe to EC pin
47K_0402_5% PR2
1 2 BATT_TEMP BATT_TEMP <26>

1
1K_0402_1%~D

2
PR3 PC400

2
10.7K_0402_1%~D 0.1U_0603_25V7K
@ PC5
PJPB1 battery connector

1
0.1U_0402_16V7K
VL

2
ME@ PJBATT
1 1 PR4

2
SMART 2 2
3 PR5
1 2
3 3S <35> 147K_0402_1%~D PR6
Battery: 4 4
5
2 1
1
PR7
2 205K_0402_1%~D
5 +3VALWP PR8
6 1K_0402_1%~D

1
6 6.49K_0402_1%~D

8
7 61.9K_0402_1%
7 PD3
1.BAT+ 10 8 OTP_IN 1 2 OTP_IN+ 3

P
GND 8 +
11 GND 9 9 PR10 0 1OTP_OUT
1 2 MAINPWON <34,36>
2.BAT+ PR9 VL 1 2 OTP_IN- 2 -

G
SUYIN_200275MR009G186ZL 1 2 EC_SMB_DA1 <26> 1SS355TE-17_SOD323-2
150K_0402_1%
3.ID 100_0402_1% PU1A

4
1
LM358ADR_SO8
4.B/I PH1

1
100K_0402_1%_TH11-4H104FT

1
5.TS
2 2

PR12 PC6 PR11 PC7

2
6.SMD 1 2 EC_SMB_CK1 <26> 1000P_0402_50V7K

2
150K_0402_1% 1U_0603_10V6K~D
100_0402_1%

2
7.SMC
8.GND
9.GND

COIN RTC Battery

BATT+
ME@ PJRTC

1
4 NC2 2 2 +COINCELL
PQ1 3 NC1 1 1
PR13
TP0610K-T1-E3_SOT23-3 ACES_85204-0200N 453K_0402_1%~D
PR14 VS

2
B+ 1 2 3 1
B+_BIAS

0.01U_0402_25V7K
100_0805_5%~D

1
470K_0402_5%~D

+5VALW PR16
2

PC8 499K_0402_1%

1
PR15

PC9
0.1U_0805_25V7M~D
1

2
2

2
1
1

3 3

PU1B
2

8
PR17
LM358ADR_SO8
220K_0402_5% PD4 PR18 5

P
+
2 1 7
2

1SS355TE-17_SOD323-2 <26> BATT_OVP 0

6
1

D -

G
PQ2 10K_0402_1%~D

1
2

1
G RHU002N06_SOT323-3
PR19 PC10
S
3
2

120K_0402_1% 0.01U_0402_25V7K
1

2
PC11 PR20

2
0.1U_0603_25V7K 220K_0402_5%
2

LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/2/6 Deciphered Date 2010/2/6 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6132P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 04, 2010 Sheet 33 of 45
A B C D
 A B C D

Vin Detector @ PC12

2200P_0402_50V7K~D @ PR21

ADPIN VIN Max. typ. Min. 1 2 1 2

56K_0402_5%~D
L-->H 18.234 17.841 17.449
PL2
H-->L 17.597 17.210 16.813 PR22
1 2
DC_IN_S1 1 2 1M_0402_1%~N
SMB3025500YA_2P
VIN VIN
VS

0.01U_0402_25V7K
ME@ PJDCIN

1
1

1
1 1
PR24

PC17
1 PC13 PC14 PR23 PR25
1 PC15 PC16 10K_0402_5%
2 2 100P_0402_50V8J 1000P_0402_50V7K 82.5K_0402_1%~D 1 2ACIN ACIN <18,26>
3 1000P_0402_50V7K 100P_0402_50V8J
1K_0402_1%~D

2
3
4 PU4A

2
4

8
5 5 PR26
6 N41 1 2 N40 3

P
6 +

0.1U_0402_16V7K
7 22K_0402_1% 1 PACIN <35>

20.5K_0402_1%~D
GND N35 O
GND 8 2 -

1
1

1
ACES_88299-0600 LM393DR_SO8

PC18
PC19

PR27

4
PL3 PD5 PR28
FBM-L11-160808-601LMT 0603~D 1000P_0402_50V7K RLZ4.3B_LL34 10K_0402_5%

2
2 1 DOCK_PSID

2
+5VALW +3VALW
PR30 RTCVREF
PR29 2 1
1 2 10K_0402_5%
1K_1206_5%
PQ3
3.3V
TP0610K-T1-E3_SOT23-3
PD6

2
VIN PR31 B+ @ PR32
2 1 1 2 3 1 1 2 PR33
1K_1206_5% 0_0402_5% 2.2K_0402_5%~D
RLS4148_LL34-2
PR34

1
1 2 PD7

100K_0402_5%

1
100K_0402_5%
DA204U_SOT323~D
1K_1206_5% ACIN PR37
1

1
DOCK_PSID

S
PR36 1 3 1 2 PS_ID <26>

PR38
PR35
Precharge detector PQ4 33_0402_5%~D

2
2 2
1 2
FDV301N_NL_SOT23-3~D
Min. typ. Max.

G
1K_1206_5%

2
100K_0402_1%
+5VALW
2

2
+5VALW
H-->L 14.589V 14.84V 15.243V

PR39
L-->H 15.562V 15.97V 16.388V

10K_0402_1%~D

DA204U_SOT323~D
1

2
1
1

1
C

PR41
BATT ONLY 2 PQ5
@ PD9
1

PR40

15K_0402_1%~D
PQ6 B MMST3904-7-F_SOT323~D
Precharge detector

2
100K_0402_5% E

2
DTC115EUA_SC70-3

PR42
1 2
Min. typ. Max.

1
@

1
2 PD8 @ PR43
<26,35> ACOFF
PQ7 H-->L 6.138V 6.214V 6.359V SM24_SOT23 1 2 PSID_DISABLE# <26>

1
DTC115EUA_SC70-3
L-->H 7.196V 7.349V 7.505V 10K_0402_1%~D
2
3

B+
3

VL PR44
2 1
2.2M_0402_5%
VIN

1
2

VS PR47
3 3

PD10 499K_0402_1%

1
RLS4148_LL34-2 PR49

2
100K_0402_1%
PD11
1

BATT+ 2 1

8
1

PD12
RLS4148_LL34-2 PR45 PR46
2 5

P
68_1206_5% 68_1206_5% <33,36> MAINPWON +
PQ8 1 7 O
<35> ACON 3 - 6

1
TP0610K-T1-E3_SOT23-3 LM393DR_SO8

1000P_0402_50V7K

1
2

PR48 RB715F_SOT323-3 PU4B PR52

PR53 PC24

4
1

1
CHGRTCP 1 2 N1 3 1 PC22 191K_0402_1%

PC23
499K_0402_1% 0.01U_0402_25V7K
200_0603_5% VS 0.1U_0603_25V7K

2
2

PRG++ 2

2
1

PR50
100K_0402_1% PC21
PC20 0.1U_0603_25V7K
2

0.22U_0603_25V7K
2

PR51 PQ9 PR56

1
PR55 D RHU002N06_SOT323-3 47K_0402_5%
<23,31> 51ON# 1 2
2 1 2 2 1
22K_0402_1% RTCVREF G
PACIN <35>
34K_0402_1%

1
S

3
PQ10
DTC115EUA_SC70-3
RTCVREF
1

2 +5VALW
PR54
PU5
200_0603_5%
4 APL5156 SOT89 3P 4

3.3V

3
2

3 2 N2
OUT IN
1

GND PC26
PC25 1U_0805_25V4Z
10U_0805_10V4Z 1
Compal Electronics, Inc.
2

Security Classification Compal Secret Data

Issued Date 2009/2/6 Deciphered Date 2010/2/6 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6132P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 04, 2010 Sheet 34 of 45
A B C D
 A B C D

Iada=0~3.34A(65W)
ADP_I = 19.9*Iadapter*Rsense
CP = 90%*Iadapter (rating); CP = 3.003A
PQ11 PQ12 PQ13
P2
AO4407A_SO8 SI4459ADY-T1-GE3_SO8 P3
PR57 B+ AO4407A_SO8
0.02_2512_1%
VIN 8 1 1 8 1 8
7 2 2 7 1 4 2 7
6 3 3 6 3 6
5 5 2 3 CSIN 5

2200P_0402_25V7K
0.1U_0603_25V7K
1 1

10U_1206_25V6M

10U_1206_25V6M
CSIP

4
1

1
PQ14 TP0610K-T1-E3_SOT23-3

PC28
PC27

PC30
PC29
5600P_0402_25V7K
1

1
PR60

0.1U_0603_25V7K
3 1 PQ17toRP9 1 2 DCIN PR61
PR58
P3

2
1

2
PR59 10_1206_5% 1 2

100K_0402_1%
PC31
VIN

1
PC32
47K_0402_1% 200K_0402_1% 47K_0402_1%
PQ15
2

1
PR62
DTC115EUA_SC70-3

2
PD13
PD14 PR63 1 2 ACOFF

2
3

PQ16 2 FSTCHG 10K_0402_1%

PR64

2
DTA144EUA_SC70-3 2 1 2 1 1SS355TE-17_SOD323-2
1SS355TE-17_SOD323-2 100K_0402_1% 3 SUSP#

1
2 1 2 6251VDD
<26,30,40,41,43> SUSP#
RB715F_SOT323-3

2.2U_0603_6.3V6K
PD15 PR65
PR66 1 2

PC33
VIN

3
1
10K_0402_5% 200K_0402_1%

1
<26> FSTCHG 2 1 PU6
1

PC35
PC34
1

2
PR67 1 2 1 24 DCIN 2 1 PD16
VDD DCIN

1
100K_0402_1%
6251VDD 1 2 PQ18 1SS355TE-17_SOD323-2
0.1U_0402_16V7K 0.1U_0603_25V7K DTC115EUA_SC70-3 2 1 2
47K_0402_5%

PR68
1
2 2 ACSET ACPRN 23 PQ20
PQ17 PQ19
RHU002N06_SOT323-3

1
DTC115EUA_SC70-3 DTC115EUA_SC70-3 D
PR69

5
6
7
8

1
0.1U_0603_25V7K
6251_EN 3 22 1 2 CSON 2 PACIN

3
EN CSON
1

2
D

PC37
<33> 3S 2 PC36 20_0603_5% G
3

2 0.047U_0603_16V7K PQ22 S

3
G PR70 CSOP
4 21 1 2

1
CELLS CSOP
S PQ21 150K_0402_1% PR71 20_0603_5% SI4128DY-T1-GE3
3

2
RHU002N06_SOT323-3 PC38 4 2
2

3
1 2 5 ICOMP CSIN 20 2 1

2
6800P_0402_25V7K PC40 PR72 20_0603_5%
PC39 PR73 0.1U_0603_25V7K
1 2 1 2 6 19 1 2 PR76

3
2
1
VCOMP CSIP PL4
10K_0402_1% PR74 2.2_0603_5%
0.01U_0402_25V7K PR75 10UH_PCMB063T-100MS_4A_20% 0.02_2512_1% BATT+
1 2 7 18 LX_CHG 1 2 CHG 1 4
ICM PHASE
1

D
PR77 100_0402_1%
<34> PACIN PACIN 1 2 2 PQ23 2 3

1
22K_0402_5% G RHU002N06_SOT323-3 6251VREF 8 17 DH_CHG
<26> ADP_I VREF UGATE

5
6
7
8
S PC41 PR78
3

10U_1206_25V6M
10U_1206_25V6M
1 2 PC42 PQ24 4.7_1206_5%
PR79
PR80 9 16 BST_CHG 1 2 BST_CHGA 2 1 SI4128DY-T1-GE3
CHLIM BOOT

1
ACON 2 1 0.1U_0402_16V7K 2.2_0603_5%
<34> ACON <26> IREF

1 2

1
PD17 0.1U_0603_25V7K

PC46
0.01U_0402_25V7K

PC45
150K_0402_1%
6251ACLIM 10 15 6251VDDP RB751V-40TE17_SOD323-2 4
ACLIM VDDP PC44
1

680P_0603_50V_NPO

2
PR82
1

PQ25 26251VDD
PC43

2
DTC115EUA_SC70-3 PR81 DL_CHG
11 VADJ LGATE 14 4.7_0603_5%

2
100K_0402_1%
2

3
2
1
ACOFF 2 PC47
<26,34> ACOFF
2

12 13 4.7U_0805_6.3V6K

1
GND PGND
PR83
6251VREF 1 2 ISL6251AHAZ-T_QSOP24
3

11.5K_0402_1%
1

PR84
2.74K_0402_1%~D
CP mode
2

3 3

Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)
Vaclim=2.39*((2.74K//152K)/((2.74K//152K)+(11.5K//152K)))
PR85
<26> CHGVADJ 1 2
18.2K_0402_1%
1

CC=0.6~3.3A PR86
31.6K_0402_1%
CHGVADJ CV mode
IREF=1*Icharge
2

IREF=0.6V~3.3V 0V 3.99V per cell

1.91V 4.2V per cell

3.3V 4.35V per cell

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/2/6 Deciphered Date 2010/2/6 Title
-
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-6132P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 04, 2010 Sheet 35 of 45
A B C D
 5 4 3 2 1

TPS51427_B+
TPS51427_B+

PR87
PJP5 0_0805_5%~D
2 1 1 2
B+ 2 1

2200P_0402_50V7K~D
1000P_0402_50V7K

1000P_0402_50V7K

4.7U_0805_25V6-K~D

4.7U_0805_25V6-K~D
0.1U_0603_25V7K

2200P_0402_50V7K~D

0.1U_0603_25V7K
4.7U_0805_25V6-K~D

4.7U_0805_25V6-K~D
JUMP_43X118

VL
1

8
7
6
5

5
6
7
8

PC55

PC56
PC52

PC53

PC54
D D
PC49

PC50

PC51

1
PC57

PC58
PQ26 PQ27
2

2
AO4466_SO8 AO4466_SO8

1U_0603_10V6K~D

2
2
PC59

4.7U_0805_6.3V6K
2
4 4

PC60

1
0.1U_0603_25V7K

PC61
1

1
+5VALWP

2
1
2
3

3
2
1
PL5
PL6 2.2UH_PCMC063T-2R2MN_8A_20%

7
3.3UH_PCMB064T-3R3MS_7A_20% PU2 PC62 1 2
2 1 1U_0603_10V6K~D

VIN

V5FILT

LDO
+3VALWP

5
6
7
8
33 TP V5DRV 19 1 2 PQ28

8
7
6
5

1
1
PQ29 DH3 DH5 AO4710_SO8 PR89
26 DRVH2 DRVH1 15
PR88 AO4710_SO8 PR90 PR91 4.7_1206_5%
4.7_1206_5% 2 1 BST3A 24 VBST2 VBST1 17 BST5A 2 1
1

61.9K_0402_1%
0_0603_5% 0_0603_5% 4

2
2

2
4
330U_D3L_6.3VM_R25M

PR92

2
0.1U_0402_10V7K~D

PC66 PC63

330U_D3L_6.3VM_R25M
1 0_0402_5%

2
0.1U_0603_25V7K 0.1U_0603_25V7K

0.1U_0402_10V7K~D
1

1
PC68
1

PR93
+ LX3 LX5
PC65

25 16 1
2

3
2
1
PC67 LL2 LL1
PC64

680P_0402_50V7K~D

1
2
3

1
680P_0402_50V7K~D +

PC69

PC70
2

2
2 DL3 DL5
23 18

1
DRVL2 DRVL1

2
2

0.1U_0603_25V7K
2
0.1U_0603_25V7K

C 22 C

10K_0402_5%

PC96
PGND
2

2
@ PR94 FB3 30
@ VOUT2

2
PR95
10K_0402_5%
PC95

10
1

VOUT1 @
VL 32
1

1
REFIN2

1
11 FB5
2VREF_TPS51427 FB1
PC71
1 2 1 VREF2
0.22U_0603_10V7K
VSW 9
8 LDOREFIN
@ PR96 +3VALW
SKIPSEL 29 2 1 VL

1
0_0402_5%
PR97 PR119
1 2 10K_0402_1%~D
20 NC PGOOD2 28 0_0402_5%
PD18

2
GLZ5.1B_LL34-2 PR98 POK <37>
1 2 1 2 4 13
VS 100K_0402_1%
EN_LDO PGOOD1
2

0.22U_0603_25V7K
PR100
2

14 12 ILM1 2 1
PR99 PC72 EN1 TRIP1
324K_0402_1%~D
200K_0402_1%

TONSE
VREF3
PR101
1

27 31 ILIM2 2 1

GND
1

EN2 TRIP2
1

B B
280K_0402_1%

2
VL

0_0402_5%
2
PD19 @ PR102 TPS51427_QFN32_5X5

21
PR103
1SS355TE-17_SOD323-2
PJP6
2

0_0402_5% PJP8

1U_0603_10V6K~D
2

1 1 2 2 PR104
1
1 2

1
+5VALWP 1 2 +5VALW
2VREF_TPS514271
806K_0603_1%~D

2
JUMP_43X118

PC73
JUMP_43X118
1

PJP7 PR105
PR106 @ PR107

1
1 2 2 1 1 2 0_0402_5%
+3VALWP +3VALW <33,34> MAINPWON

2VREF_TPS514272
1 2
0_0402_5% 47K_0402_5%
JUMP_43X118
+5VALWP
1
0.047U_0603_16V7K
PC74

Thermal Design Current=6.22A

+3VALWP
2

Peak Current=8.88A
1

Thermal Design Current=5.47A @ PC75

@PC75 OCP min=11.55A
3

Peak Current=7.81A 0.047U_0402_16V7K~D

Fsw=400KHZ
2

OCP min=10.15A Delta I=2.82 A

Fsw=300KHZ PQ30
2
TP0610K-T1-E3_SOT23-3
Delta I=2.7692 A OCP setting resistor: PR100
A A
OCP setting resistor: PR101
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/2/6 Deciphered Date 2010/2/6 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6132P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 04, 2010 Sheet 36 of 45

5 4 3 2 1
 A B C D

1 1

PJP10
+1.1VALWP_B+ 2 1
2 1 B+
JUMP_43X118

2200P_0402_50V7K~D

0.1U_0603_25V7K

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
1

1
@ PC80
PC77

PC78

PC79
PC76
2

2
+1.5VP

5
6
7
8
@ PR120 @ PR108

D
D
D
D
0_0402_5% 100K_0402_1% PQ31
PR109 PC81
1 2 1 2 FDS6298_SO8~D
2

2
2 2.2_0603_5% 0.22U_0603_25V7K 2
4 G
PU7
PG_1.1VALWP 1 10 BST_1.1VALWP
PGOOD VBST

S
S
S
PR110
1 2 TRIP_1.1VALWP 2 9 UG_1.1VALWP

3
2
1
TRIP DRVH PL7
PR111 68.1K_0402_1%
1 2 EN_1.1VALWP 3 8 SW_1.1VALWP 1 2
<36> POK EN SW +1.1VALWP
0_0402_5%
FB_1.1VALWP V5IN_1.1VALWP 1UH_PCMC063T-1R0MN_11A_20%
4 VFB V5IN 7 +5VALW
1

5
6
7
8

10U_0805_6.3V6M~D
@ PC82
PQ32

0.1U_0402_10V7K~D
RF_1.1VALWP 5 6 LG_1.1VALWP 1
0.1U_0402_16V7K RF DRVL SI4634DY-T1-E3_SO8 PR112
1 1
2

1
4.7_1206_5% +

PC85
TP 11 PC86
1

PC83

PC84
2
TPS51218DSCR_SON10_3X3~D 1U_0603_6.3V6M~D 4 330U_D2_2.5VY_R9M

2
2 2 2
PR113

1
470K_0402_5%~D
PC88
2

680P_0603_50V_NPO

3
2
1

2
PR114 PR115
1 2 2 1
3
20K_0402_1%~D 11.5K_0402_1% 3

PJP11
@ PC97 JUMP_43X118
1 2 1 1 2 2
0.1U_0603_25V7K
PJP12
JUMP_43X118
+1.1VALWP 1 1 2 2 +1.1VALW

+1.1VALWP
Thermal Design Current=6.7A
Peak Current=9.55A
OCP min=12.42A
Fsw=290KHZ

Delta I=3.5791A
L/S MOS Rds(on)=5.5m (Typ) ; 6.7m (Max)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/2/5 Deciphered Date 2008/6/05 Title
+1.1VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6132P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 04, 2010 Sheet 37 of 45
A B C D
 A B C D

+1.5VP

1
PJP13

1
JUMP_43X79

2
2
PU8
1

1 VIN VCNTL 6 +3VALW 1

2 GND NC 5

1
1K_0402_1%~D
PC89 PC90

1
4.7U_0805_6.3V6K 3 VREF NC 7 1U_0603_10V6K~D

2
PR116 4 8
VOUT NC
9

2
TP
APL5331KAC-TRL_SO8
PQ33

0.1U_0402_16V7K
SSM3K7002F_SC59-3
+0.75VSP

1K_0402_1%~D
1

1
D
PR117

PC91
<30> SUSP 1 2 2

1
10K_0402_1% G PR118 PC93

2
0.1U_0402_16V7K
1
PC92 S

3
10U_0603_6.3V6M~D

2
2
PJP14
+0.75VSP 2 2 1 1 +0.75VS
JUMP_43X118
2 2

+0.75VSP
Thermal Design Current=0.35A
Peak Currnet=0.5A
OCP min=0.65A

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/2/5 Deciphered Date 2008/6/05 Title
+0.75VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6132P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 04, 2010 Sheet 38 of 45
A B C D
 5 4 3 2 1

D D

PJP17
+1.5VP_B+ 2 1
2 1 B+
JUMP_43X118

2200P_0402_50V7K~D

0.1U_0603_25V7K

10U_1206_25V6M

10U_1206_25V6M
1

1
PC100

PC102
PC101
PC99
2

2
+1.5VP

5
6
7
8
1

1
PQ35

D
D
D
D
@ PR121 @ PR124 FDS6298_SO8~D
0_0402_5% 100K_0402_1% PC103
PR125
1 2 1 2 4
2

G
2
2.2_0603_5%
0.22U_0603_25V7K

S
S
S
C C
PU10
PG_1.5VP BST_1.5VP

3
2
1
1 PGOOD VBST 10
PR126
1 2 TRIP_1.5VP 2 9 UG_1.5VP
TRIP DRVH PL8
PR127 68.1K_0402_1%
1 2 EN_1.5VP 3 8 SW_1.5VP 1 2
<26> SYSON EN SW +1.5VP
0_0402_5% 1UH_PCMC063T-1R0MN_11A_20%
FB_1.5VP V5IN_1.5VP

330U 2.5V Y D2 LESR15M CX H1.9

4 VFB V5IN 7 +5VALW
1

5
6
7
8

10U_0805_6.3V6M~D
0.1U_0402_10V7K~D
@ PC104 RF_1.5VP 5 6 LG_1.5VP 1 1
RF DRVL PQ36
1 1
2

0.1U_0402_16V7K PR128

PC107

PC87

PC94
11 + +
TP PC105 SI4634DY-T1-E3_SO8 4.7_1206_5%
1

PC106
TPS51218DSCR_SON10_3X3~D 1U_0603_6.3V6M~D

2
PR129 2 4 2 2 2 330U 2.5V Y D2 LESR15M CX H1.9
470K_0402_5%~D

1
PC112
2

680P_0402_50V7K~D

3
2
1

2
PR130 PR131

14.3K_0402_1% 16.5K_0402_1%
1 2 2 1

B @ PC98 B
1 2
0.1U_0603_25V7K

PJP19
JUMP_43X118
1 1 2 2

PJP20
JUMP_43X118
+1.5VP 1 1 2 2 +1.5V

+1.5VP
Thermal Design Current=6.95A
Peak Current=9.93A
OCP min=12.9A
Fsw=290KHZ
A A
Delta I=4.7745A
L/S MOS Rds(on)=5.5m (Typ) ; 6.7m (Max)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date Title
Deciphered Date
+1.5VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6132P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 04, 2010 Sheet 39 of 45
5 4 3 2 1
 A B C D

1 1

+3VALW

+5VALW

1
PJP21

1
JUMP_43X79

2
PC113

2
1U_0402_6.3V6K

2
6

1
PU11 PC114
5

VCNTL
VIN 4.7U_0805_6.3V6K
7

2
POK
VOUT 4

VOUT 3 +1.8VP
PR132

1
<26,30,35,41,43> SUSP# 1 2 8 EN FB 2 PC116

1
GND
10K_0402_1% PR133

1
PC115 22U_0805_6.3V6M
9

2
VIN 1.58K_0402_1%

1
PC117 0.01U_0402_25V7K

2
@ PR134 APL5912KAI-TRL_SO8
2.2U_0402_6.3V6M

2
47K_0402_5%

1
2
PJP22 2

PR135
1 1 2 2 +1.8VS
1.27K_0402_1% +1.8VP

2
JUMP_43X79

+1.8VP
Thermal Design Current=0.87A
Peak Currnet=1.25A
OCP min=1.62A

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/2/5 Deciphered Date 2008/6/05 Title
+1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6132P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 04, 2010 Sheet 40 of 45
A B C D
 5 4 3 2 1

D D

+1.5V

+5VALW

1 1
PJP23
JUMP_43X79

2
PC118
1U_0402_6.3V6K

2
2
6

1
PU12 PC119
5 4.7U_0805_6.3V6K

VCNTL
VIN
7

2
POK
VOUT 4

VOUT 3 +CPU_VDDRP
PR136

1
<26,30,35,40,43> SUSP# 1 2 8 EN FB 2 PC121

1
PC120
PR137

GND
10K_0402_1%

1
22U_0805_6.3V6M
9

2
VIN

1
1.05K_0402_1%~D 0.01U_0402_25V7K

2
PC122 @ PR138 APL5912KAI-TRL_SO8

2
2.2U_0402_6.3V6M 47K_0402_5%

2
PJP24

1
C 1 1 2 2 +CPU_VDDR C
@ PR139
+CPU_VDDRP
PR167
3.32K_0402_1% 8.25K_0402_1% JUMP_43X79

for 1.05V for 0.9V

2
+CPU_VDDRP
Thermal Design Current=1.05A
Peak Currnet=1.5A
OCP min=1.95A

PU13
APL5508-25DC-TRL_SOT89-3

+3VS 2 3
IN OUT +2.5VDDAP

4.7U_0805_6.3V6K

1
B GND B
PJP25
1

1
@ PR140

PC123
PC124 1
150_1206_5% +2.5VDDAP 1 1 2 2 +2.5VDDA
1U_0402_6.3V6K
2

2
JUMP_43X79

+2.5VDDAP
Thermal Design Current=0.18A
Peak Currnet=0.25A
OCP min=0.33A

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+2.5VDDAP/+CPU_VDDRP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6132P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 04, 2010 Sheet 41 of 45
5 4 3 2 1
 5 4 3 2 1

CPU_B+ PL9
HCB4532KF-800T90_1812
1 2 B+

10U_1206_25V6M
PC125
33P_0402_50V8J~N
1

5
6
7
8
2 1

1
PC127
+
PC126 PC128
PR141
2 1 2 1 PQ37 100U_25V_M

2
2
44.2K_0402_1% AO4466_SO8
UGATE_NB 4
1000P_0402_50V7K

PR142 PL10
1 2 PC129 3.3UH_PCMC063T-3R3MN_6A_20%
D +5VS D

3
2
1
10_0603_5% 1000P_0402_50V7K PHASE_NB 1 2
2 1 +VDDNBP

1
PR172 PC131

5
6
7
8
PC130
0.1U_0603_16V7K~N PR143 BOOT_NB
1 2 1 2 PR144
PQ38 4.7_1206_5%
2 1 0_0603_5%

2
22K_0402_1% 0.22U_0603_10V7K AO4712_SO8 1
PR145

1 2
1 2 +VDDNBP LGATE_NB + PC132
PR146 4
1 2 10_0402_5% PC133 220U_D2_4VM
CPU_B+ 680P_0603_50V_NPO
10_0603_5% PR147
2 1 CPU_VDDNB_RUN_FB_H <8>
2 +VDDNBP(0.9v)

2
0_0402_5%
TDC=2.8A

3
2
1
+5VS +3VS PR148
2 1 PHASE_NB
11.3K_0402_1%
Peak Current=4A
LGATE_NB
OCP min=5.2A

1
PC134
PHASE_NB
0.1U_0603_25V7K Iripple= 0.8671
1

2
PR149 @ PR150 UGATE_NB
0_0402_5% 105K_0402_1%
Fsw=300KHZ
PR151
2 1 CPU_VDDNB_RUN_FB_L
0_0402_5%
2

2
1

2
PJP15
PR154
PR152 @PR153
@ PR153 +VDDNBP 2 2 1 1 +VDDNB
105K_0402_1% 10_0402_5% CPU_B+
10K_0402_1% JUMP_43X118
1

48

47

46

45

44

43

42

41

40

39

38

37
2

1
@ PR155 PU14
105K_0402_1%

VIN

VCC

FB_NB

COMP_NB

FSET_NB

VSEN_NB

RTN_NB

OCSET_NB

PGND_NB

LGATE_NB

PHASE_NB

UGATE_NB

10U_1206_25V6M
10U_1206_25V6M
C C

5
2

<8,26> VGATE VGATE 1 36 BOOT_NB

OFS/VFIXEN BOOT_NB

PC136
1

1
PC135
<8> CPU_PWRGD_SVID_REG 2 35 BOOT0 PQ39
PGOOD BOOT0
PR171 SI7686DP-T1-E3_SO8
2 1 3 34 UGATE0

2
<8> CPU_SVD PWROK UGATE0 UGATE0
0_0402_5% 4
PR156
<8> CPU_SVC 2 1 4 33 PHASE0
SVD PHASE0
0_0402_5% PR161 PHASE0 PL11
<26> VR_ON 2 1 5 SVC PGND0 32 +5VS

3
2
1
0_0402_5% PR157 PC137 0.36UH_PCMC104T-R36MN1R17_30A_20%
6 31 LGATE0
ENABLE ISL6265AHRTZ-T_TQFN48_6X6 LGATE0 BOOT0 1 2 1 2 1 4
PR162 PR163 +CPU_CORE
2 1 2 1 7 30 0_0603_5%
RBIAS PVCC 0.22U_0603_10V7K 2 3
113K_0402_1% 4.02K_0402_1% ISP0_1
8 29

1
1
OCSET LGATE1

2
5
6
7
8

5
6
7
8
9 28 PC140 PR159
VDIFF0 PGND1 1U_0603_10V6K~D PQ40 PQ41 PR158

D
D
D
D

D
D
D
D
2
FDS6676AS_SO8 4.7_1206_5%
10 27 FDS6676AS_SO8 3.65K_0805_1%
FB0 PHASE1

1 2

1
11 COMP0 UGATE1 26 PC138 PR160

G
S
S
S

S
S
S
1 2
12 25 47K_0402_1%

4
3
2
1

4
3
2
1
VW0 COMP1 BOOT1 680P_0603_50V_NPO
VDIFF1

2
VSEN0

VSEN1
RTN0

RTN1

PC139
ISN0

ISN1
ISP0

VW1

ISP1
FB1

TP
2 1
0.1U_0603_16V7K~N
13

14

15

16

17

18

19

20

21

22

23

24

49
@ PR164 @ PH2
B ISP0 LGATE0 2 1 2 1 B
ISN0 10_0402_5%
ISN0
ISP0

10K_0603_5%_TSM1A103J4302RE
PR165

ISN0
<8> CPU_VDD0_RUN_FB_H 2 1 VSEN0

ISP0
PR166 0_0402_5%
+CPU_CORE 2 1
10_0402_5%
<8> CPU_VDD0_RUN_FB_L 2 PR168 1 RTN0 RTN1
0_0402_5%
1

+CPU_CORE
2
10_0402_1%
PR170

PR169 Thermal Design Current=12.6A

0_0402_5%
Peak Current=18A
2
1

+1.8VS OCP min=24A

Fsw=300KHZ
PR175
<8> CPU_VDD0_RUN_FB_H 2 1VSEN1
0_0402_5%

DIFF_0 VW0

PR178 PC146 PC147 PC148

2 1 2 1 FB_0 2 1 COMP0 2 1
255_0402_1% 1000P_0402_50V7K
180P_0402_50V8J~N
4700P_0402_50V7K~D
A A

PR180 PR181 PC152 PR182

2 1 2 1 2 1 2 1
1K_0402_1%~D 54.9K_0402_1% 6.81K_0402_1%
1000P_0402_50V7K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/2/5 Deciphered Date 2009/2/5 Title
+CPU_CORE/+VDDNBP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6132P 0.22
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 04, 2010 Sheet 42 of 45
5 4 3 2 1
 A B C D

1 1

PJP26
+NB_COREP_B+ 2 1 B+
2 1
JUMP_43X118

2200P_0402_50V7K~D

0.1U_0603_25V7K

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
1

1
PC155
PC154

PC156

PC157

PC158
2

2
@

+3VALW

5
6
7
8
@ PR122 PR188 @
0_0402_5% 100K_0402_1% PQ45

D
D
D
D
PC159
PR189 FDS6298_SO8~D
2

2 1 2 1 2
2 2
2.2_0603_5%
0.22U_0603_25V7K 4
PU15 G
PG_NB_COREP 1 10 BST_NB_COREP
PGOOD VBST

S
S
S
PR190
1 2 TRIP_NB_COREP 2 9 UG_NB_COREP

3
2
1
TRIP DRVH PL13
PR191 86.6K_0402_1%
<26,30,35,40,41> SUSP# 1 2 EN_NB_COREP 3 8 SW_NB_COREP 1 2
EN SW +NB_COREP
0_0402_5% 1UH_PCMC063T-1R0MN_11A_20%
FB_NB_COREP 4 7 V5IN_NB_COREP
+5VALW

10U_0805_6.3V6M~D
VFB V5IN
1

5
6
7
8
@ PC160

0.1U_0402_10V7K~D
RF_NB_COREP 5 6 LG_NB_COREP PQ46 1 1
0.1U_0402_16V7K RF DRVL

PC163
1 SI4634DY-T1-E3_SO8
2

1
11 PC161 PR192 + PC164
TP
1

PC162
4.7_1206_5% 330U_D2_2.5VY_R9M
TPS51218DSCR_SON10_3X3~D 1U_0603_6.3V6M~D 2
4

2
PR193 2 2
470K_0402_5%~D

1
2

PC167

3
2
1
680P_0402_50V7K~D

2
PR194 PR195
3 1 2 2 1 3

20K_0402_1%~D 11.3K_0402_1%
PJP27
@ PC108 JUMP_43X118
1 2 1 1 2 2
0.1U_0603_25V7K

PJP28
JUMP_43X118
+NB_COREP 1 1 2 2 +NB_CORE

+NB_COREP
Thermal Design Current=8.4A
Peak Current=12A
OCP min=15.6A
Fsw=290KHZ

Delta I=3.8833A
L/S MOS Rds(on)=5.5m (Typ) ; 6.7m (Max)
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/2/5 Deciphered Date 2008/6/05 Title
+NB_COREP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6132P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 04, 2010 Sheet 43 of 45
A B C D
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 34 DCIN & DETECTOR 2009/12/30 Compal Dell has seen a couple of field return Change PQ4 from SB00000960L X01
D
systems at the other ODM with the ESD (S TR SSM3K7002FU 1N SC70-3) to SB503010010 D
damaged N-FET of PSID signal. (S TR FDV301N 1N SOT23-3)

X01
Change PC134 from SE026104KN0
2 42 +CPU_CORE 2009/12/30 Compal Over component rated voltage spec.
(S CER CAP .1U 16V K X7R 0603) to
/+VDDNBP
SE042104K80(S CER CAP .1U 25V K X7R 0603)

1 Add PR119 (P/N :SD034100280) X01

36 +5VALWP/+3VALWP 2009/12/30 Compal HW modify +1.1VALWP power sequence (S RES 1/16W 10K +-1% 0402) pull up +3VALW
3 at POK
37 +1.1VALWP
2. Change +1.1VALWP enable signal name from
"SYSON" to "POK" at Node PR111.1

1. [+3VALWP portion] Add @PC95 parallel at @PR94 X01

36 +5VALWP/+3VALWP 2009/12/30 Compal For QAD Temp/Volt margin test [+5VALWP portion] Add @PC96 parallel at PR95
C
4 C

37 +1.1VALWP 2. [+1.1VALWP portion] Add @PC97 parallel at PR114

39 +1.5VP 3. [+1.5VP portion] Add @PC98 parallel at PR130

4. [+NB_COREP portion] Add @PC108 parallel at PR194

43 +NB_COREP

Compal To prevent PQ5 damage issue Change PQ12 from SB00000DL00 (S TR AO4407A 1P SO8) X01
5 35 CHARGER 2009/12/30
to SB00000I600 (S TR SI4459ADY-T1-GE3 1P SO8)

Change X01
6 40 +1.8VP 2010/02/05 Compal HW modify +1.8VP, +CPU_VDDRP power sequence [+1.8VP portion] PC117 and
[+CPU_VDDRP portion] PC122
+2.5VDDAP from SE076104K80 (S CER CAP .1U 16V K X7R 0402)
41
/+CPU_VDDRP to SE00000888L (S CER CAP 2.2U 6.3V M X5R 0402)
B B

Change PR195 X01

43 +NB_COREP 2010/02/05 Compal HW modify power budget for +NB_COREP portion from SD00000QM80 (S RES 1/16W 14.3K +-1% 0402)
7
+NB_COREP output change from 1.2v to 1.1v to SD034113280 (S RES 1/16W 11.3K +-1% 0402)

2010/02/05 Compal Change PR115 X01

8 37 +1.1VALWP AMD measure (location :LN12) VDDPCIE Vmin under Spec
from SD034113280 (S RES 1/16W 11.3K +-1% 0402)
follow AMD suggestion to adjust voltage level to meet
to SD034115280 (S RES 1/16W 11.5K +-1% 0402)
spec.

1. Change PC130, PC139 from X02

9 42 +CPU_CORE 2010/03/08 Compal change N0 suffix P/N to meet Dell suffix P/N (80 or 8L) SE026104KN0 (S CER CAP .1U 16V K X7R 0603) to
/+VDDNBP SE026104K8L (S CER CAP .1U 16V K X7R 0603)

2. Change PC125 from

SE068330KN0 (S CER CAP 33P 50V J NPO 0402) to
SE071330J80 (S CER CAP 33P 50V J NPO 0402)
A A
3. Change PC147 from
SE071181JN0 (S CER CAP 180P 50V J NPO 0402)to
SE071181J8L (S CER CAP 180P 50V J NPO 0402)
Compal Electronics, Inc.
Title
PWR-PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6132P
Date: Tuesday, April 06, 2010 Sheet 44 of 45
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Item Page# Title Date Request Issue Description Solution Description Rev.
Owner
1 16 SB 2010/01/19 HW Boou up issue POP RS27 X01

2 17 SB 2010/01/19 HW Boou up issue UNPOP RS34, POP RS43 X01

D D

3 17 SATA 2010/01/19 HW SATA LED active ADD RS111 X01

4 17 SB 2010/01/19 HW Disable function UNPOP YS3, RS50, CS24, CS25 X01

5 19 CODEC 2010/01/19 HW CODEC voltage Change RS92 to 0 ohm, UNPOP RS93 X01

6 23 USB 2010/01/19 ESD ESD request POP DL1 X01

7 26 EC 2010/01/19 ESD ESD request ADD CE25 X01

8 30 PWR 2010/01/19 HW Boot up issue Change CZ4, CZ8, CZ19, CZ21 to 0.1U X01
Safety request reserve fuse to
9 24 VGA 2010/01/22 Safety meet LPS specification Add FV2 X01

10 30 PWR 2010/01/22 Sourcer Fairchild FDS8878 will EOL Modify QZ3, QZ8 to NTMS4107 X01

11 27 LVDS 2010/01/22 EC Reserve LVDS VDD control by EC Change RV40 to DV10 X01

12 18 SMbus 2010/01/25 HW SMbus waveform fixed Add RS25, RS28 (22ohm) on signal MEM_SMBCLK/MEM_SMBDATA X01

C
13 16,20,26 X'tal 2010/01/27 Vendor For X'tal EA test result Change CE12, CE13, CS14, CS15, CS16, CS17, CL16, CL17 for vendor recommended X01 C

14 17,25 USB 2010/01/27 DELL Delete eSATA function Delete eSATA function and follow NLM00 change sleep charge function to USB1 X01

15 26 EC 2010/01/27 ESD ESD request ADD CE25 location for ESD X01

16 26,27 LVDS 2010/01/27 DELL Add LCD panel feature Add CE_ENABLE and DBC_ENABLE X01

17 30 PWR 2010/01/27 Sourcer FDS8878/NTMS4107 will EOL Modify QZ3, QZ8 to NTMS4920NR2G X01

18 26 EC 2010/01/27 EC Change board version to 0.2(X01) POP RE1, RE7 UNPOP RE4 X01

19 18 HDA 2010/01/28 EMI Reserve SSIC for EMI concern Add US10, RS112, RS115, RS117, RS118, RS119 and CS81, CS82 X01
Prevent ACIN signal to drop down
20 18,26 ACIN 2010/02/02 HW from SB and EC code Add RE32, DE2 and QS2 X01
Reserve BT_RADIO_OFF# to ON/OFF
21 28 WLAN 2010/02/03 HW all BT function Add NET BT_RADIO_OFF# to control on/off BT function X01
Add 0 ohm to prevent different
22 27 LVDS 2010/02/04 HW PANEL spec. Reserve RV57, RV58 X01

23 13,30 Sequence 2010/02/05 HW Solve NB_PWRGD sequence issue POP RN29, RN33, QN1, QN2, and Change CZ21 to 2.2U, CZ8 to 0.01U X01
B B
24 23 PWR Rail 2010/03/17 HW Solve Sleeping charge issue Change +5V_ESAUSB to +USB_SIDE_PWR X02

25 27 New Panel 2010/03/17 SED Enable New Panel feature POP RV57, RV58 X02

26 30 PWR 2010/03/18 HW Change component for voltage issue Change CZ4, CZ19, CZ21 to 0.1U/25V, CZ8 to 0.01U/25V Change RZ21 to 470k OHM X02

27 26 EC 2010/03/23 EC For EC team common design Add RE33 and UNPOP X02

28 28 WLAN 2010/03/23 RF For RF team common design Add RM18 to disable BT,and support BT365 module, POP RM17 X02

29 31 PWR button 2010/03/25 ESD For ESD issue from power button Add CZ25, DZ4 X02

30 18,21 RF issue 2010/03/25 RF For RF issue Add CS22, RB8, CB12, Change RS119 to 33 OHM and Del RS118, RB3 X02

31 27 LVDS 2010/03/25 HW For reserve LVDS pannel sequence Add QV11, QV12, RV59, RV60, RV61 X02

32 28 WLAN 2010/03/25 RF Solve Athros B95 WLAN Card issue Change RM15 to 2k OHM X02

33 16,28 BT 2010/05/03 RF For RF team common design Add RM19, RM20, RS113 and UNPOP RM18, RM19, RS113 A00

34 18 SSIC 2010/05/11 RF For WWAN & NON-WWAN design Change SSIC BOM structure & CS22 to 8.2p for RF A00
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HW PIR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6132P
Date: Tuesday, May 11, 2010 Sheet 45 of 45
5 4 3 2 1
www.s-manuals.com