IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO.
5, SEPTEMBER 1997
Control Algorithms and Circuit Designs for
Optimal Flyback-Charging of an Energy-Storage
Capacitor (e.g., for Flash Lamp or Defibrillator)
Nathan O. Sokal, Life Fellow, IEEE, and Richard Redl, Senior Member, IEEE
Abstract— A flyback type of transformer-coupled dc/dc con-
verter supplies a train of current pulses to charge an energy-
storage capacitor to a desired high voltage, converting input dc
power obtained from a lower voltage dc source. The energy-
storage capacitor is charged to a specified voltage within a
specified time with minimum peak and rms currents in the
transistor, the rectifier diode, the transformer windings, and
the dc power source, minimizing the i2 R losses. This is done
by generating 1) energy-storage current pulses in the power
transistor and the transformer primary winding in which the
current increment from the beginning to the end of a pulse is only
a small fraction of the final (peak) value and 2) energy-delivery
flyback current pulses in the capacitor and the transformer
secondary winding in which the current decrement from the
beginning to the end of a pulse is only a small fraction of the initial
(peak) value. Recommended methods are: 1) hysteretic current-
mode control with current sensing in both transformer wind-
ings; 2) peak-current-commanding current-mode control with
switching frequency or transistor-nonconducting time varying
in a prescribed way during the charging; or 3) valley-current-
commanding current-mode control with switching frequency or
transistor-conducting time varying in a prescribed way during the
charging. Compared with one nonoptimal method, peak currents
are reduced by a factor of about 2 and i2 R power losses are
reduced by a factor of about 1.33.
Index Terms—Capacitor charger, capacitor charging, current-
mode control, defibrillator, energy-storage capacitor, feedfor-
ward control, flash, flyback charger, flyback charging, flyback
converter, high voltage, hysteretic current-mode control.
I. DEFINITION OF OPTIMAL FLYBACK-CHARGING
OF ENERGY-STORAGE CAPACITOR
A N ENERGY-storage capacitor (for example, for a flash-
lamp or defibrillator) is usually charged from near-zero
voltage to the desired final voltage in a flyback circuit like
that in Fig. 1.1 The transistor operates in the switching
mode. Fig. 2 shows the circuit voltage and current waveforms.
When the transistor turns off, the transformer current transfers
from the primary winding to the secondary winding, flowing
through the diode and charging the energy-storage capacitor
Manuscript received June 21, 1991; revised October 16, 1996. Recom-
mended by Associate Editor, R. L. Steigerwald.
N. O. Sokal is with Design Automation, Inc., Lexington, MA 02173-2404
USA.
R. Redl is with ELFI S. A., Onnens (FR), CH-1756 Switzerland.
Publisher Item Identifier S 0885-8993(97)06413-2.
1 If dc isolation between input and output is not required, the transformer
can be an autotransformer instead of having two isolated windings. That can
result in lower i2 R power losses in the windings.
0885–8993/97$10.00  1997 IEEE
885
. Usually, the capacitor is charged with a series of such
pulses. During any one pulse in the series, the rate of decay
of the charging-current pulse is proportional to the capacitor
voltage at that time during the charging process. Because the
capacitor voltage starts at near-zero voltage at the beginning
of the charging process and ends at the fully charged voltage,
the rate of decay of the capacitor-charging current pulses
varies over a wide range during the charging process. This
causes some difficulty for any charging method based on a
constant pulse frequency.2 The frequency should begin at a low
value and increase monotonically during the charging process.
Optimal flyback-charging [1] is defined as follows: a specified
capacitance is charged to a specified voltage within a specified
time, using a transistor with a specified peak-voltage capability
(or alternatively, using a specified dc supply voltage), with
the smallest possible peak and rms currents in the transistor,
the transformer primary and secondary windings, and the dc
power source. Minimizing the rms currents minimizes the
power losses in the circuit parasitic resistances. Minimizing
the peak currents minimizes the rms currents and the pulse-
current-carrying requirements of the transistor, transformer
(windings and core magnetization), rectifier diode, and capac-
2 For example, consider a constant-pulse-frequency charging of a capacitor
from 0 to 500 V via a diode whose conducting voltage is 1 V. Then the
voltage across the transformer secondary winding (the capacitor voltage plus
the diode conducting voltage) ranges from 1 V at the beginning to 501 V
at the end, a range of 501 : 1. Suppose that the transformer inductance is
chosen at a compromise value such that the secondary current falls to zero
during the flyback part of the period when the capacitor has been charged
halfway, i.e., when the transformer secondary voltage has built up to 251 V.
Near the end of the charging process, when the current falls almost twice
as fast, the current falls to zero by early in the second half of the flyback
interval; the circuit is idle during almost the entire second half of the flyback
interval. An idle condition wastes time. Near the beginning of the charging
process, when the transformer secondary voltage is nearly zero during the
flyback time, the secondary current remains almost constant during the flyback
interval. Then the primary current becomes larger on each successive pulse.
Unless the transistor minimum on time is an extremely small fraction of the
period, the transistor current probably will build up to a value that exceeds the
maximum allowed value. To protect the transistor, the designer must add an
over-current protector of the type that triggers a suspension of the transistor-
current pulses for a chosen “safe” interval that depends on the transistor
minimum on time (hiccup-type operation). The temporary suspension of the
transistor-current pulses effectively decreases the pulse frequency near the
beginning of the charging process. That results in a rough approximation to
the variable-frequency operation described in this paper, but the variation of
frequency during the charging does not follow the optimal pattern described
in this paper. The result of using fixed-frequency operation plus hiccup-mode
over-current protection is longer charging time and/or larger peak transistor
and diode currents, and the need to add the hiccup-type over-current protector,
increasing cost and component count.
886 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 5, SEPTEMBER 1997
Fig. 1. Circuit diagram.
itor, helping to reduce the cost and size of those components.
Compared with one nonoptimal method (in Section V-D), peak
currents are reduced by a factor of about 2 and power
losses are reduced by a factor of about 1.33. We derive the
required value of the peak current, give the control algorithm
for attaining the optimal charging process, show methods of
implementing the algorithm, and give experimental data that
verify the theoretical derivations.
II. SYMBOLS USED
Notation commonly used with bipolar junction transistors is
used here; the same analysis applies to MOSFET’s also. The
following symbols are used:
Transformer total primary inductance.
Transformer coupling coefficient (fraction of
primary-winding magnetic flux that links sec-
ondary winding).
Transformer leakage inductance, referred to pri-
mary.
Transformer inductance in parallel with ideal
transformer.
Transformer secondary/primary turns ratio.
Transformer primary-winding current.
Transformer secondary-winding current.
Transformer primary-winding (and transistor)
peak current.
Fraction of initial charging-current pulse to
which the charging current has decreased at the
time the off transistor is turned on.
Capacitor value.
Capacitor voltage during the charging process.
Required capacitor final voltage.
Total time allowed for charging capacitor from
zero voltage to . the fraction
Time required for charging process in the ab-
sence of delays caused by nonzero rise time of
capacitor-charging current pulses.
Time added to charging process by nonzero rise
time of capacitor-charging current pulses.
Clamped overshoot factor: the ratio of
the clamped voltage to the steady-state
value of in the off interval of the last
capacitor-charging pulse is
DC input voltage.
III. SINGLE-PULSE AND PULSE-TRAIN CHARGING METHODS
If the charging is done by one pulse, the control method is
to allow the transformer primary current to build up to a peak
value such that the energy stored in the coupled portion
of the primary inductance is equal to the energy to be stored
in the capacitor at the desired final voltage plus parasitic
power losses that are neglected here. Then
(1)
Solving (1) for the current required to charge the capacitor in
a single pulse yields
(2)
If these values of transistor peak current or transformer-
stored energy (hence, transformer volume) are too large, the
capacitor can be charged by a series of smaller-energy pulses,
each pulse delivering only a fraction of the total energy
to be stored in the capacitor. In that case, the transistor is
turned on for the amount of time needed for the transformer
primary current to build up to a chosen value described below.
When the transistor is turned off, current transfers from the
transformer primary winding to the secondary winding. The
secondary winding begins to deliver energy to the capacitor
that had been stored in the transformer inductance and
the current decreases, approximately linearly with time, to
of its initial value. When the transistor is
turned on again, current flow in the secondary ceases and that
winding ceases delivering energy to the capacitor. Because
the conducting transistor applies the dc-input voltage across
SOKAL AND REDL: CONTROL ALGORITHMS AND CIRCUIT DESIGNS FOR OPTIMAL FLYBACK-CHARGING
Fig. 2. Voltage and current waveforms.
the primary winding, the current in the transformer primary
winding increases linearly with time, starting at the fraction
of its former peak value. The interval of increasing primary
current prepares the circuit for the next transfer of energy to
the capacitor.
IV. QUESTIONS TO BE ANSWERED TO
DETERMINE OPTIMAL CHARGING METHOD
Turning-on the transistor terminates the delivery of energy
to the capacitor, so this might seem to be detrimental to
completing the charging of the capacitor within a specified
time. On the other hand, the longer the transistor is held off,
the longer it will take subsequently to replenish the energy
in the primary winding, in preparation for the next pulse
of delivering energy to the capacitor. This is because the
transistor initial current will be lower because the secondary
current will have declined further during the longer off interval
(the fraction will be smaller). This, too, could be detrimental
to completing the charging of the capacitor within the specified
time. Until the charging process is analyzed further, it is not yet
obvious which of these two opposing considerations dominates
in the charging process. The main questions to be answered
to determine the optimal method of charging follow.
• When should the transistor be turned on and off to charge
the capacitor to a required voltage within a required
time, while imposing the least possible current stress on
the transistor, the transformer primary winding, and the
dc-input power source?
• What is the best choice for the dc power supply voltage
, using a transistor with the capability to operate at
a given peak voltage ? flat-topped current pulse (of short duration) flowing into the
887
• Alternatively, what transistor peak-voltage capability is
required when using a given dc-supply voltage ?
• What is the best choice for the transformer turns ratio?
• What is the best choice for the transformer primary
inductance?
• What is the best choice for the overshoot-voltage param-
eter ?
V. OPTIMAL CHARGING METHOD
AND CHARGING-CONTROL METHODS
A. Optimal Times to Turn Transistor On and Off
The optimal charging strategy is determined later by analy-
sis. However, physical reasoning provides a qualitative result
directly: Fig. 2 shows the waveform of the capacitor-charging
current pulse (the secondary-winding current). Note that the
current decreases approximately linearly with time during the
pulse. The longer the pulse is allowed to continue, the lower
becomes its average current for a given peak value and a
given rms value. The charge delivered to the capacitor during
the pulse is directly proportional to the average value of
the current during the pulse. But the power dissipated in
the circuit’s parasitic resistances is proportional to the rms
value of the current during the pulse and the transistor and
diode costs increase with increasing peak current. Therefore,
the lowest peak and rms currents are desired for a given
value of average current. Those conditions are obtained by
charging the capacitor with current pulses whose tops droop
as little as possible; that is, the pulses are as nearly flat-
topped as possible. Therefore, the best strategy is to terminate
the secondary-winding current as soon as possible after it
begins (by turning-on the transistor again), resulting in a nearly
888 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 5, SEPTEMBER 1997
capacitor. Then allow the primary-winding current to build up
again to the chosen peak value and turn off the transistor to
begin another capacitor-charging current pulse. This strategy
leads to the use of short-duration capacitor-charging pulses,
interlaced with short-duration pulses of transistor conduction
to replenish the energy that had been delivered from the
transformer to the capacitor. The pulse-repetition frequency is
high because the pulses are short. A practical implementation
is to make the pulses as short as possible within the limitations
of the controller’s time delays, the power transistor’s current
rise and fall times, the effectiveness of the turn-on and turn-
off snubbers [2]–[5] that might be used in the power circuit,
the rectifier-diode forward and reverse recovery times, and the
frequency-dependent transformer losses.
The result of applying these considerations will be a nearly
flat-topped capacitor-charging current pulse. The current at the
end of the pulse will be the fraction of its initial value, where
is less than unity. The average/peak ratio of the current pulse
is slightly larger than . For example, a pulse that
ends with 80% of the initial current achieves slightly more
than 90% of the average/peak ratio that would, in principle,
be obtained from a circuit operating at infinite frequency with
zero-duration pulses. Thus, the optimal charging method is as
follows.
1) Turn-on the transistor for a time long enough to build up
the transformer primary-winding current to a peak value
, derived below and given in (20a) and (20b).3
2) Turn off the transistor for a time long enough for the
secondary-winding current to fall to a fraction of its
initial value of , where and are chosen
as described below. (The amount of time required for
the current to fall to the fraction of its initial value
decreases as the voltage on rises, pulse by pulse,
from zero to the final value. This is because in
the magnetizing inductance, proportional to the reflected
secondary voltage, is larger when the capacitor voltage
is larger. As a result, the transistor off-time decreases
and the switching frequency increases as the capacitor
charges.)
3) Turn on the transistor again.
4) The cycle is repeated until the capacitor reaches the
desired final voltage. After that, the transistor is held
off and the capacitor remains at the final voltage.4
The parameter should be as close to unity as possible,
consistent with other tradeoff factors involving the controller
3 After the capacitor is discharged by the load (for example, a gas-filled
flash lamp), it might be necessary to prevent the transistor from being turned
on again for the time needed for the load to return to its normal nonconducting
state (the state it normally is in during the capacitor charging), for example,
the time needed for the gas in a flash lamp to deionize. The time needed
for the transistor current to build up from zero to IP (pk) during the first
charging pulse is LIP (pk) =VCC . If that time is not long enough for the load
to return to its normal nonconducting state, a delay can be added between the
discharging of the capacitor and the beginning of the recharging process.
4 The capacitor voltage might decay slowly during the time that elapses until
the load discharges the capacitor because of leakage current in the capacitor,
the diode, or the load. If the decay can be appreciable, the controller can
be arranged to cause the power transistor to deliver a pulse of charge to
the capacitor to replace the charge lost by leakage after the capacitor-voltage
sensor has indicated that the voltage has decayed by a chosen amount.
response time and the power-stage dissipation that increases
with increasing switching frequency.
B. Optimal Charging When Can Vary
Equation (20b) shows that the optimal value of is
inversely proportional to the value of . In designing any
type of charger controller, the designer has the choice of
using a fixed value of that is sufficient for meeting
the charging-time requirement at the lowest value of or
of making be a decreasing function of . The result
of implementing the first choice is that the capacitor will be
charged within the required time when is at the minimum
value and will be charged more quickly than needed when
exceeds the minimum value. The penalty associated with the
faster-than-needed charging is that the power dissipation in
the circuit resistances will be larger than it would have been
if the value of had been reduced when exceeds
the minimum value, in accordance with the known need for
lower values of peak current. The result of implementing the
second choice will be a more-complex controller, but lower
power dissipation and higher efficiency when exceeds
the minimum value. The choice between those two alternatives
depends on the tradeoff factors that are applicable in a given
design project.
C. Control Methods for Optimal Charging
1) Hysteretic Current-Mode Control: The transistor is
turned off when the primary-winding current rises to the
peak value given in (20a) or (20b) and is turned on again
when the transformer secondary-winding current falls to the
fraction of its initial value. This is a form of hysteretic
current-mode control [6]–[8]. The currents can be sensed using
current-sensing resistors and/or current transformers and/or a
magnetic-field sensor (for example, a Hall-effect sensor) that
senses the magnetic field(s) produced by the currents.
2) Peak-Current-Commanding Current-Mode Control with
Feed-Forward-Controlled Off Time: In lieu of sensing the
transformer secondary current, the transistor is held off for a
time determined by sensing the capacitor voltage and using the
known relationship between the capacitor voltage and the time
required for the secondary current to fall to the fraction of its
initial value [derived in an Appendix (A.8)].5 This is a form of
constant-off-time current-mode control [6], [7] in which the off
time is controlled by a feedforward controller that implements
(A.8)5 : the input variable is the capacitor voltage; the output
variable is the duration of the off interval. (References [9]
and [10] give examples of feedforward controller designs for
other applications.)
3) Valley-Current-Commanding Current-Mode Control with
Feed-Forward-Controlled Transistor On Time: In lieu of sens-
ing the transformer primary current, the transistor is held
conducting for the time interval known to be needed to cause
5 The Appendix is not included here for lack of space. An earlier version
of this paper was printed: N. O. Sokal and R. Redl, Conf. Proc. APEC 90,
5th Annu. IEEE Applied Power Electron. Conf. Expo., Los Angelos, CA, Mar.
1990, pp. 295–302. An updated version of the Appendix is available upon
request from either author.
SOKAL AND REDL: CONTROL ALGORITHMS AND CIRCUIT DESIGNS FOR OPTIMAL FLYBACK-CHARGING 889

the current to rise from to

(3)

The off-time is determined by sensing the transformer sec-

ondary current and terminating the off-interval when that
current has fallen to a chosen value—nominally, times
its initial value. This is a form of constant-on-time current-
mode control [6], [7] in which the on time is controlled by
a feedforward controller that implements (3), responsive to
the actual value of (not necessarily equal to the nominal
value). In this feedforward controller, the input variable is the
dc supply voltage; the output variable is the duration of the
on interval.
4) Valley-Current-Commanding Current-Mode Control with
Fixed Transistor On Time: In lieu of sensing the transformer
primary current, the transistor is held on for a fixed length
of time, chosen as an approximation to the actual required
value that varies with the dc supply voltage, for causing the
primary current to rise from to , given in (3)
and derived in the Appendix.
The off time is determined by sensing the transformer
secondary current and terminating the off interval when that
current has fallen to a chosen value—nominally, times its
initial value. This is a form of constant-on-time current-mode
control [6], [7] in which the on time is fixed at a compromise
value that is suitable for a chosen set of values of
and .
5) Unfeasibility of Feedforward Control of Both On and
Off Intervals without Current Sensing: The transistor on and
off intervals cannot both be controlled by feedforward, as
described above, separately for the peak-current-commanding
and valley-current-commanding control methods. Any inac-
curacy in implementing either of the feedforward controls Fig. 3. Variation of design parameters with k for k between 0.900–0.998.
could cause the increase of transformer primary current in
each on interval to exceed (or be smaller than) times
E. Termination of the Charging Process
the decrease of the transformer secondary current in the
immediately preceding off interval. Then the peak primary The charging process is terminated by inhibiting the transis-
current would increase (or decrease) in each cycle, potentially tor turn-on if the capacitor voltage is equal to or greater than
resulting in circuit destruction at excessively high current or the desired final value less the small voltage increase
malfunction at excessively low current. that is caused by delivering to the capacitor the last packet of
energy .
D. Comparison of Optimal Charging Method
with Nonoptimal Charging Method
One could use a method similar to the optimal method VI. OPTIMAL POWER-STAGE DESIGN
described above, but wait to turn on the power transistor until
the secondary current falls to zero; that is, is chosen as A. Choice of Transformer Coupling Coefficient
zero. This could be done to avoid the need for the transistor
to supply reverse turn-off current for the diode. However, it The transformer should be designed so that the coupling
nearly doubles the required peak current, increasing it by a coefficient is as close to unity as possible (or economical)
factor of as compared to the optimal method described because nonunity coupling has only undesirable effects. Fig. 3
above. The rms currents increase by slightly less than a factor shows the influence of on
of and the power losses (in the transistor, the and in an example design, for in the range of
transformer windings, the diode, the ESR of the energy-storage 0.900–0.998. Although high is desirable, Fig. 3 illustrates the
capacitor, and the resistance of the dc supply and/or its fairly low sensitivities of the design parameters to deviations
bypass capacitor) increase by a factor of almost 4/3. of from the ideal value of unity.
890 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 5, SEPTEMBER 1997

B. Choice of Overshoot Factor number of pulses in the charging process. That average is
A value of less than unity results in a nonzero leak-
age inductance . The leakage inductance causes
a collector-voltage spike at transistor turn-off. The turn-off
snubber and/or clamp circuit constrains the collector voltage
to a peak value of , chosen to be safely below the
maximum rated or . (Those voltage ratings (7)
apply, instead of , if the collector-voltage waveform
is snubbed sufficiently by the turn-off snubber. A dissipative The number of pulses in the charging process is the final
[2] or nondissipative [3], [4] snubber can be used.) The voltage capacitor energy divided by the energy transferred during each
clamp can be dissipative [11], [12] or can be of a type that pulse
returns the clamped energy to a power supply. The peak
collector voltage must be larger than the highest collector
voltage that appears during diode conduction on the last pulse (8)
(when the voltage reflected from the charged capacitor to the
collector is largest) by the factor ; that is
Hence, , the increase of capacitor-charging time attributed
(4) to the nonzero secondary-current rise time, is obtained by
multiplying (7) by (8)
From (4), the overshoot-voltage parameter is

(5)

must be greater than zero to allow the current in the

transformer leakage inductance to decay after the transistor
is turned off and, hence, to allow current to transfer from (9)
the primary to the secondary of the transformer. Increasing
decreases the duration of the overshoot spike (coincident The time for the charging process , derived in the
with the transfer of transformer current from the primary Appendix, must be less than the specified final time
to the secondary, where it charges ); the duration of that by the amount given in (9) above.
spike is part of the transistor off interval. The choice of is The choice of depends on the value of achieved in
influenced by the value of the primary-to-secondary coupling the transformer design. If is unity, is zero, and can
coefficient achieved in the transformer design. Together, be chosen as zero. Given a nonunity value of , must be
and determine the rise time of the secondary-current nonzero and is nonzero and a function of the value chosen
pulse (approximately equal to the fall time of the primary- for : the larger the value of , the smaller the resulting
current pulse because, in principle, the secondary current . The smaller permits a larger value of and, hence,
rises from zero to its peak value during the time that the a smaller value of . However, the larger value of
primary current is falling from its peak value to zero). less requires a larger value of for a given set of the other
than unity and the corresponding nonzero leakage inductance parameters. That increases the value of . The optimal
contribute to making the secondary-current rise time longer combination of and (or alternatively
than the primary-current fall time. The rise time is slowed minimizes for a given (or alternatively
also by parasitic capacitance and the turn-off snubber if one and .
is used. The capacitor charging is effectively delayed by half
of the secondary-current rise time (hence, half of the primary- C. Required Peak Current in Transistor
current fall time, not accounting for the other contributors). and Transformer Primary Winding
The accumulation of the delay times during all of the pulses of
The required peak current in the transistor and the trans-
the charging process adds a total delay of to the capacitor-
former primary winding is
charging time . (The sum of and is the time to
finish charging the capacitor.) The primary-current fall time
is determined by and and it increases from pulse to
pulse during the charging process, as increases from its
initial value of zero to its final value of . Half of the (10)
primary-current fall time is
The Appendix gives the derivation, ending at (A.11). (Note
(6) that the time in (10) is , which is less than the final charging
time by the amount , which is the time occupied by the
The total delay can be approximated as the average of the nonzero rise times of the current pulses, caused by the nonzero
longest and shortest charging-pulse delays, multiplied by the transformer leakage inductance.)
SOKAL AND REDL: CONTROL ALGORITHMS AND CIRCUIT DESIGNS FOR OPTIMAL FLYBACK-CHARGING 891

Fig. 4. Experimental circuit.

D. Choice of
The durations of the transistor on and off intervals are
directly proportional to . To maintain high efficiency and
to avoid undue dependence of performance on the transistor
switching times, should be chosen to yield transistor on and
off intervals [ in (A.7) and in (A.8)] that are much
larger than the transistor switching times, for example, of the
order of 100 or more times the transistor current rise and fall
times. The required value of is the larger of (11) or (12)

(11)

(12)

Fig. 5. Capacitor voltage versus time during charging. Vertical: 50 V/div.

E. Choice of and Horizontal: 10 s/div.

and are constrained jointly by (4).

Given a value for of them, optimal values can be chosen choice of and . Alternatively, given and the
for the other of them. The expression for is, from first five parameters, we can minimize by optimal
(4) choice of and . A third alternative: given the seven
parameters other than , find the value of that minimizes
(13) . Substituting that into (13) yields the optimum value
of .
For this purpose, we set to zero the partial derivative(s)
Substituting (13) into (10) for yields an expression for of with respect to the parameter(s) that are being
in terms of and But optimized and solve for the optimum values of those
parameter(s). These, in turn, give and .
(14)
Because and are linearly related by a
where is given by (9). Accordingly, can be ex- constant [given in (15) below] that is independent of
pressed in terms of and the variables and the partial derivatives
by substituting (13) into (9), inserting the result into (14), and the solutions for the optimal parameter values can be
inserting that into (10), and solving for . Given the derived in the form of “given , find the optimal
first six parameters, we can minimize by optimal ” and the solutions can be recast in the form of “given
892 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 5, SEPTEMBER 1997

(a)

(a)

(b)
Fig. 7. Combined primary and secondary currents versus time for (a) first
three pulses and (b) last three pulses. Vertical: 0.227 A/div. Horizontal: (a)
10 s/div. (b) 5 s/div.

(b)
if is specified.
Fig. 6. Transistor drain voltage versus time for (a) first three pulses and (b)
last three pulses. Vertical: 20 V/div. Horizontal: (a) 10 s/div. (b) 5 s/div. (18b)

, find for the optimal design,” substituting

if is specified, or (19a)
the derived linear relationship (18) between the values
of and in the optimal circuit. For analysis,
let

if is specified. (19b)
(15)

if is specified, or (20a)
(16)

(As and both approach the ideal values of 1, approaches

and approaches infinity.) Setting the partial derivatives if is specified (20b)
to zero and solving for the optimal parameter values, we
F. Choice of and When
obtain Can Vary Over a Specified Range
(17) In some applications, it might be necessary to choose
values for and for a circuit to operate over
a specified range of . If and are fixed (that is, are
if is specified, or
not changed as changes), the chosen combination can
(18a) be the optimum (as derived above) at only one chosen value
SOKAL AND REDL: CONTROL ALGORITHMS AND CIRCUIT DESIGNS FOR OPTIMAL FLYBACK-CHARGING 893

TABLE I
DESIGN PARAMETERS AND CALCULATED AND MEASURED Tf

of . At other values of , the performance will be dissipation, at the cost of all power dissipations increasing
suboptimal as compared with what could be obtained with a by a factor of almost 4/3.
set of parameter values chosen to be optimal at the specific
other value of . For this type of application, the designer
would usually follow a design procedure similar to that shown VII. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS
below. The capacitor charger of Fig. 4 (using hysteretic current-
1) Choose from (17), not a function of . mode control) was designed, built, and tested. The experi-
2) Choose from (19b), using the minimum value of . mental and theoretical results are compared in Table I, which
3) Choose from (20b), using again the minimum shows the design parameters and the calculated and measured
value of . Implicitly contained in (20b) is the as- values of (the time to attain the final capacitor voltage).
sumption that the transformer will have calculated The measured time was within 2% of the calculated value,
from (19b) using the same value of as will be used verifying the accuracy of the equations given here. Figs. 5–7
in (20b) to calculate . That assumption is met show measured waveforms in the circuit of Fig. 4. (The
in this procedure. waveforms were photographed using a version of the circuit
4) Determine the required transistor capability that had slightly different design parameters than the ones
from (4), using the already-determined values of and shown in Fig. 4 and Table I, so the waveform voltages and
and the maximum value of . times do not correspond exactly with the values in Table I.)
This circuit will be the optimum at the minimum value of The waveforms confirm the theory given in this paper.
and suboptimal at higher voltages. If the optimal value
of were used at each higher value of , the needed value ACKNOWLEDGMENT
of would be inversely proportional to . But since
The authors would like to thank Prof. A. D. Sokal of the
will be fixed, the ratio of will not be increasing
Department of Physics, New York University, New York,
in proportion to . Therefore, the value of cannot be
NY, who pointed out the physical and mathematical basis of
reduced inversely with increasing as might be supposed
optimal control of capacitor charging. They would also like to
from a casual inspection of (20b).
thank their colleague R. P. Sallen, who derived the expressions
for the optimum parameter values, and their colleague L.
G. Overall Optimization Balogh, who designed, built, and tested the example circuit
This paper deals primarily with minimizing the conduction of Section VII.
losses (which frequently are the major losses in the circuit)
by making as close to unity as feasible. If the transformer
losses and volume are too large, a smaller value of can IX. LEGAL NOTICE
reduce the needed transformer inductance and, hence, reduce The technology described here is protected by U.S. Patent
the transformer losses and volume at the expense of increasing 5 485 361. Contact author N. O. Sokal to obtain a no-cost
other conduction losses. As mentioned in Section V-D, setting license to build one experimental unit for evaluation only and
to zero can eliminate 1) the need for the transistor to supply to obtain a reasonable-cost license to make, use, or sell more
turn-off current to the diode and 2) the associated power than one unit.
894 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 5, SEPTEMBER 1997
REFERENCES
[1] N. O. Sokal, Flyback Charging with Current Mode Controlled Flyback
Converter, U.S. Patent 5 485 361, Jan. 16, 1996.
[2] M. Domb and N. O. Sokal, “R-C-diode turn-off snubber: Peak VCE ,
snubber and transistor power dissipation, and optimum design, for use in
transformer-coupled power converters having nonnegligible transformer
leakage inductance,” Power Conversion Intell. Motion, vol. 11, no. 9,
pp. 34, 36, 38, Oct. 1985.
[3] M. Domb, R. Redl, and N. O. Sokal, “Nondissipative turn-off snubber
alleviates switching power dissipation, second-breakdown stress, and
VCE overshoot: Analysis, design procedure, and experimental verifi-
cation,” in PESC Rec., IEEE Catalog no. 82CH-1762-4, pp. 445–454,
1982.
[4] A. Ferraro, “An overview of low-loss snubber technology for transis-
tor converters,” in PESC Rec., IEEE Catalog no. 82CH-1762-4, pp.
466–477, 1982.
[5] G. Spiazzi, L. Rossetto, and P. Mattavelli, “Design optimization of soft-
switched insulated dc/dc converters with active voltage clamp,” in Proc.
IEEE Ind. Applicat. Soc. Annu. Meet., vol. 2, San Diego, CA, Oct. 1996,
pp. 1169–1176.
[6] R. Redl and N. O. Sokal, “Current-mode control, five different types,
used with the three basic classes of power converters: Small-signal
ac and large-signal dc characterization, stability requirements, and
implementation of practical circuits,” in PESC Rec., IEEE Catalog no.
85CH-2117-0, pp. 771–785, 1985.
[7] , “What a design engineer should know about current-mode
control,” in Proc. Power Electron. Design Conf., Anaheim, CA, Oct.
1985, pp. 18–33.
[8] T. A. Froeschle, Current Controlled Two-State Modulation, U.S. Patent
4 456 872, June 26, 1984.
[9] N. O. Sokal, “Feed-forward control for switching-mode power convert-
ers—A design example,” in Proc. POWERCON 3 Conf., Beverly Hills,
CA, June 1976, pp. E2-1–E2-11.
[10] R. Redl and N. O. Sokal, “Frequency stabilization and synchronization
of free-running current-mode-controlled converters,” in PESC Rec.,
IEEE Catalog no. 86CH2310-1, pp. 519–530, 1986.
[11] M. Domb and N. O. Sokal, “Zener or extra winding copes with leakage
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[12] S. Clemente, B. Pelly, and R. Ruttonsha, “A universal 100 kHz power
supply using a single HEXFET,” Int. Rectifier Applicat. Note AN -939A
in HEXFET Designer’s Manual, Volume 1, HDM-1, El Segundo, CA,
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Nathan O. Sokal (S’50–A’51–M’56–SM’56–F’89–
LF’94) received the B.S. and M.S. degrees in elec-
trical engineering from the Massachusetts Institute
of Technology, Cambridge, MA, both in 1950.
From 1950 to 1965, he held engineering and
supervisory positions with Holmes and Narver, Inc.,
M. I. T. Lincoln Laboratory, Mack Electronics Di-
vision of Mack Trucks, Inc., Di/An Controls, Inc.,
and Sylvania Electronic Systems Division. He was
involved with design, manufacturing, and field in-
stallation and operation of a wide variety of analog
and digital equipment for instrumentation, control, communication, computa-
tion, and signal and data processing. In 1965, he founded Design Automation,
Inc., Lexington, MA, an electronics consulting company. There, he has been
involved with design review and product design of a wide variety of electronic
equipment, mostly for equipment-manufacturing clients. Much of that work
has been in high-efficiency switching-mode power conversion and power
amplification at frequencies up to 2.5 GHz. He is a Technical Adviser to
the American Radio Relay League on RF power amplification and dc power
conversion. He has published or presented more than 100 technical papers
and is a Coauthor of a book on dynamic analysis of switching-mode power
converters.
Mr. Sokal is a Member of Eta Kappa Nu and Sigma Xi honorary profes-
sional societies.
Richard Redl (M’86–SM’86) received the Diploma
degree (telecommunications engineering), in 1969,
and the Technical Doctor degree, in 1973, both from
the Technical University of Budapest, Hungary.
From 1969 to 1984, he worked at the Technical
University of Budapest as a Research Associate and
an Assistant Professor, developing power supplies
for earth satellites and industrial equipment and
teaching courses in electronics and power electron-
ics. From 1984 to 1989, he was a consultant in
the United States, doing design review and product
design of power-electronics equipment for equipment-manufacturing clients
and development of new technology for power electronics. Since 1990, he
has been the director of ELFI S.A., Onnens, (FR), Switzerland, continuing
with the same kind of work. He holds three Hungarian and eight U.S. patents,
with three more U.S. patents pending. He has published more than 80 technical
papers. He is a Coauthor of a book on dynamic analysis of power converters.