NAME: HWACHA TADIWA

REG NUMBER R188193Y

TITLE SEQUENTIAL LOGIC DESIGN

PARTNERS NAME TAPIWA MAKUVAZA

DATE OF PRACTICAL 2/10/2019

OBJECTIVES
a)T o learn how basic sequential logic circuits work.
b) To study the behavior and applications of flip flops and basic sequential circuits including
shift registers and counters.

INTRODUCTION
Output of a sequential logic circuit depends not only on the current value of the input but also
upon the internal state of the circuit. Flip –flops are the basic building blocks of a sequential
circuit. A memory stores data usually one bit per element, a one bit memory is called a bitable,
and it has two internal states. Flip-flops have 2 outputs and they are called state variables.
S-R Latch
When the other output is high the other is high and the opposite is true.
Clocked( Enabled )S-R Flip-Flop
It has an additional clock input so that S an R inputs are active only when the clack is high
.When clock goes low , the state of flip flop is latched and cannot change until the clock goes
high again.
JK Flip flops
If outputs are unpredictable and if there is a race condition a modification of the SR flip flop is
made to make sure 1s are not applied to both inputs simultaneously as in fig 6.
Shift Registers
Is used for storage or transfer of binary data. A shift register consist of a chain of flip flops
connected together with the output of one flip-flop connected to the input of the next. They all
receive a common clock pulse which causes the shift from one stage to the next. It consist of
several bit ‘D-Type Data Latches ‘. They are classified into 3 basic considerations their method
of data handling ( serial-in serial-out , serial-in parallel –out, and parallel-in serial-out), their
direction of data movement and their bit length.
Counters
It is a circuit that goes through prescribed sequence of states upon the application of input
pulses .A counter that goes through 2N states is called a binary counter. There are two
categories if counters which are ; asynchronous and synchronous counters.
Asynchronous counters
pulse L1 L2 L3 L4

0 1 1 1 1

1 0 1 1 1

2 1 0 1 1

3 0 0 1 1

4 1 1 0 1

5 0 1 0 1
6 1 0 0 1

7 0 0 0 1

8 1 1 1 0

9 0 1 1 0

10 1 0 1 0

11 0 0 1 0

12 1 1 0 0

13 0 1 0 0

14 1 0 0 0

15 0 0 0 0

16 1 1 1 1

The time diagram

They are arranged so that the output of one flip-flop generates the clock input of the next higher
stage . They can also be called ripple counters. The clock inputs are triggered by the transition
that occurs not by the incoming pulses.
Synchronous Counters
They eliminate the cumulative flip-flop delay seen in ripple counter, each flip-flop is clacked by
the same clock signal.

Ck L4 L3 L2 L1

0 0 0 0 0

1 0 0 0 1
2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

16 0 0 0 0
EQUIPMENT
 Electronics project board
 Sequential logic tutor
 Sn74LS00 Quad 2-input NAND gate
 Sn74LS02 Quad 2-input NOR gate
 Sn74LS76 Dual JK Master-slave flip flop
 74LS11- Triple 3-input AND gate
 LEDs and limiting resistors

PROCEDURE
4.1 S-R latches were constructed as in fig 1 and fig 2 using 7402 TTL and 7400 TTL
packages .
4.1.2 LEDs and switches were used to verify their functions and results recorded on a truth
table.
4.2 a circuit as in fig 4 was constructed using 7400 TTL PACKAGE

4.2.2 Switches and Leeds were used to configure the function of the circuit and a truth table
was written for the results.

4.3.1
 • 4.4Connect as shown in fig 4 and 5 below and record the results in table 4 and 5

Fig 4
Table 4
J K Ǭ Q

0 0 An

0 1 1 0

0 0 1 0

1 0 0 1

0 0 0 1

1 1 Toggle

THE 74LS11 WASN'T AVALIBLE IN THE LAB

C) By connecting the Inverter at the J and K inputs forming the D type flip flop the outcome is as follows
J K Ǭ Q
0 1 1 0
1 0 0 1
D) Connect the inputs together and verify the operation of the T flip flop

J K Ǭ Q

0 0 An

0 1 1 0

1 0 0 1

1 1 Toggle
Connect the circuit as shown below and take note of how it functions when clear is logic 0 and
1 and SW1 when its logic 1 or 0

Table of results
J K Q1 Q2 Q3 Q4
0 1 1 1 1 1
0 1 0 1 1 1
0 1 0 0 1 1
0 1 0 0 0 1
1 0 0 0 0 0
1 0 1 0 0 0
1 0 1 1 0 0
1 0 1 1 1 0

RESULTS
( ACTIVE LOW INPUT SR) NAND GATES
S’ R’ Q Q’
0 0 1 1 Invalid condition
0 1 1 0 Latch set
1 0 0 1 Latch reset
1 1 ? ? No change

ACTIVE HIGH S-R

S R Q Q’
1 0 0 1
0 1 0 1
1 0 1 0
1 1

CLOCKED S-R FLIP FLOP

S R CLK Q Q’
0 0 1 1 0
0 1 1 0 1
1 0 1 1 0
1 1 1 1 1

JK FF WITH NOR GATES

J K Q Q’
0 0 0 1
0 1 0 1
1 0 1 0
1 1 1 0
RIPPLE COUNTER
L1 L2 L3 L4
0 0 0 0
1 0 0 0
0 1 0 0
1 1 0 0
0 0 1 0
1 0 1 0
0 1 1 0
1 1 1 0
0 0 0 1
1 0 0 1
0 1 0 1
1 1 0 1
0 0 1 1
1 0 1 1
0 1 1 1
1 1 1 1

L1 L2 L3 L4
1 1 1 1
0 1 1 1
1 0 1 1
0 0 1 1
1 1 0 1
0 1 0 1
1 0 0 1
0 0 0 1
1 1 1 0
0 1 1 0
1 0 1 0
0 0 1 0
1 1 0 0
0 1 0 0
1 0 0 0
0 0 0 0
DISCUSSION
THE JK flip flop operated as a T flip flop .From the experimental results it is clear that the RS
latch is obtained by implementing a series of gate controls and they all lead to the formation of
the JK flip flop. When the Joke flip flop was used instead of the SR flip-flop this eliminated the
race condition and the unpredictable outputs. Counters are then grouped into asynchronous were the
output of other flip flop is used to clock the next flip flop and the synchronous is where the both flip
flops are clocked with the same pulse. Synchronous counters are faster as the propagation delay is
smaller as compared to asynchronous counters. There are no counting errors also. The disadvantages of
asynchronous counter are extra “re-synchronizing” output flip-flop may be required, to count a
truncated sequence not equal to 2 n, extra feedback logic is required and counting a large number of bits,
propagation delay by successive stages may become undesirably large.

CONCLUSION
In asynchronous counters the output of one flip flop is used to clock the next flip flop and in
synchronous counters all flip flops are clocked with one pulse. The modulo of a counter is determined
when the circuit goes back to its initial state. Therefore modulo of a counter differs with the circuit that
is mounted.

REFERENCES
Digital Fundamentals ,T.L.Floyd,Nineth Edition.