2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

Low-temperature multichip-to-wafer 3D integration

based on via-last TSV with OER-TEOS-CVD and
microbump bonding without solder extrusion
Kousei Kumahara Rui Liang Sungho Lee Yuki Miwa
Graduate School of Biomedical Graduate School of Biomedical Graduate School of Engineering Graduate School of Biomedical
Engineering Engineering Tohoku University Engineering
Tohoku University Tohoku University Sendai, Japan Tohoku University
Sendai, Japan Sendai, Japan s-lee@lbc.mech.tohoku.ac.jp Sendai, Japan
kumahara@lbc.mech.tohoku.ac.jp liangrui@lbc.mech.tohoku.ac.jp miwa@lbc.mech.tohoku.ac.jp

Mariappan Murugesan Hisashi Kino Takafumi Fukushima Tetsu Tanaka

Global INTegration Initiative
(GINTI), New Industry Creation
Hatchery Center (NICHe)
Tohoku University
Sendai, Japan
murugesh@bmi.niche.tohoku.ac.jp
Frontier Research Institute for
Interdisciplinary Sciences(FRIS)
Tohoku University
Sendai, Japan
kino@lbc.mech.tohoku.ac.jp
Graduate School of Engineering /
Graduate School of Biomedical
Engineering / GINTI, NICHe,
Tohoku University
Sendai, Japan
fukushima@lbc.mech.tohoku.ac.jp
Graduate School of Biomedical
Engineering, and Graduate
School of Engineering
Tohoku University
Sendai, Japan
ttanaka@lbc.mech.tohoku.ac.jp

Abstract— 7KLVpaper deals with multichip-to-wafer (MC2W)
3D stacking technologies based on via-last TSV integration. In this
work, we verify the effectiveness of room-temperature CVD
named OER (Ozone-Ethylene Radical generation)-TEOS-CVD®
to deposit a TSV liner SiO2 layer. The film quality including
dielectric constants is evaluated alternative to plasma-enhanced
(PE)-TEOS-CVD SiO2. In addition, solid-solid inter-diffusion
bonding of 3-μm-thick Sn with 0.5-μm-thick Au is demonstrated
to achieve multiple multichip bonding for retinal prosthesis system
fabrication with a 3D artificial retina chip. Low-temperature
bonding at 190°C is realized by the Au/Sn metallurgy. Good
bondability is also obtained with the Au electrodes preliminarily
exposed at high temperature. There are no Sn microbump
extrusion, which is highly expected to be used for 3D-ICs with fine-
pitch solder microbump interconnection.
Keywords—Multichip-to-wafer 3D integration, TSV, Room-
temperature CVD, via-last TSV, Low-temperature bonding,
I. INTRODUCTION
We have proposed and developed MC2W 3D integration
including reconfigured-wafer-to-wafer 3D integration in which
large numbers of known good dies (KGDs) can be precisely and
simultaneously stacked by capillary self-assembly with liquid
droplets [1]-[10]. The MC2W stacking methodology can satisfy
both throughput and yield requirements, compared with chip-to-
chip, wafer-to-wafer, and chip-to-wafer 3D stacking. On the
other hand, TSVs are typically fabricated based on via-middle
and via-last approaches respectively for HBM and CIS
applications. These TSVs are formed at a temperature beyond
300°C because these TSV processes, DRIE/CVD/PVD/plating,
utilize no thermally unstable adhesives for temporary bonding
on support wafers [11], [12]. Our 3D/TSV project is focusing on
multichip-level 3D stacking with incoming 2D KGDs
manufactured in foundry shuttle services. The thick 2D KGDs
have no TSVs. To achieve this 3D integration strategy, we
employ MC2W stacking based on via-last TSV as shown in Fig.
1.
However, the MC2W 3D integration with via-last TSV
processes has several thermal issues in TSV liner dielectric
deposition and thermal compression chip bonding through
solder microbumps at elevated temperatures. These
conventional high-temperature processes cause viscoelasticity
changes of the temporary adhesives to give chip drift, chip/wafer
bow, delamination, and micro-void/crack/chipping generation
to mechanically thinned KGDs. Therefore, low-temperature
TSV line dielectrics with high quality are required [13], [14].
Finally, these defects further induce serious electrical
characteristics deterioration due to their bonding failures
resulted from chip misalignment and oxidization of exposed
solder microbumps in the 2nd and 3rd step bonding as shown in
Fig. 1. In this paper, we employ room-temperature SiO2-CVD
with highly pure O3 and C2H4, called OER-TEOS-CVD®, for
TSV liner formation. In addition, we demonstrate solid-solid
inter-diffusion microbump bonding compatible with the
multiple multichip bonding scheme at below 200°C with
electroplated Sn and sputtered Au without solder extrusion.
Conventional solid-liquid inter-diffusion (SLID) or liquid-liquid
Sn-Sn bonding could be squeezed and leads to an electrical short
between adjacent bumps in a narrow pitch, as previously
reported by Zhang et al. [15].

2377-5726/20/$31.00 ©2020 IEEE 1199

DOI 10.1109/ECTC32862.2020.00192

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 1. Self-assembly (Face-up) 2. Temporally bonding chip 3. Debonding supporting wafer A 4. Multichip thinning
Microbumps
Supporting Wafer A
KGD KGD Liquid Temporal
adhesive
Supporting Wafer A Supporting Wafer B Supporting Wafer B Supporting Wafer B

5. Forming via-last TSVs and microbumps 6. Microbump bonding (1st bonding) 7. Debonding supporting wafer B 8. Microbump bonding (2nd bonding)
Supporting Wafer C

Microbumps Supporting Wafer B

TSVs
TSV TSV TSV
Supporting Wafer B Interposer Wafer Interposer Wafer Interposer Wafer

9. Debonding supporting wafer C 10. Microbump bonding (3rd Bonding) 11. Debonding supporting wafer D 12. Heterogeneous 3D integration
Supporting Wafer D

TSV TSV TSV TSV

Interposer Wafer Interposer Wafer Interposer Wafer Interposer Wafer

Fig. 1. Process flow of MC2W 3D integration with multiple multichip bonding.

1. TSV fabrication 2. SiO2 deposition 3. Barrier/seed layers

by Bosch process by using OER-TEOS-CVD@ deposition
p
•Room temperature
Cu
II. EXPERIMENTS Via holes SiO
O2 •150℃ Ti

A. OER-TEOS-CVD®
As shown in Fig. 2, MIS trench capacitors with Cu-TSVs
were fabricated by Bosch etch and the subsequent OER-TEOS-
CVD® at r.t. or 150°C, followed by Ti/Cu PVD, conformal Cu
electro-less plating, and bottom-up Cu electroplating.
Conventional PE-TEOS-CVD at 200°C was also used as a TSV
liner formation for comparison. These trench capacitors were
used for measuring the leak current through the OER-TEOS-
CVD® SiO2. The cross-sectional images of the TSVs were
observed with SEM for evaluating the step coverage of the SiO2
liner. The step coverages were defined by the following
formula:
Step coverage[%] =
where Tsidewall and Tsurface are defined as the thicknesses of the
sidewall at the top, middle, bottom and via bottom and surface
of the SiO2, respectively.
A simple annealing process is performed after the debonding
of their support wafers to enhance the SiO2 film quality. In this
study, we evaluated the annealing effect on the dielectric
constant of the SiO2 deposited by OER-TEOS-CVD® with MIS
planar capacitors. The annealing conditions were under a N2
atmosphere at 200°C or 300°C for 1 hour. After that, we
characterized their k values from the accumulation capacitance
(Cox) of the planar capacitors. The capacitances at 1 MHz were
measured ranging in bias voltage from -5 V to 5 V. According
to the C-V curves of the planar capacitors, the k value was
calculated by
∙ without the pre-heating exposure step.
= (2)
∙
where ε0, d, and A were defined as permittivity under a vacuum,
insulator thickness measured with an ellipsometer, and
capacitor area [16].
4. Bottom-up fill of Cu 5. Pad formation
by electroplating by wet etching
Fig. 2. Process flow of TSV-structured MIS capacitors.
B. Solid-solid inter-diffusion Sn-Au microbump bonding
As shown in Fig. 3, Ti/Al/Ti (t: 30/500/30 nm) was used as
daisy chain wirings for top and bottom chips. In the top chip
(1) fabrication, low-height solder microbumps composed of Cu and
Sn with a thickness of 3 μm and 2 μm were formed by
electroplating. On the other hand, in the bottom chip fabrication,
Cu/Ni/Au (t: 0.5/0.2/0.2 μm) was fabricated as host electrodes
by a lift-off process with sputtering. The top and bottom chips
were bonded with a flip-chip bonder FC3000W (Toray
Engineering) at a temperature of 150-250°C for the top bonding
head and 250°C for the bottom wafer stage. The bonding
pressure was set at 30 MPa. Furthermore, to evaluate the
stability against oxidation of the host electrodes in this MC2W
3D integration with multiple multichip bonding, a highly
accelerated exposure test was conducted. Here, the bottom chips
were pre-heated on a hot plate at 250°C for 30 min to expose the
host electrodes to heat in air, and then, the corresponding top
chips having Cu/Sn microbumps were bonded to the bottom
chips. Finally, the electrical properties using Cu/Sn-Cu/Ni/Au
daisy chains were compared between the processes with and
Furthermore, to evaluate the stability against oxidation of
the host electrodes in this MC2W 3D integration with multiple
multichip bonding, a highly accelerated exposure test was
conducted. the bottom chips were pre-heated on a hot plate at
250°C for various time to expose the host electrodes to heat in
air, and then, the corresponding top chips having Cu/Sn
microbumps were bonded to the bottom chips at the 2nd

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multichip bonding step. Finally, the electrical properties using k values resulted from OER-TEOS-CVD® are relatively higher
Cu/Sn-Cu/Ni/Au daisy chains were compared between the than that of PE-TEOS-CVD. In order to further lower the k
processes with and without the pre-heating exposure. values, additional annealing is an effective technique to purify
the SiO2 by removing polar moieties. After annealing, the k
values 5.5 of the SiO2 formed at r.t. decreases down to 4.8. It is
1. SiO2 deposition 2. Ti/Al/Ti sputtering 3. Ti/Al/Ti etching
Al (300 nm) Ti (50 nm)
(wiring patterning) also found that we can finally diminish the k-value down to 4.5
SiO
O2 (1μm) or less by annealing at 300°C after the final debonding of
Si (280μm) support wafers and thermally unstable temporary adhesives.
These low dielectric constants would be applicable to 3D-ICs
4. Cu/Sn bump formation (Top chip)
4-1. Barrier/seed layers sputtering 4-2. Electroplating Cu/Sn and
with TSVs.
removing barrier/seed
er/seed layers
d layyyerss
Sn (2 μm)
μmm
Cu (100 nm) Ti (20 nm) Cu(3
Cu(((3
3μ μm
μm)
m
m)

6. Microbump bonding
(a) 10 μm
0°C, 250
150
50° 0 °C
50°

1 μm
5. Cu/Ni/Au bump formation (Bottom wafer)
5-1.
-1. Cu/Ni/Au sputterin
spu
sputtering 5-2. Lift-off
m)) Resist
Au (200 nm)
Ni (200 nm) Cu (500 nm)
0°C
250
50°
1 μm

Fig. 3. Process flow of microbump/host electrode formation and bonding.

1 μm
III. RESULTS AND DISCUSSION 100
The cross-sectional SEM images of the MIS trench (b) Step coverage [%] 90
PE-TEOS-CVD 200 C (TSV AR: 5)
OER-TEOS-CVD r. t. (TSV AR: 5)
capacitors with a SiO2 liner dielectric formed by OER-TEOS- 80 OER-TEOS-CVD r. t. (TSV AR: 15)
CVD® at r.t. are shown in Fig. 4(a). The aspect ratio of the TSV 70 AR: Aspect ratio
is approximately 5. According to the magnified SEM images
observed at the top, middle, and bottom of the via sidewall, the
60
step coverages are calculated, as shown in Fig. 4(b). In addition, 50
the step coverages of TSVs (aspect ratio: 15) formed with OER- 40
TEOS-CVD® at r.t. and the other TSVs formed with PE-TEOS- 30
CVD at 200°C are also listed for comparison. These results 20
suggest that the room-temperature OER-TEOS-CVD® has an 10
excellent step coverage comparable to or superior to 0
conventional PE-TEOS-CVD. The lowest step coverage at the Top Middle Bottom Via
bottom sidewall is more than 16% even if the aspect ratio is 15. Bottom
The higher step coverages at the top and middle sidewalls are Sidewalls
probably due to the via profile of a sloped taper structure. Fig. 4. SEM images of deep Si holes after SiO2 liner deposition by OER-
TEOS-CVD® at r.t. (a) and step coverages formed by OER- and PE-TEOS-
Moreover, the annealing process is performed to enhance the CVD (b).
SiO2 film quality and to evaluate the annealing effect on the
dielectric constant of the SiO2 deposited by OER-TEOS-CVD®. 70
The annealing conditions were under a N2 atmosphere at 200°C
Capacitance [pF]

or 300°C for 1 hour. 60

Before annealing
50 After annealing
The measured C-V characteristics of test samples on which (300 C, 1 hour)
SiO2 is deposited by OER-TEOS-CVD® are shown in Fig. 5.
40
The capacitance in the voltage -5 V to -2 V region is clearly
reduced from 57 pF to 49 pF after annealing at 300°C. Beside 30
that, the C-V curves exhibit pretty low hysteresis in the annealed
MIS capacitor, compared to that before annealing. These 20
finding indicates that the film quality can be increased by 10
annealing the room-temperature SiO2 deposited by OER-TEOS-
CVD®. 0
-5 -4 -3 -2 -1 0 1 2 3 4 5
As shown in Table 1, the resulting k values of SiO2 deposited Vbias voltage [V]
by OER-TEOS-CVD® at r.t. and 150°C are 5.2 and 7.9, Fig. 5. C-V characteristics of TSV-structured MIS capacitors with SiO2 TSV
respectively. On the other hand, the SiO2 deposited by PE- liner dielectric formed by OER-TEOS-CVD® at room temperature and PE-
TEOS-CVD at 200°C shows the k value of 4.6. The former two TEOS-CVD at 300°C.

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TABLE I. K-VALUES OF SIO2 FORMED BY OER-TEOS CVD® AND PE- and latter bonding interface temperatures are 250°C and 190°C.
TEOS-CVD.PROCESS TEMP.Ν DEPOSITION TEMPERATURE Ͷरਜ਼ These results obviously suggest that there is little change in
daisy chain resistances obtained from both the bonded chips.
OER- PE-
TEOS-CVD® TEOS-CVD Moreover, the results indicate that the Sn microbumps are
Process successfully bonded to the corresponding Au host electrodes at
temperature RT 150°C 200°C the low temperature. The measured die shear strength of the Au-
k-Value Sn microbump bonding is shown in Fig. 10. The shear strength
5.5 7.9 4.6
(before annealing) when bonding at 150°C for top chips is 19.2 MPa. In contrast,
Annealing the shear strength when bonding at the top chip temperature of
temperature 200°C 300°C
250°C is 23.2 MPa. From these results, it can be said that high
k-Value 4.8 4.5 5.3 4.1 bonding strength beyond 15 MPa is obtained from the Au-Sn
(after annealing) systems even at the low bonding interface temperature of 190°C
without serious degradation of electrical and mechanical
(a) properties.
Cu/Sn bump
Sn
a b
6 μm 6 μm
Cu
250
50٦ 150
50
0٦
Ti/Al/Ti wiring
5 μm
40 μm Ti/Al/Ti wiring Cu IMC : Au
Au-
u-Sn Cu

(b) Cu/Ni/Au bump 250

25
50٦
50٦
٦ Ni/Cu
Ni/ 250
25
50
50٦
0٦
Cu/Ni/Au bump Interface
e Temperature:
e: 250
50
0٦ Interface
e Temperature:
e: 190
90
0٦
Fig. 7. The cross-sectional SEM images of Au-Sn interfaces bonded at the
bonding interface temperature of 250°C (a) and 190°C (b).
Ti/Al/Ti wiring
40 μm Ti/Al/Ti wiring 5 μm

Fig. 6. Photomicrographs and SEM images of fabricated Cu/Sn microbumps

DDQG&X1L$XKRVWHOHFWURGHV (b).

Figure 7 shows the cross-sectional SEM of the 40-μm-pitch

microbump joints bonded with a temperature of the top bonding
head handling the top chip of 250°C and 150°C. The top and
bottom chips have Cu/Sn microbumps and Cu/Ni/Au host
electrodes, respectively. Alignment accuracy is found to be
within 500 nm. The gap between the top and bottom chips is
approximately 5? μm. From these figures, although the bonding Cu Au Sn
pressure of 30 MPa is applied, both the chips bonded at the high
or low temperature show much less Sn extrusion by squeezing
out the solder than conventional liquid-liquid Sn-Sn bonding.
Thus, the Sn-Au bonding turns out to be compatible with fine-
pitch interconnections for 3D-ICs. It is confirmed that the Fig. 8. EDS analysis of cross-sectional Au-Sn bonding interface obtained at
successful joining of the microbumps is achieved even at quite the bonding interface temperature of 190°C.
low temperatures: the interface is at 190°C below the melting
point of pure Sn to give solid-solid inter-diffusion bonding. 350
Figure 8 shows the EDS elemental mapping of a cross-sectional
300
bonding interface between the Au and Sn. Surprisingly, IMCs
Resistance [:]

composed of Au and Sn are clearly observed, whereas the other 250

IMCs composed of Sn and Cu are hardly detected from the EDX
analysis. This is because Au diffusion into the Sn layer occurs 200
at a lower temperature compared to Sn diffusion into the Cu 150
layer. AuSn, AuSn2, and AuSn4 IMCs are seen in the EDX
results. Sn is completely converted into the IMCs during flip- 100
Bonding interface temp.
chip bonding. It is well known that the AuSn, AuSn2, and AuSn4 50 190 C 250 C
are stable compounds and they are formed at temperatures lower
than 200°C [], [18]. 0 200 400 600 800 1000 1200
Number of joints
Figure 9 shows the resistance measurement results when Fig. 9. Electrical characteristics of chips bonded at high and low temperatures
chips are bonded at the high and low temperatures. The former through Au-Sn bonding.

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 30

strength [MPa] 25 MC2W integration Effect of prebake in MC2W integration

Bonding
head
heeead
a 䛆In the case of bottom chip being Au pads䛇
20
Die shear
1st chip Exposed to heat and air Bonding
head
Bonding Exposed to heat and air
Au/Ni/Cu
15 Bonding
Substrate stage‫؟‬250٦
Substrate
10 Bonding
Hot plate: 250٦, t [min] stage
head
heeead
a Exposed to
1st chip 2nd chip heat and air
5 Comparison

0 Substrate stage‫؟‬250٦
Top chip 250 C 150 C 䛆In the case of bottom chip being Cu/Sn microbumps䛇

Bottom chip 250 C 250 C Bonding

head
heeead
a Exposed to heat and air
Bonding
head
1st chip 2nd chip nth chip
(b) Die shear strength Cu/Sn
Bonding
B Bonding
Fig. 10. Mechanical characteristics of chips bonded at high and low
temperatures through Au-Sn bonding. Substrate stage‫؟‬250٦ Hot plate: 250٦, t [min] Substrate
stage

The schematic of an acceleration exposure test is shown in
Fig. 11. A part of Cu/Ni/Au host electrodes are exposed to heat
in air during the 1st chip bonding. The exposed electrodes are
used for the subsequent 2nd chip bonding. The effectiveness of
the Au host electrodes is verified by comparing with Sn
microbumps used as bottom host electrodes for Au-Sn bonding.
When the host Sn micropbumps for the 2nd chip bonding are
Fig. 11. Schematic of accelaration exposure test by pre-heating host Au
electrodes or host Sn microbumps for multiple multichip bonding. Relationship
between daisy chain resistance and the number of joints in the daisy chains
with/without a pre-heating exposure step.
OPEN

One joint resistance:[Ω]

pre-exposed to the increased temperature of 250°C for 10 min,
the chips are not bonded at all at the 2nd bonding step. Figure
12 shows the relationship between daisy chain resistances after Bonding Temp.: 190đ
bonding and pre-heating time of Au host electrodes or Sn host
1000
microbumps. As shown in this figure, the electrical resistances Exposed Au
resulted from the chips bonded with pre-heated Sn Exposed Sn
micropbumps beyond 5 min are drastically increased, indicating
the electrical open. An additional reduction step with a formic 100
acid gas slightly lowers the resistance. However, the resulting
resistance is much higher than the initial value without pre-
heating. This is due to the IMC formation before bonding to give
no pure solder for chip bonding. In contrast, the Au electrodes 10
0 10 20 30
have high environmental tolerance toward the pre-heating at Pre-heating exposure time [min]
250°C for 30 min. The chips having Sn microbumps are
successfully bonded to the pre-heated Au electrodes. Fig. 12. Relationship between RQHMRLQWUHVLVWDQFH and pre-heating exposure
time.
Figure 13 shows the exposure test results of Cu/Ni/Au host
electrodes with/without pre-heating before flip-chip bonding.
There is no change in the resistance values of the Au-Sn
microbump daisy chain with excess heating at 250°C for 30 min. 350
This result reveals that the low-height Cu/Sn microbumps are Bonding temp. : 250 C
Resistance [:]

successfully bonded to the Cu/Ni/Au electrodes even after 300

highly accelerated exposure by the excess pre-heating. The Au- 250
Sn microbump bonding system is a promising candidate to
realize multiple multichip bonding processes in via-last MC2W 200
3D integration with fine-pitch interconnection at below 200°C.
150
We apply the low-temperature MC2W 3D integration
technologies to fully implantable 3D artificial retina chip 100 Without heat exprosure
fabrication for restoring the visual sensation of blind patients, as
50 With heat exprosure
shown in Fig. 14 [19], [20]. This 3D artificial retina chip is (250 C, 30min)
consisting of a CMOS image sensor as a top chip and a signal
processing/stimulus current generator as a bottom chip. These 0 200 400 600 800 1000 1200
two chips with Cu-TSVs formed by the via-last processes are Number of joints
stacked in a back-to-face fashion. We successfully confirm its Fig. 13. Relationship between daisy chain resistance and the number of joints
basic operation in which stimulation frequencies to retinal in the daisy chains with/without a pre-heating exposure step.
neurons are well controlled by the intensity of the incident light.

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 Chip receiving light (3mm x 3mm)
Signal processing / stimulation current
generation chip (5mm x 5mm)
Fig. 14. A photo of fabricated 3D artificial retina chip with via-last TSV (left)
and its schematic configuration (right).
IV. CONCLUSION
A room-temperature TSV liner SiO2 formation named OER-
TEOS-CVD® and low-temperature Au-Sn low-height
microbump bonding was implemented to solve the thermal
issues in via-last MC2W 3D integration. High step coverage,
relatively low dielectric constant, and low leak current were
shown with the trench and planar MIS capacitors using the
OER-TEOS-CVD SiO2. In addition, the Au-Sn microbump
bonding system withstood the accelerated exposure test of pre-
heating at 250°C for 30 min in air, which allows the MC2W
heterogeneous 3D integration with multiple multichip bonding.
An implantable 3D artificial retina chip was successfully
fabricated by applying these 3D integration technologies.
ACKNOWLEDGEMENT
This work was performed in the Micro/Nano-machining
research and education Center (MNC) and Jun-ichi Nishizawa
Research Center at Tohoku University. We acknowledge
MEIDENSHA Corporation (Japan) for their OER-TEOS-
CVD® process support. This work was partially supported by
JSPS KAKENHI Grant Number 18H04159 and 19KK0101.
This work was also supported by VLSI Design and Education
Center (VDEC), University of Tokyo, in collaboration with
Cadence Design Systems.
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