NT5CB256M8BN/NT5CB128M16BP

NT5CC256M8BN/NT5CC128M16BP

2Gb DDR3 SDRAM B-Die                                                        


Table 2: Input / Output Functional Description
Symbol Type Function

Clock: CK and &. are differential clock inputs. All address and control input signals are
CK, ҏ&. Input
sampled on the crossing of the positive edge of CK and negative edge of &..

Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE low provides Precharge
Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit and for
CKE, (CKE0), Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. After VREF has
Input
(CKE1) become stable during the power on and initialization sequence, it must be maintained
for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF
must maintain to this input. CKE must be maintained high throughout read and write

accesses. Input buffers, excluding CK, &., ODT and CKE are disabled during Power
Down. Input buffers, excluding CKE, are disabled during Self-Refresh.

Chip Select: All commands are masked when &6 is registered high. &6 provides for
&6, (&6), (&6),
Input external rank selection on systems with multiple memory ranks. &6is considered part
(&6), (&6)
of the command code.

Command Inputs: 5$6, &$6 and :( (along with &6) define the command being
5$6, &$6, :( Input
entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write access. DM is
DM, (DMU, DML) Input
sampled on both edges of DQS. For x8 device, the function of DM or TDQS /74'6 is
enabled by Mode Register A11 setting in MR1

Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read,
Input
BA0 - BA2 Write or Precharge command is being applied. Bank address also determines which

mode register is to be accessed during a MRS cycle.

Auto-Precharge: A10 is sampled during Read/Write commands to determine whether

Autoprecharge should be performed to the accessed bank after the Read/Write
operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a
A10 / AP Input
Precharge command to determine whether the Precharge applies to one bank (A10

LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by bank addresses.

Address Inputs: Provide the row address for Activate commands and the column
address for Read/Write commands to select one location out of the memory array in
A0 – A14 Input
the respective bank. (A10/AP and A12/%& have additional function as below.) The
address inputs also provide the op-code during Mode Register Set commands.

ϱ
REV 1.6 CONSUMER DRAM
May. 2011 © NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5CB256M8BN/NT5CB128M16BP
NT5CC256M8BN/NT5CC128M16BP

2Gb DDR3 SDRAM B-Die                                                        


Symbol Type Function

Burst Chop: A12/%&is sampled during Read and Write commands to determine if
A12/%& Input
burst chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).

On Die Termination: ODT (registered HIGH) enables termination resistance internal

to the DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQS, '46and
ODT, (ODT0),
Input DM/TDQS, NU/7'46 (when TDQS is enabled via Mode Register A11=1 in MR1) signal
(ODT1)
for x8 configurations. The ODT pin will be ignored if Mode-registers, MR1and MR2, are
programmed to disable RTT.

Active Low Asynchronous Reset: Reset is active when 5(6(7 is LOW, and inactive
when 5(6(7 is HIGH. 5(6(7 must be HIGH during normal operation. 5(6(7 is a
5(6(7 Input
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for
DC high and 0.30V

DQ Input/output Data Inputs/Output: Bi-directional data bus.

DQL, Data Strobe: output with read data, input with write data. Edge aligned with read data,
DQU, centered with write data. The data strobes DQS, DQSL, DQSU are paired with
DQS , ('46), Input/output differential signals '46, '46/, '468, respectively, to provide differential pair signaling
DQSL,('46/), to the system during both reads and writes. DDR3 SDRAM supports differential data
DQSU,('468), strobe only and does not support single-ended.

Termination Data Strobe: TDQS/7'46 is applicable for X8 DRAMs only. When

enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination

resistance function on TDQS/7'46 that is applied to DQS/'46. When disabled via

TDQS, (7'46) ʳ Output
mode register A11=0 in MR1, DM/7'46 will provide the data mask function and 7'46
is not used. x16 DRAMs must disable the TDQS function via mode register A11=0 in
MR1.

NC - No Connect: No internal electrical connection is present.

VDDQ Supply DQ Power Supply: 1.35V -0.675V/+0.1V or & 1.5V ± 0.075V

VDD Supply Power Supply: 1.35V -0.675V/+0.1V or & 1.5V ± 0.075V

VSSQ Supply DQ Ground

Vss Supply Ground

VREFCA Supply Reference voltage for CA

VREFDQ Supply Reference voltage for DQ

ZQ Supply Reference pin for ZQ calibration.

Note: Input only pins (BA0-BA2, A0-A14, 5$6, &$6, :(, &6, CKE, ODT, and 5(6(7) do not supply termination.

ϲ
REV 1.6 CONSUMER DRAM
May. 2011 © NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.