MC6809-MC6809E 8-Bit Microprocessor Programming Manual (Motorola Inc.) 1981

M6809PM (AD)
MC6809·MC6809E
8·BIT MICROPROCESSOR
PROGRAMMING MANUAL
Original Issue: March 1, 1981

Reprinted: May 1983
©MOTOROLA INC., 1981

TABLE OF CONTENTS
Paragraph No. Title Page No.
SECTION 1
GENERAL DESCRIPTION
1.1 Introduction .............................................................................................................1-1

1.2 Features 1-1
...................................................................................................................
1.3 Software Features ..................................................................................................1-2

1.4 Programming Model ...............................................................................................1-3
1.5 Index Registers (X, Y) . ..... . .
........... ..... ........... .... . . .
...................... ... . 1-3
.......... .............. .
1.6 Stack Pointer Registers (U, S) ...............................................................................1.3

1.7 Program Counter ( PC) ............................................................................................1-4
1.8 Accumulator Registers (A, B, D) ...........................................................................1-4
1.9 Direct Page Register (O P) ...................................................................................... 1-4
1.10 Condition Code Register (CC) ...............................................................................1-4
1.10.1 Condition Code Bits ...........................................................................................1-5
1.10.1.1 Half Carry ( H), Bit 5 .........................................................................................1-5
1.10.1.2 Negative (N), Bit 3 ...........................................................................................1-5
1.10.1.3 Zero (Z), Bit 2....................................................................................................1.5
1.10.1.4 Overflow (V), Bit 1 . . . . . ..
......·.......... . ..................................... ..... . . .. 1-5
... . .............. .. .
1.10.1.5 Carry (C), Bit 0 .................................................................................................1-5

1.10.2 Interrupt Mask Bits and Stacking Indicator .................................................... 1-5
1.10.2.1 Fast Interrupt Request Mask (F), Bit 6 .........................................................1-5
1.10.2.2 Interrupt Request Mask (I), Bit 4 ...................................................................1-5
1.10.2.3 Entire Flag (E), Bit 7 ........................................................................................1-6
1.11 Pin Assignments and Signal Oescription ............................................................ 1-6
1.11.1 MC6809 Clocks ...................................................................................................1-6
1.11.1.1 Oscillator (EXTAL, XTAL)...............................................................................1-6
1.11.1.2 Enable (E)............. ,...........................................................................................1-7
1.11.1.3 Quadrature (Q) ................................................................................................1-7
1.11.2 MC6809E Clocks (E and Q) ................................................................................1-7
1.11.3 Three State Control (TSC) (MC6809E) ..............................................................1-7
1.11.4 Last Instruction Cycle (LIC) (MC6809E) ...........................................................1-7
1.11.5 Address Bus (AO·A15).........................................................................................1-7
1.11.6 Data Bus (00-07) .................................................................................................1-7
1.11.7 ReadlWrite (RIW).................................................................................................1-8
1.11.8 Processor State Indicators (BA, BS) ................................................................1-8
1.11.8.1 Normal .............................................................................................................1-8
1.11.8.2 Interrupt or Reset Acknowledge ...................................................................1-8
1.11.8.3 Sync Acknowledge .........................................................................................1-8
iii
TABLE OF CONTENTS
(CONTINUED)
1.11.8.4 Halt/Bus Grant ................................................................................................1·8

1.11.9 Reset (RESET) .....................................................................................................1·9
1.11.10 Interrupts .............................................................................................................1·9
1.11.10.1 Non·Maskable Interrupt (NMI) ......................................................................1·9
1.11.10.2 Fast Interrupt Request (FIRQ).......................................................................1·9
1.11.10.3 Interrupt Request (IRQ)..................................................................................1·9
1.11.11 Memory Ready (MRD Y) (MC6809) .....................................................................1·9
1.11.12 Advanced Valid Memory Address (AVMA) (MC6809E) .................................1·10
1.11.13 Halt (HALT) ........................................................................................................1·10
1.11.14 Direct Memory Access/Bus Request (DMA/BREQ) (MC6809) .....................1·10
1.11.15 Busy (MC6809E) ................................................................................................1·10
1.11.16 Power .
....... . . .
............... ..... .
..... ... ....... . .
..... .
.................... .. 1·11
................ ....................
SECTION 2
ADDRESSING MODES
2.1 Introduction . .
.............. .... .
............. ......... . . . . .
.................................. 2·1 .. .... ....... ...... ........
2.2 Addressing Modes ..................................................................................................2·1

2.2.1 Inherent................................................................................................................2·1
2.2.2 Immediate . ... ... .
.......................... ... .. ......... . . ..
........................... 2·1 .......... ........ . .........
2.2.3 Extended . . .
.................................................. . . .... .... . . . .. 2·2
.......... ...... .. ................... .. .. .
2.2.4 Direct 2·2

....................................................................................................................
2.2.5 Indexed . ..
....... .. . . . . .. . .
................ ............ . .. ... . . . ..
... . ..... ........... .. 2·2
.. .. ..... . ................... ..
2.2.5.1 Constant Offset from Register . ... . . .. . .. .. . .

..... .. . . 2·2
............ . ...... .... ............. ... .. ....
2.2.5.2 Accumulator Offset from Register ...............................................................2·3

2.2.5.3 Autoincrement/Decrement from Register...................................................2·3
2.2.5.4 Indirection .......................................................................................................2·4
2.2.5.5 Extended Indirect ...........................................................................................2·4
2.2.5.6 Program Counter Relative .............................................................................2·4
2.2.6 Branch Relative ..................................................................................................2·4
SECTION 3
INTERRUPT CAPABILITIES
3.1 Introduction .............................................................................................................3·1

3.2 Non·Maskable Interrupt (NMI) ..............................................................................3·1
3.3 Fast Maskable Interrupt Request (FIRQ).............................................................3·2
3.4 Normal Maskable Interrupt Request (IRQ) ..........................................................3·2
3.5 Software Interrupts (SWI, SWI2, SWI3) ................................................................3·2
iv
TABLE OF CONTENTS
(CONCLUDED)
SECTION 4
PROGRAMMING
4.1 Introduction ............................................................................................................. 4-1

4.1.1 Position-Independence ...................................................................................... 4-1
4.1.2 Modular Programming ....................................................................................... 4-1
4.1.2.1 Local Storage .................................................................................................. 4-1
4.1.2.2 Global Storage ................................................................................................ 4-2
4.1.3 Reentrancy/Recursion ....................................................................................... 4-2
4.2 M6809 Capabilities ................................................................................................. 4-2
4.2. 1 Module Construction ......................................................................................... 4-2
4.2.1. 1 Parameters ...................................................................................................... 4-3
4.2.1.2 Local Storage ..................................................................................................4-3
4.2.1.3 Global Storage ................................................................................................4-3
4.2.2 Position-Independent Code .............................................................................. 4-4
4.2.3 . Reentrant Programs ........................................................................................... 4-5
4.2.4 Recursive Programs ...........................................................................................4-5
4.2.5 Loops 4-5
...................................................................................................................
4.2.6 Stack Programming ...........................................................................................4-6

4.2.6.1 M6809 Stacking Operations ..........................................................................4-6
4.2.6.2 Subroutine Linkage ........................................................................................4-7
4.2.6.3 Software Stacks .............................................................................................4-8
4.2.7 Real Time Programming ....................................................................................4-8
4.3 Program Documentation 4-8
.......................................•...............................................
4.4 Instruction Set ........................................................................................................4-9
APPENDIX A
INSTRUCTION SET DETAILS
A.1 Introduction ............................................................................................................A-1

A.2 Notation ..................................................................................................................A-1
Instructions (listed in alphabetical order)...........................................................A-3
APPENDIX B
ASSIST09 MONITOR PROGRAM
8.1 General Description ............................................................................................... 8-1

8.2 Implementation Requirements ............................................................................ 8-1
8.3 Interrupt Control .................................................................................................... 8-2
8.4 Initialization ............................................................................................................ 8-3
v
TABLE OF CONTENTS
(CONTINUED)
B.5 Input/Output Control ............................................................................................. B-4

B.6 Command Format ..................................................................................................B-4
B.7 Command List ........................................................................................................B-5
B.8 Commands .............................................................................................................. B-5
Breakpoint ...........................................................................................................B-6
Call .......................................................................................................................B-6
Display .................................................................................................................B-7
Encode ................................................................................................................B-7
Go ......................................................................................................................... B-8
Load ..................................................................................................................... B-8
Memory ...............................................................................................................B-9
Null ....................................................................................................................B-10
Offset ................................................................................................................. B-10
Punch B-11
.....................................................•...........................................................
Register ............................................................................................................. B-11

Stlevel ................................................................................................................B-12
Trace ..................................................................................................................B-12
Verify .................................................................................................................B-13
Window .............................................................................................................B-13
B.9 Services ................................................................................................................. B-14
BKPT ..................................................................................................................B-15
INCHP................................................................................................................B-15
MONITR.............................................................................................................B-16
OUTCH ..............................................................................................................B-17
OUT2HS.............................................................................................................B-17
OUT4HS.............................................................................................................B-18
PAUSE ...............................................................................................................B-18
PCRLF ...............................................................................................................B-19
PDATA ............................................................................................................... B-19
PDATA1 .............................................................................................................B-20
SPACE ....•..........................................................................................................B-21
VTRSW ..............................................................................................................B-21
B.10 Vector Swap Service ............................................................................................B-22
.ACIA ..................................................................................................................B-23
.AVTBL...............................................................................................................B-23
.BSDTA .............................................................................................................. B-24
.BSOFF ..............................................................................................................B-24
.BSON ................................................................................................................B-25
.CIDTA ...............................................................................................................B-25
.CIOFF ...............................................................................................................B-26
.CION .................................................................................................................B-26
.CMDL1 ..............................................................................................................B-27
.CMDL2 ..............................................................................................................B-28
vi
TABLE OF CONTENTS
(CONTINUED)
.CODTA .
.......................................... . . ........ 8-28
....................................... ...... ............
.COOFF ............................................................................................................. 8-29

.COON ............................................................................................................... 8-29
.ECHO ................................................................................................................ 8-30
.FIRQ .................................................................................................................. 8-30·
.HSDATA ................................................ . ...................... . ................ . ...... . ........ . 8-31
..
.IRQ .................................................................................................................... 8-31

.NMI .......................... . .............. . ......... . .......................... ............................... . . 8-32
.. ..
.PAD ........ ....................................... . ........ . ........................................... . .............. 8-32

.PAUSE ....................... . ................................. . .
.. ......................... .
.......... .... ......... 8-33
.PTM ........ ..
. ..
... ........................... ............. . ......... . ............................. . . .. ..... . .. . 8-33
.. .. ..
.RESET ..... . ........ . ............... . ..

... ................ . .... . .... . ............ ... ... .
. . .... . ........... . ..... . . . 8-34
..
.RSVD ........... . .......... ..

. ............................ ... . . .... . ................... .. ..... .. . ........ .. ... .. ..... 8-34
.SWI ....... . ......... . ....................................... . ...... .. . . .... . ............ .. ....... . .... . ......... . ...... 8-35
.SWI2.................................................................................................................. 8-35
.SWI3.................................................................................................................. 8-36
8.11 Monitor Listing ... ...
. . .... . .... . .
.. .... . ..... .. . . .... ... .. .
. .. .... .. .... ... ... .. .. . . ....
. . . . .. ....... . .. . .. . .. 8-37
. . . . .
APPENDIX C
MACHINE CODE TO INSTRUCTION CROSS REFERENCE
C.1 Introduction . .. ........... . ..... .. .. ... .

.. . . . .. ... . .... . ...... . . .. ... .. ..
. .. . .
..... .... .. ....... . ..... .. . . . . .. . C-1
. . . .. . .. .
APPENDIX D
PROGRAMMING AID
0.1 Introduction ..... . . . .. .... ...

. . .. . . .. .. ... . .... .. . . .. .... .. � . . .. ....... ... ............. ...... ......... . 0·1
. . . . .. . . . . . . . . . . .
APPENDIX E
ASCII CHARACTER SET
E.1 Introduction ............................................................................................................E·1

E.2 Character Representation and Code Identification ..........................................E·1
E.3 Control Characters ................................................................................................E·2
E.4 Graphic Characters ...............................................................................................E·2
vii
TABLE OF CONTENTS
(CONTINUED)
APPENDIX F
OPCODE MAP
F.1 Introduction F-1

............................................................................................................
F.2 Opcode Map............................................................................................................ F-1
APPENDIX G
PIN ASSIGNMENTS
G.1 Introduction ............................................................................................................ G-1
APPENDIX H
CONVERSION TABLES
H.1 Introduction ............................................................................................................ H-1
H.2 Powers of 2; Powers of 16 ..................................................................................... H-1
H.3 Hexadecimal and Decimal Conversion............................................................... H-2
H.3.1 Converting Hexadecimal to Decimal .............................................................. H-2 .
H.3.2 Converting Decimal to Hexadecimal .............................................................. H-2
LIST OF ILLUSTRATIONS
Figure No. Title Page No.
1-1 Programming Model ...............................................................................................1-3

1-2 Condition Code Register .......................................................................................1-4
1-3 Processor Pin Assignments .................................................................................. 1-6
2-1 Post byte Usage for EXGrrFR, PSH/PUllnstructions ........................................2-2
3-1 Interrupt Processing Flowchart ............................................................................3-5
4-1 Stacking Order ........................................................................................................4-7
8-1 Memory Map ........................................................................................................... 8-2
E-1 ASCII Character Set ...............................................................................................E-1
G-1 Pin Assignments .................................................................................................... G-1
viii
LIST OF TABLES
Table No. Title Page No.
1 -1 BAlBS Signal Encoding ........................... . ................................... . . .. ............ . .

.. ....... 1 -8
2-1 Postbyte Usage for Indexed Addressing Modes ................................................2-3
3-1 Interrupt Vector Locations .......................................... . ...... . ....... . .......................... 3-1
4-1 Instruction Set ........................................... . ....................... . .

.. ........ .. ....... . ....... . ....... 4-9
4-2 8-Bit Accumulator and Memory Instructions ............................ . ........... . ......... . 4-1 1
.
4-3 16-Bit Accumulator and Memory Instructions ..... . ........ . ................................... 4-12
4-4 Index/Stack Pointer Instructions ......... . ............ . ...... . ...... . ....... . ..... . .............. . ...... 4-1 2
4-5 Branch Instructions .......................................... . ... . ..................... . .... . ................... 4-1 3
4-6 Miscellaneous Instructions .... ....... . ................... . ........................................ . ....... 4-1 3
A-1 Operation Notation ....................... . ... . .............................. . ......................... . .......... .A-1

A-2 Register Notation ...................................................................................................A-2
B-1 Command List ........................................................................................................B-5

B-2 Services B-1 4
.................................................................................................................
B-3 Vector Table Entries ............................................................................................B-22
C-1 Machine Code to Instruction Cross Reference .................................................. C-2
0-1 Programming Aid ................................................................................................... 0-1
E-1 Control Characters ................................................................................................ E-2

E-2 Graphic Characters . ... . .
............................ .. . . .
.......... . .
...............E-3 . .. .. ............... .... .....
F-1 Opcode Map .

................... ...................................................... . ......... . ........ � .......... . ... F-2
F-2 Indexed Addressing Mode Data ... . ............. ............ . .................. . ..... . ...... . ............. F-3
H-1 Powers of 2; Powers of 16 .....................................................................................H-1

H-2 Hexadecimal and Decimal Conversion Chart ....................................................H-2
ix/x
SECTION 1
GENERAL DESCRIPTION
1.1 INTRODUCTION
This section contains a general description of the Motorola MC6809 and MC6809E
Microprocessor Units (MPU). Pin assignments and a brief description of each input/out
put signal are also given. The term MPU, processor, or M6809 will be used throughout this
manual to refer to both the MC6809 and MC6809E processors. When a topic relates to
only one of the processors, that specific designator (MC6809 or MC6809E) will be used.
.
1.2 FEATURES
The MC6809 and MC6809E microprocessors are greatly enhanced, upward compatible,
computationally faster extensions of the MC6800 microprocessor.
Enhancements such as additional registers (a Y index register, a U stack pOinter, and a

direct page register) and instructions (such as MUL) simplify software design. Improved
addressing modes have also been implemented.
Upward compatibility is guaranteed as MC6800 assembly language programs may be

assembled using the Motorola MC6809 Macro Assembler. This code, while not as com
pact as native M6809 code, is, in most cases, 100% functional.
Both address and data are available from the processor earlier in an instruction cycle
than from the MC6800 which simplifies hardware design. Two clock signals, E (the
MC6800 <1>2) and a new quadrature clock Q (which leads E by one-quarter cycle) also
simplify hardware design.
A memory ready (MRDY) input is provided on the MC6809 for working with slow
memories. This input stretches both the processor internal cycle and direct memory ac
cess bus cycle times but allows internal operations to continue at full speed. A direct
memory access request (DMAIBREQ) input is provided for immediate memory access or
dynamic memory refresh operations; this input halts the internal MC6809 clocks.
Because the processor's registers are dynamic, an internal counter periodically recovers
the bus from direct memory access operations and performs a true processor refresh
cycle to allow unlimited length direct memory access operation. An interrupt
acknowledge signal is available to allow development of vectoring by interrupt device
hardware or detection of operating system calls.
1-1
Three prioritized, vectored, hardware interrupt levels are available: non-maskable, fast,
and normal. The highest and lowest priority interrupts, non-maskable and interrupt re
quest respectively, are the normal interrupts used in the M6800 family. A new interrupt on
this processor is the fast interrupt request which provides faster service to its interrupt
input by only stacking the program counter and condition code register and then servic
ing the interrupt.
Modern programming techniques such as position-independent, system independent,

and reentrant programming are readily supported by these processors.
A Memory Management Unit (MMU), the MC6829, allows a M6809 based system to ad
dress a two megabyte memory space. Note: An arbitrary number of tasks may be sup
ported - slower - with software.
This advanced family of processors is compatible with all M6800 peripheral parts.
1.3 SOFTWARE FEATURES
Some of the software features of these processors are itemized in the following
paragraphs. Programs developed for the MC6800 can be easily converted for use with the
MC6809 or MC6809E by running the source code through a M6809 Macro Assembler or
any one of the many cross assemblers that are available.
The addressing modes of any microprocessor provide it with the capability to efficiently
address memory to obtain data and instructions. The MC6809 and MC6809E have a ver
satile set of addressing modes which allow them to function using modern programming
techniques.
The addressing modes and instructions of the MC6809 and MC6809E are upward com
patible with the MC6800. The old addressing modes have been retained and many new
ones have been added.
A direct page register has been added which allows a 256 byte "direct" page anywhere in
the 64K logical address space. The direct page register is used to hold the most
significant byte of the address used in direct addreSSing and decrease the time required
for address calculation.
Branch relative addressing to anywhere in the memory map (- 32768 to + 32767) is

available.
Program counter relative addreSSing is also available for data access as well as branch
instructions.
The indexed addreSSing modes have been expanded to include:

0-, 5-, 8-, 16-bit constant offsets,
8- or 16-bit accumulator offsets,
autoincrement/decrement (stack operation).
1-2
In addition, most indexed addressing modes may have an additional level of indirection
added.
Any or all registers may be pushed on to or pulled from either stack with a single instruc
tion.
A multiply instruction is included which multiplies unsigned binary numbers in ac

cumulators A and B and places the unsigned result in the 16-bit accumulator D. This un
signed multiply instruction also allows signed or unsigned multiple precision multiplica
tion.
1.4 PROGRAMMING MODEL
The programming model (Figure 1-1) for these processors contains five 16-bit and four
8-bit registers that are available to the programmer.
}
15 o
x - I ndex Register
Y - I ndex Register
Po;",,, Rog;"""
U - User Stack Pointer
S - Hardware Stack Poi nter
PC Progra m Cou nter
A
I B Accumu lators
,
D
7 0
LoI ____ ____ DP 1

... Direct Page Register
7 0
I ElF I H I I I N I z I V I C I Condition Code Register
Figure 1·1. Programming Model
1.5 INDEX REG ISTERS (X, y)
The index registers are used during the indexed addressing modes. The address informa
tion in an index register is used in the calculation of an effective address. This address
may be used to point directly to data or may be modified by an optional constant or
register offset to produce the effective address.
1.6 STACK POINTER REGISTERS (U, S)
Two stack pOinter registers are available in these processors. They are: a user stack
pOinter register (U) controlled exclusively by the programmer, and a hardware stack
pOinter register (5) which is used automatically by the processor during subroutine calls
1-3
and interrupts, but may also be used by the programmer. Both stack pOinters always
point to the top of the stack.
These registers have the same indexed addressing mode capabilities as the index
registers, and also support push and pull instructions. All four indexable registers (X, Y,
U, S) are referred to as pOinter registers.
1.7 PROGRAM COUNTER (PC)
The program counter register is used by these processors to store the address of the
next instruction to be executed. It may also be used as an index register in certain ad·
dressing modes.
1.8 ACCUMULATOR REGISTERS (A, B, D)
The accumulator registers (A, B) are general·purpose 8·bit registers used for arithmetic
calculations and data manipulation.
Certain instructions concatenate these registers into one 16·bit accumulator with
register A positioned as the most·significant byte. When concatenated, this register is
referred to as accumulator D.
1.9 DIRECT PAG E REGISTER (DP)
This 8-bit register contains the most·significant byte of the address to be used in the
direct addressing mode. The contents of this register are concatenated with the byte
following the direct addressing mode operation code to form the 16·bit effective address.
The direct page register contents appear as bits A15 through A8 of the address. This
register is automatically cleared by a hardware reset to ensure M6800 compatiblity.
1.10 CONDITION CODE REGISTER (CC)
The condition code register contains the condition codes and the interrupt masks as
shown in Figure 1·2.
Carry
....-Overflow
..
----Zero
----- Negative
.......
--- - I RQ Mask
....-----
. H alf Carry
'------ FIRQ Mask
----- Entire Flag
Figure 1·2. Condition Code Register
1·4
1.10.1 CONDITION CODE BITS. Five bits in the condition code register are used to in
dicate the results of instructions that manipulate data. They are: half carry (H), negative
(N), zero (Z), overflow (V), and carry (C). The effect each instruction has on these bits is
given in the detail information for each instruction (see Appendix A).
1.10.1.1 Half Carry (H), Bit 5. This bit is used to indicate that a carry was generated from
bit three in the arithmetic logiC unit as a result of an a-bit addition. This bit is undefined in
all subtract-like instructions. The decimal addition adjust (OAA) instruction uses the
state of this bit to perform the adjust operation.
1.10.1.2 N eg ative (N),

Bit 3. This bit contains the value of the most-significant bit of the
result of the previous data operation.
1.10.1.3 Zero (Z), Bit 2. This bit is used to indicate that the result of the previous opera
tion was zero.
1.10.1.4 Overflow (V),

Bit 1. This bit is used to indicate that the previous operation caused
a signed arithmetic overflow.
1.10.1.5 Carry(C), Bit O. This bit is used to indicate that a carry or a borrow was generated
from bit seven in the arithmetic logic unit as a result of an a-bit mathematical operation.
1.10.2 INTERRUPT MASK BITS AND STACKING INDICATOR. Two bits (I and F) are used
as mask bits for the interrupt request and the fast interrupt request inputs. When either
or both of these bits are set, their associated input will not be recognized.
One bit (E) is used to indicate how many registers (all, or only the program counter and
condition code) were stacked during the last interrupt.
1.10.2.1 Fast Interrupt Mask (F), Bit 6. This bit is used to mask (disable) any fast
Request
Q
interrupt request line (FIR ). This bit is set automatically by a hardware reset or after
recognition of another interrupt. Execution of certain instructions such as SWI will also
inhibit recognition of a FIRQ input.
1.10.2.2Interru�equest Ma s k (I), Bit

This bit is used to mask (disable) any interrupt
4.
request input (IRQ). This bit is set automatically by a hardware reset or after recognition
of another interrupt. Execution of certain instructions such as SWI will also inhibit
recognition of an IRQ input.
1·5
1.10.2.3 Ent i re Flag (E), Bit 7. This bit is used to indicate how many registers were stack
ed. When set, all the registers were stacked during the last interrupt stacking operation.
When clear, only the program counter and condition code registers were stacked during
the last interrupt.
The state of the E bit in the stacked condition code register is used by the return from in
terrupt (RTI) instruction to determine the number of registers to be unstacked.
1.11 PIN ASSIGNMENTS AND SIGNAL DESCRIPTION
Figure 1-3 shows the pin assignments for the processors. The following paragraphs pro
vide a short description of each of the input and output signals.
MC6809 MC6809E
VSS H'A'CT VSS HALT
NMI XTAL NMI TSC

IRQ EXTAL IRQ LlC
FIRQ 4 RESET FIRQ 37 RESET
BS 5 MR O Y BS 36 AVMA
BA 6 Q. 35 Q
VCC 7 E VCC 34 E
AO 8 OMA/BREQ AO 33 BUSY
Al 9 R/ W 32 R/W
A2 10 DO 31 DO
A3 11 01 30 01
02 29 02
03 28 03
A6 04 27 04
A7 05 26 05
A8 16 06 25 06
A9 07 A9 24 07
Al0 Al5 Al0 23 Al5
All A14 All 22 Al4
A12 Al2 21 A13
Figure 1-3. Processor Pin Assignments
1.11.1 MC6809 CLOCKS. The MC6809 has four pins committed to developing the clock
signals needed for internal and system operation. They are: the oscillator pins EXTAL
and XTAL; the standard M6800 enable (E) clock; and a new, quadrature (Q) clock.
1.11.1.1 Oscillator (EXTAL, XTAL). These pins are used to connect the processor's inter
nal oscillator to an external, parallel-resonant crystal. These pins can also be used for in
put of an external TTL timing signal by grounding the XTAL pin and applying the input to
the EXTAL pin. The crystal or the external timing source is four times the resulting bus
frequency.
1-6
1.11.1.2 Enable (E). The E clock is similar to the phase 2 (<p2) MC6800 bus timing clock.
The leading edge indicates to memory and peripherals that the data is stable and to
begin write operations. Data movement occurs after the Q clock is high and is latched on
the trailing edge of E. Data is valid from the processor (during a write operation) by the
rising edge of E.
1.11.1.3 Quadrature (Q). The Q clock leads the E clock by approximately one half of the E
clock time. Address information from the processor is valid with the leading edge of the
Q clock. The Q clock is a new signal in these processors and does not have an equivalent
clock within the MC6800 bus timing.
1.11.2 MC6809E CLOCKS (E and Q). The MC6809E has two pins provided for the TIL
clock signal inputs required for internal operation. They are the standard M6800 enable
(E) clock and the quadrature (Q) clock. The Q input must lead the E input.
Addresses will be valid from the processor (on address delay time after the falling edge
of E) and data will be latched from the bus by the falling edge of E. The Q input is fully TIL
compatible. The E input is used to drive the internal MOS circuitry directly and therefore
requires input levels above the normal TIL levels.
1.11.3 THREE STATE CONTROLS (TSC) (MC6809E). This input is used to place the ad
dress and data lines and the RIW line in the high-impedance state and allows the address
bus to be shared with other bus masters.
1.11.4 LAST INSTRUCTION CYCLE (LIC)(MC6809E). This output goes high during the last
cycle of every instruction and its high-to-Iow transition indicates that the first byte of an
opcode will be latched at the end of the present bus cycl�.
1.11.5 ADDRESS BUS(AO·A15). This 16-bit, unidirectional, three-state bus is used by the
processor to provide address information to the address bus. Address information is
valid on the rising edge of the Q clock. All 16 outputs are in the high-impedance state
when the bus available (BA) signal is high, and for one bus cycle thereafter.
When the processor does not require the address bus for a data transfer, it outputs ad
dress FFFF16, and read/write (RIW) high. This is a "dummy access" of the least
significant byte of the reset vector which replaces the valid memory address (VMA) func
tions of the MC6800. For the MC6809, the memory read signal internal circuitry inhibits
stretching of the clocks during non-access cycles.
1.11.6 DATA BUS (00·07). This 8-bit, bidirectional, three-state bus is the general purpose
data path. All eight outputs are in the high-impedance state when the bus available (BA)
output is high.
1-7
1 .11.7 READIWRITE (RIW). This output indicates the d i rection of data transfer on the data
bus. A low indicates that the processor is writi n g onto the data bus; a high indicates that
the processor is read i n g data from the data bus. The signal at the R/W output is val i d at
the lead i n g edge of the Q clock. The R/W output is in the h igh-i m pedance state when the
bus ava i l able (BA) output is high.
1 .1 1.8 PROCESSOR STATE INDICATORS (BA, BS). The processor uses these two output
l i nes to indicate the p resent processor state. These pins are val id with the leadi n g edge
of the Q c lock.
The bus available (BA) output is used to i ndicate that the buses (address and data) and
the read/write output are in the h i g h-Im pedance state. Thi s signal can be used to i n d i cate
to bus-sharing or d irect memory access systems that the buses are available. When BA
goes low, an additional dead cycle will elapse before the processor regains control of the
buses.
The bus status (BS) output is used in conjunction With the BA output to I ndicate the pre
sent state of the processor. Table 1 -1 is a listing of the BA and BS outputs and the pro
cessor states that they Indicate. The fol lowing paragraphs briefly explain each processor
state.
Table 1-1. BAIBS Signal Encoding
M U Pl'OC8IIOr State
0 0 Normal (Running)
0 1 Interrupt or Reset Acknowledge
1 0 Sync Acknowledge
1 1 Haiti Bus Grant Acknowledged
1 _1 1 .8.1 Normal. The processor is run n i ng and executing i nstructions.
1 .1 1 .8.2 Interrupt or Reset Acknowledge. This processor state is i nd icated d u ring both
cycles of a hardware vector fetch which occurs when any of the fol l ow i n g i nterrupts have
occurred: RESET, N MI, FIRQ, IRQ, SWI, SWI2, and SWI3.
This output, p l us decod ing of address li nes A3 through A1 provides the user with an
i ndication of which interrupt is bei ng serviced.
1 .11.8.3 Sync Acknowledge. The processor is waiting for an external synchron ization in
put on an i nterrupt l i ne. See SYN C inst ruction i n Appendix A.
1 .11.8.4 Halt/Bus Grant. The processor is halted or bus control has been g ranted to some
other device.
1-8
1.11 .9 RESET (RESET). This input is used to reset the processor. A low input lasting
longer than one bus cycle will reset the processor.
The reset vector is fetched from locations $FFFE and $FFFF when the processor enters
the reset acknolwedge state as indicated by the BA output being low and the BS output
being high.
During initial power-on, the reset input should be held low until the clock oscillator is ful
ly operational.
1.1 1 .1 0 INTERRUPT�The processor has three separate interrupt input�s: non

maskable interrupt (NMI), fast interrupt request (FIRQ), and interrupt request (IRQ). These
interrupt inputs are latched by the falling edge of every Q clock except during cycle steal
ing operations where only the NMI input is latched. Using this pOint as a reference, a
delay of at least one bus cycle will occur before the interrupt is recognized by the pro
cessor.
1.1 1 .1 0.1 Non-Maskable Interrupt (NMI). A negative edge on this input requests that a
non-maskable interrupt sequence be generated. This input, as the name indicates, can
not be masked by software and has the highest priority of the three interrupt inputs. After
a reset has occurred, a NMI input will not be recognized by the processor until the first
program load of the hardware stack pointer. The entire machine state is saved on the
hardware stack during the processing of a non-maskable interrupt. This interrupt is inter
nally blocked after a hardware reset until the stack pOinter is initialized.
1 .1 1 .1 0.2 Fast Interrupt Request (FIRQ). This input is used to initiate a fast interrupt re
quest sequence. Initiation depends on the F (fast interrupt request mask) bit in the condi
tion code register being clear. This bit is set during reset. During the interrupt, only the
contents of the condition code register and the program counter are stacked resulting in
a short amount of time required to service this Interrupt. This interrupt has a higher priori
ty than the normal interrupt request (IRQ).
1.1 1 .1 0.3 Interrupt Request (IRQ). This input is used to initiate what might be considered
the "normal" interrupt request sequence. Initiation depends on the I (interrupt mask) bit
in the condition code register being clear. This bit is set during reset. The entire machine
state is saved on the hardware stack during processing of an IRQ input. This input has
the lowest priority of the three hardware interrupts.
1 .1 1 .11 MEMORY READ (MRDy) (MC6809). This input allows extension of the E and Q
clocks to allow a longer data access time. A low on this input allows extension of the E
and Q clocks (E high and Q low) in integral multiples of quarter bus cycles (up to 1 0
cycles) to allow interface with slow memory devices.
1-9
M emory ready does not extend the E and Q clocks d u ring non-va l id memory access
cycles and therefore the processor does not slow down for "don't care" bus accesses.
M emory ready may also be used to extend the E and Q clocks when an external device is
using the halt and d i rect memory access/bus request i n p uts.
1.11 .1 2 ADVANCED VALID MEMORY ADDRESS(AVMA)(MC8809E). This output signal in

d icates that the MC6809E wi l l use the bus In the fol lowing bus cycle. This output is low
when the MC6809E Is in either a halt or sync state.
1.11 .1 3 HALT. This i n put is used to halt the processor. A low i n put halts the processor at
the end of the present instruction execution cycle and the processor remains halted in
defin itely without loss of data.
When the processor is halted, the BA output is high to indicate that the buses are in the
h i g h-im pedance state and the BS output is also high to indicate that the processor is i n
t h e halt/bus g rant state.
During the halt/bus grant state, the processor will not respond to external real-time re
q uests such as FIRQ or IRQ. However, a d irect memory accesslbus request input wi l l be
accepted . A non-maskable Interrupt or a reset i n put wi l l be l atched for processing l ater.
The E and Q clocks conti n ue to run during the halt/bus grant state.
1.11.14 DIRECT MEMORY ACCESS/BUS REQUEST (DMAIBREQ) (MC8809). This input is

used to suspend program execution and make the buses available for another use such
as a direct memory access or a dynamic memory refresh.
A low level on this i nput occurring d uring the Q clock high time suspends instruct ion ex
ecution at the end of the current cycle. The processor ac �nowledges acceptance of this
i n put by setti ng the BA and BS outputs high to sign ify the bus grant state. The requesting
device now has up to 15 bus cycles before the processor retrieves the bus for self-refresh.
!n!!...c � di rect memory access controller w i l l req uest to use the bus by setting the
DMAIBREQ I nput low when E goes high. When the processor acknowledges this i n p ut by
setti ng the BA and BS outputs high, that cycle will be a dead cycle used to transfer bus
mastership to the direct memory access controller. False memory access d u ri ng any
dead cycle should be prevented by externally developing a system DMAVMA signa·1
which Is low in any cycle when the BA output changes.
When the BA output goes low, either as a result of a d irect memory access/bus request or
a processor self-refresh, the d irect memory access device should be removed from the
bus. Another dead cycle w i l l elapse before the processor accesses memory, to al low
transfer of bus mastership without contention.
1.1 1 .1 5 BUSY (MC8809E). This output ind icates that bus re-arbitration should be deferred
and provides the i ndlvisable memory operation required for a "test-and-set" pri m itive.
1-10
This output wi l l be high for the fi rst two cycles of any Read-Modify-Wrlte i n struction, h i g h
d u ring t h e fi rst byte o f a double-byte access, a n d h i g h d u r i n g t h e fi rst byte of any indirect
access or vector-fetch o peration.
1 .1 1 .16 POWER. Two i n puts are used to su pply power to the p rocessor: Vee i s + 5.0
± 5%, wh i le VSS is g round or 0 volts.
1-1111-12
SECTION 2
ADDRESSIN G MODES
2.1 INTRODUCTION
This section contains a description of each of the addressing modes available on these
processors.
2.2 ADDRESSING MODES
The addressing modes available on the MC6809 and MC6809E are: Inherent, Immediate,
Extended, Direct, Indexed (with various offsets and autoincrementing/decrementing),
and Branch Relative. Some of these addressing modes require an additional byte after
the opcode to provide additional addressing interpretation. This byte is called a postbyte.
The following paragraphs provide a description of each addressing mode. In these

descriptions the term effective address is used to indicate the address in memory from
which the argument for an instruction is fetched or stored, or fram which instruction pro·
cessing is to proceed.
2.2.1 INHERENT. The information necessary to execute the instruction is contained in

the opcode. Some operations specifying only the index registers or the accumulators,
and no other arguments, are also included in this addressing mode.
Example: MUL
2.2.2 IMMEDIATE. The operand is contained in one or two bytes immediately following
the opcode. This addressing mode is used to provide constant data values that do not
change during program execution. Both 8- bit and 16-bit operands are used depending on
the size of the argument specified in the opcode.
Example: LOA #CR
LOB #7
LOA #$FO
LOB #%1110000
LOX #$8004
Another form of immediate addressing uses a postbyte to determine the registers to be

manipulated. The exchange (EXG) and transfer (TFR) instructions use the postbyte as
shown in Figure 2-1(A). The push and pull instructions use the postbyte to designate the
registers to be pushed or pulled as shown in Figure 2-1(8).
2-1
b7 b6 b5 b4 b3 b2 bl bO
I SOURCE ( R l 1 DESTINAT I O N ( R21 I
Code- Register Code- Register
0000 D (A:BI 0101 Program Counter
000 1 X Index 1 000 A Accumulator
00 1 0 Y Index 1001 B Accumulator
001 1 U Stack Pointer 1010 Condition Code
0 1 00 S Stack Pointer 101 1 Direct Page
• All other combinations of bits produce undefined results.
(A) Exchange ( EXG) or Transfer (TFR) Instruction Postbyte
b7 b6 b5 b4 b3 b2 bl bO
I PC l s/ u I y I X I DP I B I A I cc I
PC = Program Counter
StU = Hardware/ User Stack Pointer
y = Y Index Register
X = U Index Register
DP = Direct Page Register
B = B Accumulator
A = A Accumulator
CC = Condition Code Register
(B) Push (PSH) or Pull ( PUll Instruction Postbyte
Figure 2·1. Post byte Usage for EXGrrFR, PSH/PU L Instructions
2.2.3 EXTENDED. The effective address of the argument is contained in the two bytes
fol lowing the opcode. I n structions using the extended addressing mode can reference
arg uments anywhere in the 64K add ressi ng space. Extended addressi ng is generally not
u sed i n position i ndependent programs because it suppl ies an absol ute add ress.
Example: LOA > CAT
2.2.4 DIRECT. The effective address is developed by concaten ation of the contents of the
d i rect page reg ister with the byte immediately fol lowi n g the opcode. The d i rect page
reg ister contents are the most·significant byte of the address. This allows accessi n g 256
l ocations withi n any one of 256 pages. Therefore, the enti re add ressing range i s avai l able
for access using a single two·byte instruct ion.
Example: LOA > CAT
2.2.S INDEXED. I n these addressing modes, one of the pOi nter reg i sters (X, V, U, or S), and
someti mes the program counter (PC) is u sed in the calculation of the effective add ress of
the i n struct ion operand. The basic types (and their variations) of i ndexed add ressing
avai lable are shown i n Table 2-1 along with the post byte conf i g u ration used .
2.2.S.1 Constant Offset from Register. The contents of the reg i ster deSignated i n the
post byte are added to a twos com plement offset val ue to form the effective add ress of
2-2
the instruction operand. The contents of the designated register are not affected by this
addition. The offset sizes available are:
No
offset designated register contains the effective
address
5-bit 16 to + 15
8·bit 128 to + 127
16-bit 32768 to + 32767
Table 2·1. Postbyte Usage for Indexed Addressing Modes
Mode Type Variation Direct Indirect

Constant Offset from Register No Offset l R R00 1 00 1 R R 1 0l 00
(twos Complement Offset) 5-B it Offset ORRnnnnn Defaults to 8-bit
8- Bit Offset l RR01000 l R R l l 000
1 6-Bit Offset l R R0100l 1 R R l l 00 l
Accumulator Offset from Register A Accumulator Offset l R ROOl l 0 l R R 10l l 0
(twos Complement Offset) B Accumulator Offset l R R0010l 1 R R 1 0l 0l
D Accumulator Offset 1 R R010l l l R R l l0l l
Auto I ncrement/ Decrement from I ncrement by 1 l R ROOOOO Not Allowed
Register I ncrement by 2 l R ROOOO l l R R 1 000 l
Decrement by 1 l R ROOO 1 0 N o t Allowed
Decrement by 2 1 R ROOO l l l R R 1 00l l
Constant Offset from Program 8- Bit Offset l XXOl l 00 1 XX 1 1 1 00
Counter 1 6-Bit Offset l XXOl l 0 l l XX l l l 0l
Extended I ndi rect 1 6- Bit Address - --.........- 1 001 1 1 1 1
The 5·bit offset value is contained in the postbyte. The 8· and 16·bit offset values are con·
tained in the byte or bytes immediately following the postbyte. If the Motorola assembler
is used, it will automatically determine the most efficient offset; thus, the programmer
need not be concerned about the offset size.
Examples: LOA ,X LOY - 64000, U
LOB O,Y LOA 17, PC
LOX 64,000,5 LOA There, PCR
2.2.5.2 Accumulator Offset from Register. The contents of the index or pOinter register
designed in the postbyte are temporarily added to the twos complement offset value con·
tained in an accumulator (A, B, or D) also designated in the postbyte. N either the
designated register nor the accumulator contents are affected by this addition.
Example: L OA A,X LOA O,U
LOA B,Y
2.2.5.3 Autoincrement/Decrement from Register. This addressing mode works in a

postincrementing or predecrementing manner. The amount of increment or decrement,
one or two positions, is designated in the postbyte.
2-3
I n the autoincrement mode, the contents of the effective address contai ned i n the
pOi nter reg ister, designated in the postbyte, and then the pOinter regi ster is automatical
ly incremented ; thus, the pOi nter reg ister is post incremented.
In the autodecrement mode, the poi nter reg ister, designated in the postbyte, is
automatical ly decremented fi rst and then the contents of the new address are used;
thus, the poi nter reg i ster is predecremented.
Exam ples: Autolncrement Autodecrement
LOA ,X + LOY ,X + + LOA ,-X LOY ,- -X
LOA ,Y + LOX ,Y + + LOA ,-V LOX ,- -Y
LOA ,5 + LOX ,U + + LOA ,-5 LOX ,- -U
LOA ,U + LOX ,5 + + LOA ,-U LOX ,- -5
2.2.5.4 Indirection. When using indirect ion, the effect ive address of the base i ndexed ad
dressing mode is used to fetch two bytes which contai n the final effective address of the
operand. It can be used with al l the i ndexed addressing modes and the program cou nter
rel ative addressing mode.
2.2.5.5 Extended Indirect. The effective address of the arg ument is located at the ad
dress specified by the two bytes fol low i n g the post byte. The postbyte is used to indicate
i n d i rection .
Example: LOA [$FOOO]
2.2.5.8 Program Counter Relative. The p rogram counter can also be used as a pOi nter
with either an 8- or 1 6-bit signed constant offset. The offset val ue is added to the program
cou nter to develop an effective address. Part of the post byte is used to indicate whether
the offset is 8 or 16 bits.
2.2.8 BRANCH RELATIVE. This addressing mode is used when branches from the c u rrent
i n struction location to some other locat ion relative to the current program counter are
des i red. If the test condition of the branch instruction is true, then the effective address
is calculated (program counter plus twos complement offset) and the branch is taken. If
the test condition i s false, the processor proceeds to the next in-l i ne instruction. Note
that the prog ram counter is always poi nting to the next instruction when the offset is ad
ded . Branch relative addressing is always used i n position independent programs for all
contro l transfers.
For short branches, the byte fol lowi n g the branch instruction opcode is treated as an
8-bit signed offset to be used to cal c u l ate the effective add ress of the next i n struction if
the branch i s taken . Th is is cal led a short relative branch and the range is l i m i ted to p l us
1 27 or m i n u s 1 28 bytes from the fol low i n g opcode.
For long branches, the two bytes after the opcode are used to calculate the effective ad
d ress. Th i s is cal led a long relative branch and the range is p l u s 32,767 or m i n us 32,768
2-4
bytes from the fol lowing opcode or the f u l l 64K address space of memory that the pro
cessor can add ress at one t i me.
Examples: Short Branch Long Branch
BRA PO LE LBRA CAT
2-5/2-6
SECTION 3
I NTERRUPT CAPABI LITI ES
3.1 INTRODUCTION
The M C6809 and MC6809E microprocessors have six vectored i nterrupts (th ree hardware
and three software). The hardware interrupts are the non-maskable interrupt (N M I), the
fast maskable interru pt req uest (FI RQ), and the normal maskable interru pt req uest (I RQ).
The software I nterrupts consist of SWI , SWI2, and SWI3. When an i nterrupt request is
acknowledged, all the processor registers are pushed onto the hardware stack, except i n
t h e case o f F I RQ where o n l y t h e program counter and t h e condition code register is sav
ed , and control is transferred to tl!!.! d dress1!!.1he interrupt vector. The p ri o rity of these
i nterrupts is, h i ghest to lowest, N M I , SWI , FI RQ, I RQ, SWI2, and SWI3. Figure 3-1 is a
detai l ed flowchart of i nterru pt processi n g i n these processors. The i nterrupt vector loca
tions are g iven in Table 3-1 . The vector locations contai n the address for the i nterru pt
routi ne.
Add itional information on the SWI , SWI2, and SWI3 interrupts is g iven in Appendix A. The
hardware i nterrupts, N M I , FI RQ, and I RQ are l i sted al phabetical ly at the end of Appendix
A.
Table 3·1. Interrupt Vector Locations
Interru pt Vector Location

Description MS Byte LS Byte
Reset (RESET) FFFE FFFF
Non-Maskable I nterrupt (NMi) FFFC FFFD
Software Interrupt �I l FFFA FFFB
Interrupt Request ( I RQ) FFF8 FFF9
Fast I nterrupt Request iFiRQ) FFF6 FFF7
Software I nterrupt 2 ( SWI2) FFF4 F F F5
Software Interrupt 3 ( SW I3) FFF2 FFF3
Reserved FFFO FFFl
3.2 NON-MASKABLE INTERRUPT (NMI)
The non-maskable i nterrupt is edge-sensitive i n the sense that if it is sam p led low one cy
cle after it has been sampled high, a non-maskable interrupt wi l l be triggered. Because
the non-maskable i nterrupt cannot be masked by execution of the non-maskable i nter
rupt handler routine, it is possible to accept another non-maskable interru pt before ex
ecut i ng the first instruct ion of the interru pt routine. A fatal error w i l l exist if a non
maskable i nterrupt is repeatedly al lowed to occur before completing the retu rn from i n
terru pt (RTI) instruction of the previous non-maskable interru pt req uest, si nce the stack
3-1
w i l l eventual ly overflow. Th is i nterrupt is especial ly appl icable to gai n i n g i m med iate p ro
cessor response for powerfa i l , software dynamic memory refresh , or other non-delayable
events.
3.3 FAST MASKABLE INTERRUPT REQUEST (FIRQ)
A low level on the F I RQ i nput with the F (fast i nterrupt req uest mask) bit i n the condit ion
code reg i ster clear triggers this i nterru pt seq uence. The fast i nterru pt req uest provides
fast i nterru pt response by stacking only the prog ram counter and condit ion code
reg i ster. Th i s al lows fast context switching with m i n imal overhead . If any reg i sters are
u sed by the i nterrupt routine then they can be saved by a single push i nstruct ion.
After accepti n g a fast interru pt req uest, the processor clears the E flag, saves the pro
g ram c2!:!IDer and cond ition code reg ister, and then sets both the I and F bits to mask any
f u rther I RQ and F I RQ i nterrupts. After servicing the ori g i nal interru pt, the user may selec
t ively clear the I and F bits to al low multi ple-level i nterrupts if so desired .
3.4 NORMAL MASKABLE INTERRUPT REQU EST (IRQ)
A low level on the I RQ input with the I (i nterru pt req uest mask) bit i n the cond ition code
reg i ster clear triggers this i nterru pt seq uence. The normal m askabl e i nterru pt req uest
p rovides a slower hardware response to i nterru pts because it causes the ent i re m ach i ne
state to be stacked . However, this means that i nterrupting software routi nes can use all
p rocessor resou rces without fear of damag ing the i nterrupted routine. A normal i nterru pt
request, havi n g lower priority than the fast i nterrupt request, i s prevented from i nterru p
t i n g the fast i nterru pt hand ler by the automatic sett i ng of the I bit by the fast i nterrupt re
q uest handler.
After accepti n g a normal i nterrupt req uest, the p rocessor sets the E flag, saves the ent i re
m achine state, and then sets the I bit to mask any further interrupt req uest i n puts. After
servicing the ori g i nal i nterrupt, the user may clear the I bit to al low m u lt i ple-level normal
i nterrupts.
All interrupt hand l i ng routi nes shou ld retu rn to the formerly executing tasks u s i n g a
ret u rn from i nterrupt (RiT) instruction. Th is i n st ruction recovers the saved mach ine state
f rom the hardware stack and control is retu rned to the i nterru pted program . If t he
recovered E bit is clear, it indicates that a fast i nterrupt req uest occurred and only the
program cou nter address and condition code reg ister are to be recovered.
3.5 SOFTWARE INTERRU PTS (SWI, SWI2, SWI3)
The software i nterru pts cause the processor to go through the normal i nterru pt request
sequence of stacking the complete mac h i ne state even though the i nterru pt i n g sou rce i s
the processor itself. These i nterru pts are com monly used for prog ram debugg i n g a n d for
cal l s to an operating system.
3-2
Normal p rocessing of the SWI i n put sets the I and F bits to p revent either of these i nter
ru pt req uests from affecting the com pletion of a software i nterrupt req uest. The remain
ing software interru pt request inp uts (SWI2 and SWI3) do not have the priority of the SWI
i n put and therefore do not mask the two hardware i nterru pt req uest i n puts (FI RQ and
I RQ).
3-3
r- - - - - - ~C6!!
~ --,
O-DPR
I-F,I
l-R/W
Clrimi
LogiC
DlsarmNm
----r---
L ___________ _
CWAI
Bus SIal8 BA I BS
Run",n o I 0
Interrupt or Reset Acknowledge o I 1
ync Acknowledge o
Halt Acknowledge
NOTES: 1. Asserting RESET will result in entering the reset sequence from any point in Ihe flowchart.
2. BUSY is high during first vector fetch cycle (MC6809EI.
Figure 3·1. Interrupt Processing Flowchart

SECTION 4
P ROG RAM MING
4.1 I NTRODUCTION
These processors are designed to be sou rce-code com patible with the M 6800 to m ake
use of the su bstantial existi n g base of M6BOO software and traini n g . However, this asset
sho u l d not overshadow the capab i l ities bu i lt i nto these processors that allow more
modern prog ram m i ng tec h n i q ues such as position-i ndependence, mod u lar programm
i n g , and reentrancy/recu rsion to be u sed on a m icroprocessor-based system. A brief
review of these methods is given in the fol l owing paragraphs.
4.1 .1 POSITION I N DEPENDENCE. A program is said to be "posit ion-independent" i f it

wil l run correct ly when the same machine code is positioned arbitrarily in memory. Such
a prog ram is u sef u l i n many d i fferent hardware configurations, and m ight be copied from
a d isk i nto RAM when the operat i ng system first sees a req uest to use a system util ity.
Pos it ion-i ndependent prog rams n ever use absol ute (extended or direct) add ressing: in
stead, i nherent i m med iate, register, i ndexed and rel ative modes are used . In particu l ar,
there should be no jump (absol ute) or j u m p to subroutine i nstruct ions nor sho u l d ab
sol ute addresses be used. A position-i ndependent prog ram is al most always preferable
to a position-d ependent program (although position-i ndependent code i s usually 5 to
1 0% slower than normal code).
4.1 .2 MO DULAR P ROG RAMM I N G . M od u lar prog ramm i ng is another indication of q ual ity
code. A mod u l e is a prog ram element which can be easily discon nected from the rest of
the prog ram either for re-use in a new environment or for replacement. A module is usual
ly a su broutine (although a subroutine i s not necessari ly a mod u le); freq uently, the p ro
g rammer isol ates reg ister changes i nternal to the module by pushing these reg isters
onto the stack u pon entry, and p u l l i ng them off the stack before the return. I so l at i n g
register changes i n t h e cal led mod u l e , to that mod u l e alone, allows t h e code i n the cal l
i n g program to be more eas i ly analyzed since it can be assumed that al l registers (except
those spec ifical l y used for parameter transfer are u nchanged by each cal led mod u le.
Th i s l eaves the processor's registers free at each level for loop counts, add ress com
parisons, etc.
4.1 .2.1 Local Storage. A clean m ethod for al locat i n g "local " storage is req u i red both by
position-i ndependent prog rams as wel l as mod u l ar prog rams. Local or temporary storage
is used to hold va l ues on ly d u ri n g execution of a mod ule (or cal l ed modu les) and is releas
ed u pon ret u rn . One way to al locate local storage is to decrement the hardware stack
4-1
pOinter(s) by the nu mber of bytes needed. I n terru pts w i ll then leave th i s area intact and i t
c a n b e de-allocated o n exit ing the module. A mod u l e wi ll almost always need more tem
porary storage than just the M PU regi sters.
4.1.2.2 Global Storage. Even in a modu lar envi ron ment there may be a n eed for "global"
val ues which are accessi ble by many modu l es wit h i n a gi ven system. These provide a
conven ient means for storing val u es from one i nvocat ion to another i nvocat ion of the
same routi n e. Global storage may be created as local storage at some level, and a
pOinter reg ister (usually U) used to pOi nt at this area. Th is register is passed u nchanged
i n al l subrouti n es, and may be used to i ndex i nto the global area.
4.1.3 REENTRANCY/RECURSION. Many programs w i l l eventually i n volve execution in an

i nterrupt-driven envi ronment. If the i nterrupt handlers are com plex, they m ight wel l cal l
the same routine wh ich has just been interrupted. Therefore, to protect present programs
against certai n obsolescence, al l programs should be written to be reentrant. A reentrant
routine allocates d ifferent local variable storage u pon each entry. Th us, a later entry
does not destroy the processing associated wit h an earl ier entry.
The same tec h n i que wh ich was implemented to allow reentrancy also allows recursion .
A recursive routine i s defined as a routine that cal l s itself. A recu rsive routine might be
written to simplify the solution of certai n types of problems, especially those wh ich have
a data structure whose elements may themselves be a structure. For exam ple, a paren
thet ical equat ion represents a case where the expression i n parenthesis may be con
sidered to be a val ue wh ich is operated on by the rest of the equation. A programmer
m ight choose to write an expression evaluator passing the parenthetical expression
(which m i g ht also contain parenthetical expressions) i n the call, and receive back the
retu rned value of th e expression wit h i n th e parenthesis.
4.2 M8809 CAPABILITIES
The followi ng paragraphs briefly explain how the MC6809 is used with the programmi ng
tech n i ques mentioned earl ier.
4.2.1 MODULE CONSTRUCTION. A module can be defined as a log ically self-contained

and discrete part of a larger program. A properly constructed mod u l e accepts well defi n
e d inputs, carries o u t a set o f processing actions, a n d produces a specified output. The
u se of parameters, local storage, and g lobal storage by a program mod u l e is g iven i n the
followi ng paragraphs. Si nce reg isters wi ll be used i nside the mod u l e (essentially a form
of local storage), the f i rst thing that is usually done at entry to a mod ule is to push (save)
them on to the stack. This can be done with one i n struction (e.g., PSHS Y, X, B, A). After
the body of the mod ule is executed, the saved registers are collected, and a subro ut i n e
retu rn i s performed, at o n e time, by p u l l i ng the program counter from t h e stack (e.g.,
PULS A,B,X,Y,PC).
4-2
4.2.1.1 Parameters. Parameters may be passed to or from modu l es eith er i n reg i sters, if
they will provi de sufficient storage for parameter passage, or on the stack. If parameters
are passed on the stack, they are placed there before call ing the lower level modu l e. The
called modu l e is then written to use local storage i n s i de the -stack as n eeded (e.g., ADDA
offset,S). Notice that the requ i red offset consists of the n u mber of bytes pushed (upon
entry), plus two from the stacked return address, plus the data offset at the t i me of the
call. Th is value may be calculated, by hand, by drawing a "stack pictu re" d i ag ram
representi n g module entry, and assi g n i n g conven i ent mnemonics to these offsets with
the assembler. Returned parameters replace those sent to the routi ne. If more
parameters are to be returned on the stack than would normal ly be sent, space for the i r
return is allocated by t h e call ing rout i n e before t h e act ual call (i f four additional bytes are
to be returned, the caller wou l d execute LEAS -4,S to acqu i re the additional storage).
4.2.1.2 Local Storage. Local storage space is acqu i red from the stack wh i le the present
rout i n e is executing and then returned to the stack prior to exit. The act of push i ng
reg isters which w i l l be used in later calcu l ations essentially saves those regi sters i n tem
porary local storage. Add itional local storage can easi ly be acqu i red from the stack e.g.,
executing LEAS -2048,S acqu i res a buffer area ru n n i ng from the O,S to 2047,S i nclusive.
Any byte in this area may be accessed d i rectly by any instruction which h as an i ndexed
addresing mode. At the en d of the routi ne, the area acqu ired for local storage is released
(e.g., LEAS 2048,S) prior to the fi nal pull . For c l eaner prog rams, local storage should be
allocated at entry to the module and released at the exit of the module.
4.2.1.3 Global Storage. The area requ i red for global storage is also most effecti vely ac
qu i red from the stack, probably by the h ighest level routi ne in the standard package.
Although this is local storage to the highest level routine, it becomes "global" by posi
tion i ng a reg ister to poi nt at this storage, (someti mes referred to as a stack mark) then
establishing the convention that all modu les pass that same pOi nter val u e when cal l i ng
lower level modu les. I n practice, it i s conve n ient to leave this stack mark reg i ster u n
changed i n all modules, especially if g lobal accesses are common. The highest level
routi n e in the standard package would execute the fol lowing sequence u pon ent ry (to i n
itialize t h e g lobal area):
PSHS U h i gh er level mark, i f any

TFR S,U n ew stack mark
LEAS -1 7,U a l locate global storage
Note that the U register now defines 1 7-bytes of locally allocated (permanent) g lobals
(which are -1 ,U through -17,U) as well as oth er external globals (2,U and above) which
have been passed on the stack by the routi n e which called the standard package. Any
global may be accessed by any modu l e usi n g exact l y the same offset value at any l evel
(e.g., ROL, RAT,U; where RAT EaU -1 1 h as been defi ned). Furthermore, the values stack
ed prior to i n voki ng the standard package may i nclu de pOi nters to data or I /O peri pherals.
Any i n dexed operat ion may be performed i n dexed i n di rect through those pOi nters, which
means, for example, that the module n eed know noth i n g about the actual hardw are con
f i gu rat ion, except that (upon ent ry) the pOi nter to an I/O register has been placed at a
gi ven location on the stack.
4-3
4.2.2 POSITION·INDEPENDENT CODE. Position-independent code means that the same
machine lang uage code can be placed anywhere in memory and sti l l function correctly.
The M6809 has a long relative (16-bit offset) branch mode along with the com mon
MC6800 branches, p l u s program-counter rel at ive addressi ng. Program-counter rel ative
addressing u ses the program counter l i ke an i ndexable reg ister, which allows all instruc
tions that reference memory to also reference data rel ative to the program counter. The
M6809 also h as load effect ive add ress (LEA) i n st ructions which al low the user to pOi nt to
data in a ROM in a position-independent man ner.
An i mportant rule for generat i n g position-independent code is: NEVER USE ABSOLUTE
ADDRESSI NG.
Program-cou nter relative addressing on the M6809 is a form of i ndexed addressing that
uses the prog ram cou nter as the base reg ister for a constant-offset i ndexi ng operation.
However, the M6809 assembler treats the PCR address field differently from that used in
other i ndexed instructions. I n PCR addressing, the assembly t i me location val ue i s sub
tracted from the (con stant) value of the PCR offset. The resulting distance to the desi red
symbol is the val ue placed i nto the machine language object code. During execution, the
processor adds the value of the run time PC to the d i stance to get a posit ion-independent
absol ute add ress.
The PCR indexed add ressing form can be used to poi nt at any locat ion relati ve to the pro
g ram regard l ess of position in memory. The peR form of i ndexed addressing al lows ac
cess to tables with i n the program .s pace in a position-independent manner via use of the
load effective address instruction.
I n a program which is completely position-i nd$pendent, some absol ute locations are
usual ly requi red, particularly for I /O. If the locations of I /O devices are placed on the
stack (as g lobals) by a small set u p rout ine before the standard package Is invoked, all in
ternal mod ules can do their I /O through that pOi nter (e.g., STA [ACIAD, UD, al lowing the
hardware to be eas i ly changed, i f desi red . Only the Single, smal l , and obvious set u p
rout ine need b e rewritten for each different hardware confi g u rat ion.
Global, permanent, and temporary values need to be eas i ly available in a position

i ndependent manner. Use the stack for this data s i nce the stacked data is d i rectly ac
cessible. Stack the absol ute address of I /O devices before cal l ing any standard software
package s i nce the package can use the stacked addresses for I /O in any system.
The LEA instructions al low access to tables, data, or i mmediate val ues i n the text of the
program in a position-i ndependent manner as shown i n the fol lowing example:
LEAX MSG1 , PCR

LBSR PDATA
MSG1 FCC IPRI NT THIS !I
4-4
Here we wish to pOint at a message to be pri nted from the body of the program. By
writing "MSG1 , peR" we s i gnal the assembler to compute the distance between the pre
sent address (the address of the LBSR) and MSG1 . Th is resu lt is inserted as a constant
i nto the LEA instruction which wi l l be indexed from the program counter value at the t i me
of execution. Now, no matter where the code i s located, when i t is executed the com
p uter offset from the program cou nter wi ll poi nt at MSG1 . Th is code is position
i n dependent.
It is common to use space in the hardware stack for temporary storage. Space is made
for temporary variables from O,S through TEMP-1 , S by decrement i n g the stack pOi nter
equal to the len gth of requ i red storage. We could u se:
LEAS -TEMP,S.
Not only does this facil itate position-i ndependent code but i t is structured and helps
reentrancy and recursion.
4.2.3 REENTRANT PROGRAMS. A program that can be executed by several d ifferent

users shari n g the same copy of it in memory is called reentrant. Th is is i mportant for i n
terrupt driven systems. This method saves considerable memory space, especi a l ly with
l arge i nterrupt routi nes. Stacks are requ i red for reentrant programs, and the M6809 can
su pport up to four stacks by usi n g the X and Y i ndex registers as stack poi nters.
Stacks are simple and convenient mechanisms for generati n g reentrant programs.
Subrouti nes wh ich use stacks for pass i n g parameters and results can be easily made to
be reentrant. Stack accesses use the i ndexed addressing mode for fast, efficient execu
tion. Stack addressi n g is qu ick.
Pure code, or code that is not self-modifying, is mandatory to produce reentrant code. No
i nternal i nformation within the code Is subject to modification . Reentrant code never has
i nternal tem porary storage, is sim pler to debug, can be placed i n ROM, and must be i nter
ruptable.
4.2.4 RECURSIVE PROGRAMS. A recu rsive program is one that can call itself. They are
quite conven ient for parsing mechanisms and certain arithmetic functions such as com
puting factorials. As with reentrant programmi ng, stacks are very usef u l for this techni
que.
4.2.5 LOOPS. The usual structured loops (i.e., REPEAT ... UNTIL, WHI LE ... DO, FOR ... , etc.)
are avai lable In assembly language i n exactly the same way a h i gh-level language com
piler cou ld translate the construct for execution on the target machine. Using a
FOR...NEXT loop as an example, it is possi ble to p ush the loop count, i ncrement value,
and termi nation val ue on the stack as variables local to that loop. On each pass through
the loop, the worki ng register is saved, the loop count picked up, the increment added i n ,
a n d t h e resu lt compared to t h e termi nation value. Based o n t h i s comparison, t h e loop
counter might be u pdated, the worki n g register recovered and the loop resumed, or the
workin g register recovered and the loo p variables de-allocated. Reasonable macros
4-5
cou ld m ake the sou rce form for loop trivial , even i n assembly l an guage. Such m acros
might red uce errors resu lt i n g from the u se of m u lt i ple i n structions sim ply to i m pl ement a
standard control structure.
4.2.6 STACK PROGRAMMING. Many microprocessor applications requ i re data stored as

cont i n g uous pieces of i nformation i n memory. The data may be temporary, that is, sub
ject to change or it may be permanent. Tem porary data w i l l most li kely be stored in RAM.
Permanent data w i ll most l i kely be stored i n ROM.
It i s i m portant to al low the main program as well as su brouti nes access to this block of
data, especially if arg uments are to be passed from the mai n program to the subrouti nes
and vice versa.
4.2.6.1 M6809 Stacking Operations. Stack pOi nters are markers which poi nt to the stack
and its i nternal contents. Although a l l fou r i ndex reg i sters may be used as stack
regi sters, the S (hardware stack pointer) and the U (user stack pOi nter) are generally
preferred because the push and pull instructions apply to these regi sters. Both are 16-bit
i ndexable registers. The processor uses the S reg i ster automatically d u ring i nterrupts
and subroutine cal ls. The U register is free for any purpose needed. It i s not affected by
i nterrupts or subroutine cal ls i mplemented by the hardware.
Either stack poi nter can be specified as the base address in i ndexed addreSSi ng. One u se
of the i n d i rect addressing mode uses stack poi nters to al low addresses of d ata to be
passed to a subrouti n e on a stack as argu ments to a subrouti n e. The subroutine can now
reference the data with one instruction. Hi gh-level language cal l s that pass argu ments
by reference are now more efficiently coded. Also, each stack push or pull operation in a
program u ses a post byte wh ich specifies any register or set of regi sters to be pushed or
p u lled from either stack. With this option, the overhead associated with subroutine call s
i n both assembl y a n d high-level language program s i s greatly decreased. I n fact, with the
large n u m ber of i n st ructions that use autoincrement and autodecrement, the M6809 can
em u l ate a true stack computer architectu re.
Using the S or U stack poi nter, the order i n which the reg isters are pushed or pu l led i s
shown i n Figure 4-1. Not ice that w e push "onto" the stack towards decreas i n g memory
locations. The program cou nter is pushed fi rst. Then the stack poi nter is decremented
and the "other" stack pOi nter is pushed onto the stack. Decrement i ng and stori ng con
t i n ues u nt i l all the reg isters requested by the postbyte are pushed onto the stack. The
stack pOi nter pOi nts to the top of the stack after the push ope ration.
The stacki n g order i s specified by the processor. The stacki ng order is identical to the
order used for all hardware and software i nterrupts. The same order is used even if a
subset of the reg i sters i s p ushed.
Without stacks, most modern block-structured h i gh -level languages would be c um ber

some to i m plement. Subroutine l i n kage is very i m portant in h i g h-level language genera
tion. Paragraph 4.2.6.2 describes how to use a stack mark pOi nter for this i m portant task.
4-6
Good prog rammi ng pract ice dictates the use of the hardware stack for temporary
storage. To reserve space, decrement the stack poi nter by the amount of storage re
qu i red with the i n struction LEAS -TEMPS, S. Th i s instruction makes space for tem
porary variables from 0,5 through TEMPS -1,5.
Memory
=R ·
...
Stack Pointer
After Stacking
- CC } Condition Code Register Contents
A } A Accumu lator Contents

B } B �ccumulator Contents
DP } Direct Page Register Contents
-
X.H
X.L
-
} X Contents
-
.Y .H
Y. L
- } Y Contents
U . H or S .H
-
�
U . L or S . L .
} Other Stack Pointer Contents
-
PC.H
PC. L
- } P rogram Counter Contents
Stack Pointer
..
Before Stacking
·
. · .
Figure 4·1 . Stacking Order
4.2.6.2 Subroutine Linkage. In the h ighest level routi ne, global variables are someti mes
considered to be local. Therefore, global storage is al located at this poi nt, but access to
these same variables requ ires different offset val ues dependi ng on s u brouti n e dept h .
Because subroutine depth chan ges dynamically, the length may not b e known
beforehan d . Th is problem is solved by ass i g n i ng one pOi nter (U will be u sed i n the fol low
ing descri ption, but X or Y could also be used) to "mark" a location on the hardware stack
by using the instruct ion TFR S,U. If the prog rammer does this i mmediately prior to
allocating g lobal storage, then all variables will then be available at a constant n egat i ve
offset location from this stack mark. I f the stack i s marked after the g lo bal variables are
4-7
al located, then the g lobal variables are avai lable at a constant positive offset from U .
Reg ister U is then cal led the stack mark pOi nter. Recall that the hardware stack poi nter
m ay be modi fied by hardware i nterrupts. For this reason, i t i s fatal to use data referred to
by a negative offset with respect to the hardware stack pOi nter, S.
4.2.6.3 Software Stacks.If more than two stacks are needed, autoincrement and
autodecrement mode of addressi n g can be used to gen erate addi ti onal software stack
pOi n ters.
The X, Y, and U i n dex regi sters are qu i te useful i n loops for i ncrementi ng and decremen
t i ng pu rposes. Th e pOi nter is used for searching tables and also to move data from one
area of memory to another (block moves). Th is auto i ncrement and autodecremen t
feature i s available i n the i ndexed addressi ng mode of the M6809 to fac i l itate such opera
t ions.
In autoi ncrem ent, the value contained i n the i ndex reg i st er (X or Y, U or S) is used as the
effective address and then the reg ister i s i nc remen ted (post i ncremen ted). I n autodecre
ment, the i n dex reg i ster is f i rst decremented and then used to obtai n the effecti ve ad
d ress (predecremented). Postincremen t or predecrement is always performed in this ad
d ressing mode. Th i s is equ i valent in operation to the push and p u l l from a stack. Th i s
equ i valence allows the X and Y i n d ex reg i sters to be used a s software stack pOi n ters. The
i ndexed addressi ng mode can a l so i mplement an extra level of post i n di rection. Thi s
feature supports parameter and pOi nter operations.
4.2.7 REAL TIME PROGRAMMING. Real t i me programmi ng requ ires special care.
Someti mes a peri pheral or task demands an i mmediate response from the processor,
other t i mes it can wait. Most real t i me app l i cat ions are demanding in t erms of processor
response.
A common solution is to use the i n terru pt capab i l i ty of the processor in solvi ng real ti me
p roblems. I nterru pts mean just that; they request a break i n the cu rrent sequence of
events to solve an asynch ronous service request. The system designer must consider all
vari at ions of the conditions to be encountered by the system i n c l u ding software i nterac
t ion w i th i n terrupts. As a resu lt, probl ems d u e to software design are more common in i n
terrupt i mplementation code for real t i me programmi ng than most other situations. Soft
ware timeou ts, h ardware i nterrupts, and program control i n terru pts are typically used i n
solving real t i m e prog ramming problems.
4.3 PROGRAM DOCUMENTATION
Common sense dictates that a wel l docu mented prog ram is mandatory. Comments are
needed to explai n each g roup of i nstructions si nce thei r use i s not always obvious from
l ooking at the code. Program bou n daries and branch i n structions n eed full clarificatio n .
Consider the fol lowing pOi nts when writi n g comments: u p-to-date, acc uracy, com
pl eteness, conciseness, and u n derstandab i l ity.
4-8
Accu rate docu mentation enables you and others to maintai n and adapt programs for u p
dat i n g and/or addi tional use with other programs.
The follow i n g program documentation standards are suggested.

A) Each su broutine should have an associated header block contain i n g at least the
followi n g elements:
1 ) A full specification for th is subroutine - includi n g associated data struc
tures - such that replacement code cou l d be generated from this descri ption
alone.
2) All usage of memory resou rces must be defi ned, i nclu ding:
a) Al l RAM needed from temorary (local) storage used duri ng exec ution of
this subroutine or called subrouti nes.
b) All RAM needed for permanent storage (used to transfer values from one
execution of the subrout i n e to future executions).
c) All RAM accessed as global storage (used to transfer values from or to
h i gher-level subroutines).
d) All possible exit-state conditions, if these are to be used by calli n g
routines t o test occurrences i nternal to t h e subrouti ne.
B) Code i nternal to each subrout ine shou l d h ave sufficient associated li ne com
ments to help i n u n derstandi ng the code.
C) All code must be non-self-modifying and position-i n dependent.
D) Eac h su broutine which i nclu des a loop m ust be separately documented by a
flowchart or pseudo h i gh-level language algorithm.
E) Any modu le or su broutine should be executable start i n g at the fi rst locat ion and
exit at the last location.
4.4 I N STRUCTION SET
The complete i n struction set for the M6809 is gi ven in Table 4-1.
Table 4·1 . Instruction Set
Instruction Description
ABX Add Accumulator B into Index Register X
ADC Add with Carry into Register
ADD Add Memory into R egister
AND logical A N D Memory into Register
ASl Arithmetic Shift left
ASR Arithmetic Shift R ight
BCC Branch on Carry Clear
BCS Branch on Carry S et
BEQ Branch on Equal
BGE Branch on Greater Than or Equal to Zero
BGT Branch on Greater
BH I Branch if H igher
BH S Branch if H igher or S ame
BIT Bit Test
BlE Branch if less than or Equal to Zero
4-9
Table 4·1. Instruction Set (Continued)
B LO Branch on Lower
B LS Branch on Lower or Same
B LT Branch on Less than Zero
BMI Branch on Minus
BNE Branch N ot Equal
BPL Branch on Plus
BRA Branch Always
BRN Branch Never
BSR Branch t o Subroutine
BVC Branch on Overflow Clear
BVS B ranch on Overflow Set
CLR Clear
CMP Compare Memory from a Register
COM Complement
CWAI Clear CC bit's and Wait for Interrupt
DAA Decimal Addition Adjust
D EC Decrement
EOR Exclusive OR
EXG Exchange Registers
INC I ncrement
J MP J ump
JSR J ump to Subroutine
LD Load Register from Memory
LEA Load Effective Address
LSL Logical Shift Left
LS R Logical S hift Right
MU L Multiply
N EG Negate
NOP No Operation
OR Inclusive OR Memory into Register
PSH Push Registers
PUL Pull Registers
ROL Rotate Left
ROR Rotate Right
RTI Return from Interrupt
RTS Return from Subroutine
SBC S ubtract with Borrow
S EX Sign Extend
ST Store Register into Memory
SUB Subtract Memory from Register
SWI Software I nterrupt
SYNC Synchronize t o External Event
TFR Transfer Register to Register
TST Test
4-10
The instruction set can be functional ly divi ded i n to five categories. They are:
8-Bit Accumulator and Memory Instructions
16-Bit Accumulator and Memory I nstructions
I ndex Reg ister/Stack Pointer I nstructions
Branch Instructions
Miscellaneous I nstructions
Tables 4-2 th rough 4-6 are l isti n gs of the M6809 instructions and th eir variations grouped
i nto the five categories l isted.
Table 4·2. 8·Bit Accum ulator and Memory Instructions
ADCA, ADCB Add memory to accumulator with carry
ADDA, A D D B Add memory t o accumulator
AN DA, A N D B And memory with accumulator
ASL, A S LA , A S L B Arithmetic shift of accumulator or memory left
A S R , A S R A , AS R B Arithmetic shift o f accumulator o r memory right
BITA, BITB Bit test memory with accumulator
CLR, CLRA, C L R B Clear accumulator or memory location
CMPA, CMPB Compare memory from accumulator
COM, COMA, COMB Complement accumulator or memory location
DAA Decimal adjust A accumulator
DEC, D ECA, DECB Decrement accumulator or memory location
EO R A , EO R B Exclusive o r memory with accumulator
EXG R l , R 2 Exchange R l with R 2 ( R l , R2", A, B, CC, DP)
I N C, I N CA, INCB I ncrement accumulator or memory location
LOA, LOB Load accumulator from memory
LSL, LSLA, LSLB Logical shltt lett accumulator or memory location
LS R , L S R A , L S R B Logical shift right accumulator o r memory location
MUL U nsigned multiply ( Ax B-D)
N E G , N EG A , N EG B Negate accumulator o r memory
ORA, O R B O r memory with accumulator
ROL, R O LA, R O L B Rotate accumulator or memory left
ROR, RORA, RORB Rotate accumulator o r memory right
S BCA, S BCB Subtract memory from accumulator with borrow
STA, S T B Store accumulator to memroy
S U BA, S U B B S ubtract memory from accumulator
TST, TSTA, TSTB Test accumulator or memory location
TFR R l , R2 Transfer Rl to R2 ( R l , R2",A, B, CC, D P )
NOTE: A, B, C C , or D P may b e pushed t o (pulled from) either stack with P SH S , PS HU

( P U LS , P U LU ) instructions.
4·11
Table 4·3. 16·Bit Accumulator and Memory Instructions
ADDD Add memory t o D accumulator
CMPD Compare memory from D accumulator
EXG D, R Exchange D with X, y, S, U, or PC
LDD Load D accumulator from memory
S EX Sign Extend B accum ulator into A accumulator
STD Store D accum ulator to memory
SUBD Subtract memory from D accumulator ...
TFR D, R Transfer D to X, Y, S, U, or P C
TFR R , D Transfer X, Y, S , U, or PC to D
NOTE: D may be pushed (pulled) to either stack with PSHS, PSHU ( P U LS, P U L U )
instructions.
Table 4·4. Index/Stack Pointer Instructions
CMPS, CMPU Compare memory from stack pointer
C M PX, C M P Y Compare memory from index register
EXG R 1 , R2 Exchange D, x, Y, �, U or PC Wltn D, x, Y, 5, U or PC
LEA S , LEAU Load effective address into staCk·pointer
LEAX, LEAY Load effective address into index register
LDS, LDU Load stack pointer from memory
LDX, LDY Load index register from memory
PSHS Push A, B, CC, DP, D, X, Y, U, or P C onto hardware stack
P SH U Push A, B, CC, D P , D , X, Y , X , or PC onto user stack
P U LS Pull A, B, CC, DP, D, X, Y, U, or PC from hardware stack
P U LU Pull A, B, CC, DP, D, X, Y, S, or PC; from hardware stack
STS, STU Store stack pointer to memory
STX, STY Store index register to memory
TFR R 1 , R2 Transfer D, X, Y, S, U, or PC to D, X, Y, S, U, or PC
ABX Add B accumulator to X ( unsigned)
4·1 2
Table 4·5. Branch Instructions
Instruction I Description
SIMPLE BRANCHES
B EQ, lBEQ B ranch if equal
B N E, l B N E B ranch i f not equal
B M I, l B M I B ranch i f minus
B Pl,lBPl B ranch if plus
BCS, lBCS B ranch if carry set
BCC, lBCC Branch if carry clear
BVS, lBVS Branch if overflow set
BVC, lBVC Branch if overflow clear
SIGNED BRANCHES
BGT, lBGT B ranch if greater (signed)
BVS, lBVS B ranch if invalid twos complement result
B G E, l B G E B ranch i f greater t h a n or equal (signed)
BEQ, l B EQ B ranch if equal
B N E, l B N E B ranch i f n o t equal
B lE, lBlE B ranch if less than or equal (Signed)
BVC, lBVC B ranch if valid twos complement result
B lT,l B lT B ranch if less than (Signed)
UNSIGNED BRANCHES
B H I ,l B H I B ranch i f higher ( unsigned)
B CC, lBCC B ranch if higher or same ( unsigned)
B H S,lB H S B ranch i f higher or same ( unsigned)
B EQ, lBEQ B ranch if equal
B N E, l B N E B ranch i f n o t equal
B lS, lBlS B ranch if lower or same ( unsigned)
BCS, lBCS B ranch if lower ( unsigned)
B lO, lBlO Branch if lower (unsigned)
OTHER B RANCHES
B S R, lBSR B ranch to subroutine
BRA,lBRA B ranch always
BRN, lBRN B ranch never
Table 4·6. Miscellaneous Instructions
ANDCC A N D condition code register
CWAI AND condition code register,then wait for interrupt
NOP N o operation
ORCC OR condition code register
JMP Jump
JSR Jump to subroutine
RTI Retum from interrupt
RTS Retum from subroutine
SWI, SWI2, SWI3 Software interrupt (absolute indirect)
SYNC Synchron ize with interrupt line
4-13/4-14
APPENDIX A
INSTRUCTION SET DETAILS
A.1 INTRODUCTION
This appendix contains detailed information about each instruction in the MC6809 in
struction set. They are arranged i n an alphabetical order with the mnemonic head ing set
in larger type for easy reference.
A.2 NOTATION
I n the operation description for each instruction, symbols are used to indicate the opera
tio n . Table A-1 l ists these symbols and their meanings. Abbreviations for the various
registers, bits, and bytes are also used . Table A-2 l ists these abbreviations and their
meani ngs.
Table A·1. Operation Notation
� Meaning
Is transferred to
A Boolean A N D
V Boolean O R
• Boolean exclusive O R
(Overlinel Boolean NOT
Concatenation
+ Arithmetic plus
Arithmetic minus
X Arithmetic multiply
A-1
Table A·2. Register Notation
Abbreviation Meaning
ACCA or A Accumulator A
ACCB or B Accumulator B
ACCA:ACCB or 0 Double accumulator 0
ACCX Either accumulator A or B
CCR or CC Condition code register
D P R or DP Direct page register
EA Effective add ress
I FF If and only if
IX or X I ndex register X
I Y or Y I ndex register Y
LSN Least significant nibble
M Memory location
MI Memory immediate
MSN M ost significant nibble
PC Program counter
R A register before the operation
R' A register after the operation
TEMP Temporary storage location
xxH Most signifcant byte of any 16-bit register
xxL Least significant byte of any 1 6-bit register
Sp or S Hardware Stack pointer
Us or U User Stack pointer
P A memory argument with Immediate, Di
rect,Extended, and Indexed addressing
modes
Q A read-modify-write argument with Direct,
I ndexed, and Extended addressing modes
( ) The data pointed to by the enclosed
( 1 6-bit address)
dd �bit branch offset
DODD 16-bit branch offset
I Immediate value follows
$ Hexadecimal value follows
[ 1 I ndirection
I ndicates indexed addressing
A-2
ABX Add Accumulator B into Index Register X ABX
Source Form: ABX
Operation: IX' - IX + ACCB
Condition Codes: Not affected .
Description: Add the a·bit unsigned val ue in acc u m u l ator B i nto i ndex reg ister X.
Addressing Mode: I nherent
A·3
ADC Add with Carry into Register A DC
Source Forms: ADCA P; ADCB P
Operation: R' - R + M + C
Condition Codes: H - Set if a half-carry is generated ; cl eared otherwise.

N - Set if the result is negat ive; c leared ot herwise.
Z - Set if the result i s zero; c l eared otherwise.
V - Set if an overflow is generated ; cleared ot herwise.
C - Set if a carry i s generated ; cleared otherwise.
Description: Adds the contents of the C (carry) bit and the memory byte i nto an
8-bit acc u m u l ator.
Addressing Modes: I mmed i ate

Extended
Di rect
Indexed
A-4
A D D (8- Bit) Add Memory into Register AD D (8- Bit)
Source Forms: ADDA P; ADDB P
Operation: R' - R + M
Condition Codes: H - Set if a half-carry i s generated ; c leared otherwise .

N - Set if the resu lt i s negative; cleared otherwise.
Z - Set if the resu lt i s zero; cleared otherwise.
V - Set if an overflow is generated; c leared otherwise.
C - Set if a carry is generated; cleared otherwise.
Description: Adds the memory byte i nto an a-bit acc u m u l ator.
Addressing Modes: I m mediate

Extended
Di rect
I ndexed
A-5
A D D (16-Bit) Add Memory into Register AD D (16-Bit)
Source Forms: ADDD P
Operation: R' - R + M : M + 1
Condition Codes: H - N ot affected .

N - Set if the resu lt is negative; cl eared ot herw i se.
Z - Set if the result is zero; cl eared otherwise.
V - Set if an overflow is generated ; cl eared otherwise.
C - Set if a carry is generated ; cleared ot herwise.
Description: Adds the 1 6·bit memory val ue into the 1 6·bit acc u m u l ator
Addressing Modes: I mmed iate

Extended
D i rect
I ndexed
A·6
AN D Logical AN D Memory into Regi ster AN D
Source Form s: A N DA P; AN DB P
Operation: R' - RAM

N - Set if the resu lt is negat ive; cleared otherw i se.
Z - Set if the resu lt is zero; c l eared ot herwise.
V - Always c leared .
C - N ot affected .
Description: Performs the logical AN D operat ion between t h e contents of an ac·

c u m u l ator and the contents of memory locat ion M and the result i s
stored i n t h e acc u m u l ator.
Addressing Modes: I m m ed i ate

Extended
D i rect
I ndexed
A·7
AN D Logical AND Immediate Memory Into Condition Code Register AN D
Source Form: A N DCC #xx
Operation: A' - AA MI
Condition Codes: Affected accord ing to the operation.
Description: Performs a logical AN D between the cond ition code reg ister and the
i m med i ate byte specified in the i n struction and places the result in
the condition code reg ister.
Addressing Mode: I mmed i ate
A-a
ASL Arithmetic Shift Left AS L
Source Forms: AS L Q; AS LA; AS LB
Operation: c+-I I I I I I I I 1- 0
..
b7 bO
Condition Codes: H - Undef ined
N - Set if the result is neg at ive; cleared ot herwise.
Z - Set if the result is zero; c l eared otherw i se.
V - Loaded with the res u lt of the exc l usive OR of bits s i x and
seven of the ori g i nal o perand .
C - Loaded with bit seven of the ori g inal operan d .
Description: Sh i fts a l l bits of the operand one place to the l eft. Bit zero is loaded
with a zero. Bit seven is sh i fted into the C (carry) bit.
Addressing Modes: I nherent

Extended
Di rect
I ndexed
A-9
AS R Arithmetic Shift Right AS R
Source Forms: ASR Q; ASRA; ASRB
Operation:
�""""rl----
b7
-r �
-r- -'Ir---T'I---r-I--'1 -. c
bO
Condition Codes: H - U ndefi ned.

N - Set if the result is negat ive; c leared otherwise.
Z - Set if the result is zero; c leared otherw i se.
V - Not affected.
C - Loaded with bit zero of the ori g i nal operand.
Description: Shifts al l bits of the operand one pl ace to the right. Bit seven i s held
constant. Bit zero i s shifted i nto the C (carry) bit.

Extended
Direct
I ndexed
A·1 0
Bee Branch o n Carry Clear Bee
Source Forms: BCC dd; LBCC DODD
Operation: TEM P - M I
I F F C = 0 then PC' - PC + TEM P
Description: Tests the state of the C (carry) bit and causes a branch if it is c l ear.
Addressing Mode: Rel at ive
Comments: Equ ivalent to B H S dd; LBHS DODD
A-11
B CS Branch on Carry Set BCS
Source Forms: BCS dd; LBCS DODD
I F F C=1 then PC' - PC + TEM P
Description: Tests the state of the C (carry) bit and causes a branch if it is set.
Addressing Mode: Relat ive
Comments: Eq uivalent to BLO dd; LBLO DODD
A-12
B EQ Branch on Equal B EQ
Source Forms: B EQ dd; LBEQ DODD
Operation: T EM P - M I
I F F Z = 1 then PC' - PC + TEM P
Condition Codes: N ot affected .
Description: Tests the state of the Z (zero) bit and causes a branch if it is set .
When used after a su btract or compare operation, this i n struction
will branch if the com pared val ues, sig ned or unsig ned, were exact ly
the same.
A·1 3
BG E Branch on G reater than or Equal to Zero BG E
Source Forms: BG E dd; LBG E DODD
I FF [NeV1 = O then PC' - PC + TEM P
Description: Causes a branch if the N (negat ive) bit and the V (overflow) bit are
either both set or both clear. That is, branch if the sign of a val id
twos com plement resu lt is, or woul d be, positive. When u sed after a
subtract or compare operation on twos com plement val ues, t h i s in
struction will branch if the reg i ster was g reater than or eq ual to the
memory operand.
A-1 4
BGT Branch on Greater BGT
Source Forms: BGT dd; LBGT DODD
I FF Z A [N eV] = O then PC' - PC + TEM P
Description: Causes a branch if the N (negative) bit and V (ove rflow) bit are either
both set or both clear and the Z (zero) bit is c lear. I n other words,
branch if t he s i g n of a val id twos com p lement result is, or wou l d be,
posit ive and not zero. When used after a subt ract or com pare opera
tion on twos complement val ues, t h i s i nstruction wi l l branch if the
reg i ster was g reater than the memory operand.
A-15
BHI Branch if Higher BHI
Source Forms: B H I dd; LBH I DODD
I FF [C v Z] = 0 then PC' - PC + TEMP
Description: Causes a branch if the previous operation caused neither a carry nor
a zero result. When used after a subtract or compare operat ion on
unsigned binary val ues, t h i s instruct ion w i l l branch if the reg ister
was h i gher than the memory operand.
Addressing Mode: Relative
Comments: Generally not usef u l after I NC/DEC, LDITST, and TST/CLR/CO M i n

struct ions.
A-1 6
BHS Branch if Higher or Same BHS
Source Forms: BHS dd ; LBHS DDDD
I F F C = O then PC' - PC+M I
Description: Tests the state of the C (carry) bit and causes a branch if it is c l ear.
When used after a subt ract or com pare on unsigned binary val ues,
t h i s i n struct ion w i l l branch if the reg i ster was h i gher than or the
same as the memory operand.
Comments: Th i s is a d u p l icate assembly-lang uage m nemonic for the single

mach i n e i n st ruction BCC. Generally not useful after I NC/DEC,
LD/ST, and TST/CLR/COM instruct ions.
A-1 7
B IT Bit Test BIT
Source Form: Bit P
Operation: TEM P - RAM
Condition Codes: H - Not affected.

N - Set if the resu lt is negat ive; cleared otherwise.
Z - Set if the res u lt is zero; c leared otherwise.
V - Always cleared .
C - Not affected .
Description: Performs the log ical AN D of the contents of accu m u l ator A or B and
the contents of memory location M and mod ifies the cond ition
codes accord i n g ly. The contents of accu m u l ator A or B and memory
locat ion M are not affected .
Addressing Modes: Immed iate

Extended
Di rect
I ndexed
A·1 8
BlE Branch on Less than or Equal to Zero BlE
Source Forms: BlE dd; lBlE DO D D
Operation: TEM P-M I

I F F Z v [N ED V] = 1 then PC'-PC + TEM P
Description: Causes a branch if the exclusive OR of the N (negative) and V

(overflow) bits is 1 or if the Z (zero) bit is set . That i s , branch i f the
sign of a val id twos com plement result is, or wou ld be, negat ive.
When used after a subtract or com pare operation on twos com p l e
ment val ues, t h i s i n struct ion wi l l branch if the reg i ster was less than
or equal to the memory operand .
A-19
BlO Branch on Lower BlO
Source Forms: BLO dd; LBLO DODD
Operation: TEMP - MI
I FF C=1 then PC'-PC+TEMP
Condition Codes: Not affected.
Description: Tests the state of the C (carry) bit and causes a branch if it is set.
When used after a su btract or compare on unsigned bin ary val ues,
this instruction wil l branch if the register was lower than the
memory operand.
Comments: This is a du plicate assembly-language mnemon ic for the single

mach ine instruction BCS. General l y not useful after INC/DEC,
LD/ST, and TST/CLR/COM i n structions.
A-20
BLS Branch on Lower or Same BLS
Source Forms: BLS dd; LBLS DOD D
I FF (C v Z) = 1 then PC' - PC + TEM P
Description: Causes a branch if the previous operat ion caused either a carry or a
zero result. When used after a subtract or compare operat ion on u n
s i gned binary val ues, t h is i n struction w i l l branch if the reg ister was
lower than or the same as the memory operand.
Comments: Generally not useful after I N C/DEC, LD/ST, and TST/CLR/COM i n

structions.
A-21
Bll Branch on Less than Zero Bll
Source Forms: BLT dd; LBLT DODD
Operation: TEMP-MI
IFF [NeV]=1 then PC'-PC+TEMP
Description: Causes a branch if either, but not both, of the N (negative) or V

(overflow) bits is set. That i s, branch if the s i g n of a val i d twos com
plement result Is, or would be, negat ive. When used after a s ubtract
or compare operation on t wos complement b inary values, t h i s i n
struction wi l l branch if the reg ister was less t h a n t h e memory
operand.
A-22
BMI Branch on Minus BMI
Source Forms: BM I dd; LBM I DODD
I FF N =1 then PC' - PC + TEM P
Description: Tests the state of the N (negative) bit and causes a branch if set.
That is, branch if the sign of the tw os com plem ent result is negative.
Comments: When u sed after an operation on signed binary values, this i n struc
tion w i l l branch if the resu lt is m i n us. It is general ly preferred to use
the LBLT i nstruction after sig ned operations.
A-23
BN E Branch Not Equal BNE
Source Forms: B N E dd; LBN E DODD
I FF Z = O then PC' - PC + TEM P
Description: Tests the state of the Z (zero) bit and causes a branch if it is c lear.
When used after a subtract or com pare operation on any binary
val ues, this instruction w i l l branch i f the reg ister is, or would be, not
equal to the memory operand.
A-24
BPL Branch o n Plus BP L
Source Forms: BPL dd; LBPL DODD
I FF N = 0 then PC' - PC + TEM P
Description: Tests the state of the N (negative) bit and causes a branch if it is
clear. That is, branch if the sign of the twos com p lement result i s
posit ive.
Addressing Mode: Rel ative
Comments: When used after an operation on sig ned binary val ues, this i nstruc
tion wi l l branch if the resu lt (possibly i nval id) is positive. It is general
ly preferred to use the BGE i n struction after sig ned operations.
A-25
BRA Branch Always B RA
Source Forms: BRA dd; LBRA DODD
PC' - PC + TEM P
Description: Causes an uncond itional branc h .
A·26
B RN Branch Never BRN
Source Forms: BRN dd; LBRN DODD
Descript ion: Does not cause a branch. Th is i n struction is essent ially a no opera
tion, but has a bit pattern logically rel ated to branch always.
A-27
BSR Branch to Subroutine BSR
Source Forms: BSR dd; LBSR DODD
S P' - SP - 1 , (SP) - PCL
S P' - S P - 1 , (S P) - PC H
PC' - PC + TEM P
Description: The program counter is pushed onto the stack. The prog ram counter
i s then loaded with the sum of the prog ram counter and the offset .
Comments: A ret urn from subroutine (RTS) i n st ruction i s used to reverse this pro
cess and m u st be the l ast i n st ruction executed in a subrouti ne.
A-28
Bve Branch on Overflow Clear Bve
Source Forms: BVC dd; LBVC DODD
I FF V=O then PC' - PC + TEM P
Description: Tests the state of the V (overflow) bit and causes a branch if it is
clear. That is, branch if the twos complement result was val id. When
used after an operation on twos complement b i nary val ues, t h i s i n
struct ion wi l l branch if there was no overflow.
A-29
BVS Branch on Overflow Set BVS
Source Forms: BVS dd; LBVS DODD
I FF V = 1 then PC' - PC + TEM P
Description: Tests the state of the V (overflow) bit and causes a branch if it i s set .
That is, branch if the twos complement result was i nval id. When us
ed after an operation on twos .complement binary val ues, this i n
struction w i l l branch if there was an overflow.
A-30
CLR Clear CLR
Source Form: CLR a
Operation: TEM P - M
M - 00 1 6

N - Always cleared.
Z - Always set.
V - Always cleared.
C - Always cleared.
Description: Accu m u l ator A or B or memory location M is loaded with 00000000.

Note that the EA is read during this operation .

Extended
Direct
I ndexed
A-31
CMP (8-Bit) Compare Memory from Register CMP (8-Bit)
Source Forms: C M PA P; CM PB P
Operation: TEM P - R - �
Condition Codes: H - U ndefi ned.

N - Set if the result is negative; cleared otherwise.
Z - Set if the result is zero; cleared otherwise.
V - Set if an overflow is generated ; cleared otherwise.
C - Set if a borrow is generated; cleared otherwise.
Description: Com pares the contents of memory locat ion to the contents of the
specified reg i ster and sets the appropriate condition codes. N either
memory location M nor the specified reg ister is modified . The carry
flag represents a borrow and is set to the i nverse of the resulting
bi nary carry.

Extended
Di rect
I ndexed
A-32
CMP (1 6- Bit) Compare Memory from Register CMP (1 6- Bit)
Source Forms: C M PD P; CM PX P; CM PY P; CM PU P; CM PS P
Operation: TEM P - R - M:M + 1

N - Set if the resu lt is negative; cleared otherwise.
Z - Set if the resu lt is zero; cleared otherw i se.
V - Set if an overflow is generated ; cleared otherwise.
C - Set if a borrow is generated ; cleared otherwise.
Description: Compares the 1 6-bit contents of the concatenated memory locations

M:M + 1 to the contents of the specified reg i ster and sets the ap
propriate condition codes. N either the memory locations nor the
specified reg ister i s mod ified unless autoincrement or autodecre
ment are used . The carry flag represents a borrow and is set to the
inverse of the resulting binary carry.
Addressing Modes: I m med iate

Extended
D irect
I ndexed
A-33
CO M Complement CO M
Source Forms: COM Q; COMA; COM B
Operation: M ' - 0 + f\f

N - Set if the resu lt is negat ive; cl eared otherwise.
Z - Set if the res u lt is zero; cl eared otherw ise.
V - Atways cleared .
C - Always set .
Description: Replaces the contents of memory location M or accumulator A or B

with its log ical com plement . When operat i n g on unsig ned val ues,
only BEQ and BN E branches can be expected to behave properly
fol lowing a COM i n st ruction . When operat i n g on twos com plement
val ues, al l signed branches are avai l able.
Addressing Modes: I n herent

Extended
D i rect
I ndexed
A·34
CWAI Clear CC bits and Wait for Interrupt CWAI
Source Form: CWAI #$XX IEl F I H I I I NI I VI C I
z
Operation: CCR - CCR A M I (Possibly clear masks)

Set E (ent i re state saved)
SP' - SP - 1 , (SP) - PCL
S P' - SP - 1 , (S P) - PCH
SP' - SP - 1 , (S P) - USL
SP' - SP - 1 , (SP) - USH
S P' - SP - 1 , (SP) - IYL
SP' - SP - 1 , (S P) - IYH
S P' - SP - 1 , (SP) - IXL
SP' - SP - 1 , (S P) - IXH
SP' - SP - 1 , (SP) - DPR
SP' - SP - 1 , (S P) - ACCB
SP' - SP - 1 , (S P) - ACCA
S P' - SP - 1 , (SP) - CCR
Condition Codes: Affected according to the operation .
Description: Th i s i nstruction AN Ds an i m med iate byte with the condition code

reg i ster which may c l ear the i nterrupt mask bits I and F, stacks the
ent i re mac h i n e state on the hardware stack and then looks for an i n
terrupt. When a non-masked i nterrupt occurs, no further mac h i ne
state informat ion need be saved before vectori ng to the i nterrupt
hand l ing routine. Th is i n struction rep l aced the M C6800 CLI WAI se
q uence, but does not p l ace the buses in a h igh-impedance state. A
Fi"RO' (fast interrupt req uest) may enter its i nterrupt handler with its
ent i re mac h i ne state saved. The RTI (return from i nterrupt) i nst ruc
tion w i l l automat ical ly ret urn the ent i re machine state after test i n g
the E (ent i re) b i t o f t h e recovered cond it ion code reg i ster.
Addressing Mode: I m med iate
Comments: The fol lowi n g i m med iate values w i l l have the fol low i ng results:
F F = enable neither
E F = enable 'iRa
B F = enable FI RQ
AF = enable both
A-35
DAA Decimal Addition Adjust DAA
Source Form: DAA
Operation: ACCA' - ACCA + CF (M SN):CF(LSN)

where CF is a Correct ion Factor, as fol lows: the CF for each n i bble
(BCD) d ig it is determ i ned separately, and is either 6 or o .
Least Significant N ibble
C F(LSN) = 6 I FF 1) C = 1
or 2) LSN > 9
Most Significant N i bble
C F(MSN) = 6 I FF 1) C = 1
or 2) M SN > 9
or 3) M SN > 8 and LSN > 9

N - Set if the result is negative; cl eared otherwise.
Z - Set if the result is zero; c leared otherwise.
V - U ndefi ned .
C - Set i f a carry is generated or if the carry bit was set before the
operation; cleared otherwise.
Description: The seq uence of a single-byte add i nstruction on acc u m u l ator A

(e ither ADDA or ADCA) and a fol lowi ng dec i m a l add ition adj u st i n
struction resu lts i n a BCD add ition with an appropriate carry bit.
Both val ues to be added m u st be i n proper BCD form (each n i bble
such that: Os n i bble s 9). M u lt i p l e-precision add ition m ust add the
carry generated by this decimal add ition adj u st i nto the next h i g her
d i g it d u ring the add operation (A DCA) immed i ately prior to the next
dec i m al add it ion adj ust.
A-36
D EC Decrement DEC
Source Forms: DEC Q; DECA; DECB
Operation: M' - M - 1

N - Set if the resu lt is negat ive; cleared ot herwise.
Z - Set if the result is zero; c leared ot herwise.
V - Set i f the original operand was 1 0000000; c leared ot herwise.
C - N ot affected .
Description: Subtract one from the operand. The carry bit is not affected, thus
allowing t h i s instruct ion to be used as a loop counter i n m u lt i ple
prec ision com putations. When operat i n g on unsig ned val ues, on ly
BEQ and B N E branches can be expected to behave consistently.
When operat i ng on twos com plement val ues, al l sig ned branches
are available.

Extended
Di rect
I ndexed
A-37
EO R Excl usive O R EO R
Source Forms: EO RA P; EO RB P
Operation: R' - R ED M

Z - Set if the result is zero; c leared otherw i se.
V - A lways cleared .
C - N ot affected .
Description: The contents of memory l oc ation M is exc l usive O Red i nto an 8-bit
reg i ster.

Extended
D i rect
I ndexed
A-38
EXG Exchange Registers EXG
Source Form: EXG R1 , R2
Operation: R1 - R2
Condition Codes: N ot affected (u n l ess one of the reg i sters is the condition code
reg i ster).
Description: Exchanges data between two designated reg i sters. Bits 3-0 of the
post byte defi ne one reg ister, wh i l e bits 7-4 d efine the other, as
fo l lows:
OOOO = A:B 1 000 = A
0001 = X 1 001 = B
001 0 = Y 1 0 1 0 = CCR
001 1 = US 1 01 1 = DPR
01 00 = S P 1 1 00 = U ndefi ned
01 01 = PC 1 1 01 = Undefi ned
01 1 0 = Undefi ned 1 1 1 0 = Undefi ned
01 1 1 = Undefi ned 1 1 1 1 = Undefi ned
Only l i ke size reg i sters may be exchanged. (8-bit with 8-bit or 1 6-bit
with 1 6-bit .)
A-39
INC Increment I NC
Source Forms: I N C Q; I N CA; I N CB
Operation: M'- M + 1

N - Set if the result is negat ive; cleared otherwise.
Z - Set if the result is zero; c leared otherwise .
V - Set if the origi nal operand was 01 1 1 1 1 1 1 ; cl eared otherw i se.
C - N ot affected .
Description: Adds to the operand. The carry bit is not affected , thus al low i n g t h i s
i n struction to b e used a s a loop counter in m u lt i ple-precision com
putat ions. When operating on unsigned val ues, only the BEQ and
BN E branches can be expected to behave consistently. When
operat i ng on twos com plement val ues, al l sig ned branches are cor
rectly avai lable.

Extended
Direct
I n dexed
A-40
JMP J ump JMP
Source Form: J M P EA
Operation: PC' - EA
Description: Prog ram contro l is transferred to the effect ive address.
Addressing Modes: Extended

Di rect
I ndexed
A-41
JSR J ump to Subro utine JSR
Source Form: JSR EA
Operation: SP' - SP - 1 , (S P) - PC L
SP' - SP - 1 , (S P) - PC H
PC' - EA
Description: Prog ram control is transferred to the effective add ress after stori ng
the retu rn address on the hardware stack. A RTS i n st ruction sho u l d
b e t h e last executed inst ruct ion o f t h e su brout ine.

Di rect
I ndexed
A·42
L D (8- Bit) Load Register from M emory L D (8- Bit)
Source Forms: LOA P; LOB P
Operation: R' - M
Condition Codes: H N ot affected .

-
N - Set if the l oaded data i s negative; cleared ot herwise.

Z Set if the l oaded data is zero; cl eared otherwise.
-
V Always cl eared .
-
C N ot affected .
-
Description: Loads the contents of memory location M i nto the desig nated
reg i ster.

Extended
Di rect
Indexed
A-43
L D (1 6- Bit) Load Register from Memory L D (1 6-Bit)
Source Forms: LOO P; LOX P: LOY P; LOS P; LOU P
Operation: R' - M : M + 1

N - Set if the loaded data is negat ive; c leared otheriwse.
Z - Set if the loaded data is zero; cl eared otherwise.
V - Always cleared .
C - N ot affected .
Description: Load the contents of the memory locat ion M : M + 1 i nto the
desi gnated 1 6-bit reg i ster.

Extended
Di rect
I ndexed
A-44
LEA Load Effective Address L EA
Source Forms: LEAX, LEAY, LEAS, LEAU
Operation: R' - EA

N - N ot affected .
Z - LEAX, LEAY: Set if the resu lt is zero; cl eared otherwise.
LEAS, LEAU: Not affected.
V - N ot affected .
C - N ot affected .
Description: Cal c u l ates the effect ive add ress f rom the i ndexed addressi ng mode
and pl aces the add ress in an i ndexable reg ister.
LEAX and LEAY affect the Z (zero) bit to al low u se of these reg isters
as counters and for M C6800 I N XIDEX compat i b i l ity.
LEAU and LEAS do not affect the Z bit to al low clean i ng up the stack
w h i l e ret u rn i n g the Z bit as a parameter to a cal l i ng routi ne, and also
for M C6800 I N SID ES com pat i b i l ity.
Addressing Mode: I ndexed
Comments: Due to the order i n which effective add resses are calcu lated i nter
nal ly, the LEAX, X + + and LEAX, X + do not add 2 and 1 (respective
ly) to the X reg ister; but i n stead leave the X reg ister unchanged . Th is
also appl ies to the Y, U , and S reg isters. For the expected resu lts,
use the faster i nst ruction LEAX 2, X and LEAX 1 , X.
Some exam ples of LEA i nstruction uses are g iven in the fol lowi ng
table.
Instruct ion Operation Comment
LEAX 1 0, X X + 10 - X Adds 5-bit constant 1 0 to X
LEAX 500, X X + 500 - X Adds 1 6-bit constant 500 to X
LEAY A, Y Y+A-Y Add s 8-bit acc u m u l ator to Y
LEAY 0, Y Y+D-Y Adds 1 6-bit 0 accumulator to Y
LEAU - 1 0, U U - 10 - U Subt racts 1 0 from U
LEAS - 1 0, S - S - 10 - S Used to reserve area on stack
LEAS 1 0, S S + 10 - S Used to 'clean up' stack
LEAX 5, S S+5-X Transfers as wel l as adds
A-45
LSL Logical Shift Left LSL
Source Forms: LSL Q; LSLA; LS LB
Operation:
c- I I I I I I I I 1- 0
b7 bO
Condition Codes: H - U ndefi ned .
N - Set if the res u lt is negative; cleared otherwise.
Z - Set if the res u lt is zero; cl eared otherwise.
V - Loaded with the resu lt of the exc l usive O R of bits six and
seven of the original operand.
C - Loaded with bit seven of the origi nal operand .
Description: Sh ifts al l bits of accu m u l ator A or B or memory locat ion M one place
to the left . Bit zero is loaded with a zero. Bit seven of acc u m u l ator A
or B or memory locat ion M is shifted i nto the C (carry) bit.
Add ressing Modes: I n herent

Extended
D i rect
I ndexed
Comments: Thi s is a d u p l icate assem bly-language mnemonic for the s i n g l e

mach ine i n struction ASL.
A-46
LS R Logical Shift Right LS R
Source Forms: LS R Q; LS RA; LSRB
Operation:
0-+1 I I I I I I I 1- c
b7 bO
N - Always cleared .
Z - Set if the result is zero; c leared ot herw i se.
V - N ot affected.
C - Loaded with bit zero of the orig i nal operand .
Description: Performs a logical shift right on the operand . Sh ifts a zero i nto bit
seven and bit zero i nto the C (carry) bit.

Extended
D i rect
I ndexed
A·47
MUL M ultiply MUL
Source Form: MUL
Operation: ACCA':ACCB' - ACCA x ACCB

N - N ot affected .
Z - Set if the res u lt is zero; cleared ot herwise.
V - N ot affected .
C - Set if ACCB bit 7 of resu lt is set; cleared otherwise.
Description: M u lt i p ly the unsigned b i nary n u m bers in the accum u l ators and

place the resu lt in both acc u m u l ators (ACCA contai ns the most
significant byte of the resu lt). Unsig ned m u lt i ply a l lows m u lt i p l e
precision operations.
Comments: The C (carry) bit allows rou nding the most-sig nif icant byte t h rough
the seq uence: M U L, ADCA #0.
A-48
N EG Negate N EG
Source Forms: N EG Q; N EGA; N EG B
Operation: M'-0 - M
Condition Codes: H - U ndefined.

N - Set if the result is negat ive; cleared otherw i se.
V - Set if the orig i nal operand was 1 0000000.
C - Set if a borrow is generated ; cleared ot herwise.
Description: Rep laces the operand with its twos com plement. The C (carry) bit
represents a borrow and is set to the i nverse of the resulting bin ary
carry. N ote that 80 1 6 i s replaced by itself and only i n this case i s the
V (overflow) bit set . The val ue 00 1 6 is also rep laced by itself, and only
i n t h i s case is the C (carry) bit cleared .

Extended
Di rect
A-49
NOP No Operation NOP
Source Form: NOP
Operation: N ot affected .
Condition Codes: This i nstruct ion causes only the prog ram cou nter to be incremented .
No ot her reg i sters or memory locations are affected .
A-50
OR Inclusive O R Memory into Register OR
Source Forms: O RA P; ORB P
Operation: R' - Rv M

Z - Set if the result is zero; cl eared otherw ise.
V Always cleared .
-
C - N ot affected .
Description: Performs an i n c l u sive OR operation between the contents of ac

c u m u l ator A or B and the contents of memory locat ion M and the
resu lt i s stored in accumulator A or B.
Addressing Modes: I mme d iate

Extended
Di rect
I ndexed
A-51
OR I nclusive OR Memory Immediate i nto Condition Code Register OR
Source Form: ORee #XX
Operation: R' - R v M I
Condition Codes: Affected according to the operation.
Description: Performs an inclusive OR operation between the contents of the

cond ition code reg isters and the immed i ate value, and the result is
placed in the cond ition code reg ister. This i n struct ion may be used
to set i nterrupt masks (d i sable i nterrupts) or an y other bit(s).
Addressing Mode: Immed i ate
A-52
PS·H S Push Registers on the Hardware Stack PSH S
Source Form: PSH S reg ister l i st
PSH S # LABEL
Post byte:
b7 b6 b5 b4 b3 b2 b1 bO
Ipc IU I Y I X l op I B I A I cc i
push order- - - - .
Operation: I FF b7 of post byte set, then: SP' - SP - 1 , (SP) - PCL

SP' - S P - 1 , (SP) - PCH
I FF b6 of postbyte set , then: SP' - SP - 1 , (SP) - USL
SP' - SP - 1 , (SP) - USH
I FF b5 of post byte set , then: SP' - SP - 1 , (SP) - IYL
SP' - S P - 1 , (SP) - IYH
I F F b4 of postbyte set , then: SP' - SP - 1 , (SP) - I X L
SP'- SP - 1 , (SP) - I XH
I FF b3 of postbyte set, then: SP' - SP - 1 , (SP) - DPR
I FF b2 of postbyte set, then: SP' - SP - 1 , (SP) - ACCB
I FF b 1 of postbyte set, then: SP' - SP - 1 , (SP) - ACCA
I F F bO of post byte set, then: SP' - SP - 1 , (SP) - CCR
Description: Al l , some, or none of the p rocessor reg isters are pushed onto the
hardware stack (with the exception of the hardware stack pOi nter
itself).
Comments: A single reg i ster may be pl aced on the stack with the cond ition
codes set by doing an autodecrement store onto the stack (example:
STX , - - S).
A·53
PSH U Push Registers on the User Stack PS H U
Source Form: PSH U reg i ster l i st
PSH U # LABEL
Postbyte:
b7 b6 b5 b4 b3 b2 b1 bO
I PC I U I Y I X I D P I B I A I cc I
push order- - - - -�
Operation: I FF b7 of postbyte set , then: US' - US - 1 , (US) - PCL

US' - US - 1 , (US) - PCH
I FF b6 of postbyte set , then: US' - US - 1 , (US) - SPL
US' - US - 1 , (US)- SPH
I FF b5 of postbyte set , then: US' - US - 1 , (US) - IYL
US' - US - 1 , (US) - IYH
I FF b4 of post byte set , then: US' - US - 1 , (US) - IXL
US' - US - 1 , (US) - IXH
I FF b3 of postbyte set , then: US' - US - 1 , (US) - DPR
I FF b2 of post byte set, then: US' - US - 1 , (US) - ACCB
I FF b1 of postbyte set , then: US' - US - 1 , (US) - ACCA
I FF bO of postbyte set , then: US' - US - 1 , (US) - CCR
Description: Al l , some, or none of the p rocessor reg isters are pushed onto the
user stack (with the except ion of the user stack poi nter itself).
Comments: A s i n gl e reg ister may be p laced on the stack with the condition
codes set by doing an autodecrement store onto the stack (exam ple:
STX , - - U).
A·54
P U LS Pull Registers from the H a rdware Stack P U LS
Source Form : PU lS reg ister l i st
P U lS #lABEl
Postbyte:
b7 be b5 b4 b3 b2 b1 bO
I pc I U I Y I x l op I B I A I cci
... - - - - - - pu l l order
Operation: I FF bO of post byte then: CCR' - (S P),

set , SP' - S P + 1
I FF b1 of postbyte then: ACCA' - (S P),
set , SP' - SP + 1
I FF b2 of postbyte then: ACCB' - (S P),
set , SP' - SP + 1
I FF b3 of post byte then: OPR' - (SP),
set , SP' - SP + 1
I FF b4 of post byte then: I X H ' - (S P),
set , S P ' - SP + 1
I Xl' - (S P), SP' - SP + 1
I FF b5 of postbyte set , then: IYH ' - (S P), S P' - SP + 1
IYl' - (SP), SP' - SP + 1
I FF b6 of post byte set , then: USH' - (SP), S P' - SP + 1
USl' - (SP), S P' - SP + 1
I F F b7 of post byte set , then: PCH ' - (S P), SP' - SP + 1
PCl' - (S P), SP' - SP + 1
Condition Codes: M ay be p u l led from stack; not affected otherwise.
Description: Al l , some, or none of the processor registers are p ulled from the
h ardware stack (w ith the exception of the h ardware stack poi nter
itself).
Addressing Mode: I m med i ate
Comments: A single reg i ster may be p u l l ed from the stack with cond ition codes
set by doing an auto i ncrement load from the stack (exa m ple:
lOX ,S + + ).
A-55
PU LU Pull Registers from the User Stack P U LU
Source Form: PU lU reg ister l i st
PU lU #lASEl
Post byte:
b7 b6 b5 b4 b3 b2 b1 bO
I PC I U I Y I X I OP I S I A I cci
. - - - - - - pu l l order
Operation: I FF bO of postbyte set ,

then: CCR' - (US), US' - US + 1
I FF b1 of postbyte set ,
then: ACCA' - (US), US' - US + 1
I FF b2 of post byte set ,
then: ACCS' - (US), US' - US + 1
I FF b3 of postbyte set,
then: OPR' - (US), US' - US + 1
I FF b4 of postbyte then: I XH ' - (US), US' - US + 1
set ,
I Xl' - (US), US' - US + 1
I F F b5 of postbyte set , then: IYH' - (US), US' - US + 1
IYl' - (US), US' - US + 1
I FF b6 of postbyte set , then: SPH' - (US), US' - US + 1
SPl' - (US), US' - US + 1
I FF b7 of postbyte set, then: PCH - (US), US' - US + 1
PCl' - (US), US' - US + 1
Condition Codes: May be pul led from stack; not affected otherwise.
Description: Al l , some, or none of the processor reg i sters are p u l l ed from the u ser
stack (with the exception of the user stack pOi nter itself).
Addressing Mode: I mmediate
Comments: A single reg i ster may be p u l l ed from the stack with condition codes
set by doing an auto i n c rement load from the stack (exam ple:
lOX ,U + + ).
A-56
RO L Rotate Left RO L
Source Forms: RO L Q; ROLA; RO LB
�� """--"' �....,..--
j=r""I ,.
Operation:
b7 'II(�-----
.... bO

N - Set if the result is negat ive; cleared ot herwise.
Z - Set if the resu lt is zero; cleared otherwise.
V - Loaded with the result of the excl usive O R of bits six and
seven of the orig i nal operand.
C -Loaded with bit seven of the orig i nal operand .
Description: Rotates a l l bits of the operand one place l eft through the C (carry)
bit. Th is is a 9-bit rotation.
Addressing Mode: I n herent

Extended
Di rect
I ndexed
A-57
RO R Rotate Right RO R
Source Forms: ROR Q; RO RA; RORB
Y"--'---I�_c_ I �
I --
Operation:
- I --
b7 -----�. bO
Condition Codes: H - Not affected .

N - Set i f the result is negat ive; c leared ot herwise.
Z - Set i f the result is zero; c l eared ot herw i se.
V - Not affected .
C - Loaded with bit zero of the previous operand .
Description: Rotates al l bits of the operand one place right through the C (carry)
bit. Th i s is a 9·bit rotation.

Extended
Di rect
I ndexed
A·58
RTI Return from Interrupt RTI
Source Form: RTI
Operation: CCR' - (S P), SP' - SP + 1 , then
I F F CCR bit E is set , then: ACCA' - (S P), SP' - SP + 1

ACCS' - (SP), SP' - S P + 1
OPR' - (S P), SP' - SP + 1
IXH ' - (S P), SP' - SP + 1
IXL' - (SP), SP' - SP + 1
IYH ' - (SP), SP' - SP + 1
IYL' - (S P), SP' - SP + 1
USH' - (S P), SP' - SP + 1
USL' - (S P), SP' - SP + 1
PCH ' - (SP), SP' - SP + 1
PCL' - (S P), SP' - SP + 1
I F F CCR bit E i s c lear, then: PCH ' - (SP), SP' - SP + 1

PCL' - (SP), SP' - SP + 1
Cond ition Codes: Recovered from the stack.
Description: The saved mach ine state is recovered from the hardware stack and
contro l i s returned to the i nterru pted prog ram . I f the recovered E (en
t i re) bit is clear, it i n d icates that only a subset of the machine state
was saved (retu rn address and cond ition co des) and only that subset
is recovered .
A-59
RTS Return from Subroutine RTS
Source Form: RTS
Operation: PCH ' - (SP), SP' - SP + 1

PCl' - (SP), SP' - SP + 1
Description: Program control is retu rned from the subrout i ne to the cal l i ng pro
g ram. The return address is pul l ed from the stack.
Add ressing Mode: I nherent
A-60
SBe Subtract with Borrow SBe
Source Forms: SBCA P; SBCB P
Operation: R' - R - M - C
Condition Codes: H - Undefi ned .

N - Set if t h e resu lt is negative; c l eared otherwise.
Z - Set if the resu lt is zero; c l eared ot herwise.
V - Set if an overflow is generated; cleared otherwise.
C - Set if a borrow i s generated ; cl eared oth erwi se .
Description: Subtracts the contents of memory locat ion M and the borrow (in the
C (carry) bit) from the contents of the designated a·bit register, and
places the res u lt i n that reg i ster. The C bit represents a borrow and
i s set to the i nverse of the resulting bin ary carry.
Addressing Modes: I mm ed i ate

Extended
Di rect
I ndexed
A·61
S EX Sign Extended SEX
Sou rce Form: S EX
Operation: If bit seven of ACCe is set then ACCA' - F F 1 6

e l se ACCA' - 00 1 6

N - Set if the result is negat ive; cleared otherwise.
V - N ot affected .
C - N ot affected .
Description: This i nstruction transforms a twos complement 8-bit value i n ac

cumulator e i nto a twos com plement 1 6-bit val ue in the 0 ac
cumulator.
A -62
ST (8-Bit) Store Register· into Memory ST (8-Bit)
Source Forms: STA P; STe P
Operation: M' - R

N - Set if the resu lt is negat ive; c leared ot herwise.
V - Always cl eared .
C - Not affected .
Description: Writes the contents of an 8·bit reg ister i nto a memory location .

Di rect
I ndexed
A-63
8T (1 6-Bit) Store Register Into Memory 8T (1 6-Bi·t )
Source Forms: STD P; STX P; STY P; STS P; STU P
Operation: M ':M + 1 ' - R

Z - Set if the resu lt is zero; c leared otherwise.
V - Always c l eared .
C - Not affected .
Description: Writes the contents of a 1 6·bit reg ister i nto two consecutive memory
locations.

Di rect
I ndexed
A-64
SU B (8- Bit) Su btract Memory from Register SU B (8- Bit)
Source Forms: S U BA P; SUBB P
Operation: R' - R - M
Condition Codes: H - U ndefined .

N - Set if the resu lt is negative; c leared otherwise.
V - Set if the overflow is generated; c leared otherwise.
C - Set if a borrow is generated; c leared otherwise.
Description: Subtracts the value i n memory location M from the contents of a

designated 8-bit register. The C (carry) bit represents a borrow and is
set to the inverse of the resu lting b i nary carry.
Addressing Modes: I m m ed iate

Extended
Direct
I ndexed
A-65
S U B (1 6- Bit) Subtract Memory from Register S U B (1 6- Bit)
Source Forms: SUBD P
Operation: R' - R - M:M + 1

V - Set if the overflow is generated ; cleared otherwise.
C - Set if a borrow is generated ; cleared otherw ise.
Description: Subtracts the val ue in memory location M :M + 1 from the contents of

a designated 1 6-bit reg i ster. The C (carry) bit represents a borrow
and is set to the inverse of the resulting binary carry.
Addressing M odes: I mmed iate

Extended
Di rect
I ndexed
A-66
SWI Software Interrupt SWI
Source Form: SWI
Operation: Set E (enti re state wi l l be saved)

SP' - SP - 1 , (S P) - PCL
S P' - SP - 1 , (S P) - PCH
S P' - SP - 1 , (SP) - USL
SP' - SP - 1 , (S P) - USH
SP' - S P - 1 , (SP) - IYL
SP' - SP - 1 , (SP) - IYH
SP' - S P .- 1 , (SP) - IXL
SP' - SP - 1 , (SP) - IXH
SP' - SP - 1 , (S P) - D P R
S P' - SP - 1 , (SP) - ACCB
S P' - S P - 1 , (SP) - ACCA
S P' - SP - 1 , (SP) - CCR
Set I, F (mask i nterru pts)
PC' - (FFFA):(FFFB)
Description: Al l of the processor reg i sters are pushed onto the hardware stack
(with the exception of the h ardware stack poi nter itsel f), and control
is transferred through the software i nterrupt vector. Both the normal
and fast i nterrupts are masked (di sabled).
A-67
SWI2 Software Interrupt 2 SWI2
Source Form: SWI 2
Operation: Set E (ent i re state saved)

S P' - SP - 1 , (SP) - PCL
S P' - SP - 1 , (S P) - PCH
S P' - S P - 1 , (S P) - USL
S P' - SP - 1 , (S P) - USH
S P' - SP - 1 , (SP( - IYL
S P' - S P - 1 , (SP) - IYH
S P' - SP - 1 , (S P) - IXL
S P' - SP - 1 , (SP) - IXH
S P' - SP - 1 , (SP) - D P R
S P' - S P - 1 , (SP) - ACCB
S P' - SP - 1 , (SP) - ACCA
S P' - SP - 1 , (S P) - CCR
PC' - (FFF4):(FFF5)
Description: A l l of the processor reg i sters are pushed onto the hardware stack
(with the except ion of the hardware stack pOi n t er itself), and control
i s transferred through the software i nterrupt 2 vector. Th i s i nterrupt
i s avai l able to the end user and must not be u sed i n packaged soft
ware. Th is interru pt does not mask (d isable) the normal and fast in
terrupts.
A-6 8
SWI 3 Software Interrupt 3 SWI 3
Source Form: SW I 3
Operation: Set E (ent i re state wi l l be saved)

SP' - SP - 1 , (SP) - PCl
SP' - SP - 1 , (SP) - PCH
S P' - SP - 1 , (SP) - USl
SP' - SP - 1 , (S P) - USH
S P' - SP - 1 , (SP) - IYl
S P' - SP - 1 , (S P) - IYH
SP' - SP - 1 , (S P) - IXl
S P' - SP - 1 , (S P) - IXH
SP' - S P - 1 , (S P) - DPR
S P' - SP - 1 , (SP) - ACCB
S P' - S P - 1 , (SP) - ACCA
SP' - SP - 1 , (SP) - CCR
PC' - (FFF2):(FFF3)
Description: Al l of the processor reg i sters are pushed onto the hardware stack
(with the except ion of the hardware stack poi nter itself), and control
i s transferred t h rough the software i nterru pt 3 vector. This i nterru pt
does not mask (d i sable) the normal and fast i nterru pts.
Addressing Mode: I n h erent
A-69
SYN C Synchronize to External Event SYN C
Source Form: SYNC
Operat ion: Stop processi ng i n structions
Descri ption: When a SYNC i nstruct ion is excuted , the processor enters a syn
chron izi ng state, stops processing instructions, and waits for an in
terrupt . When an interrupt occ u rs, the synchron izi ng state i s c leared
and processing cont i n ues. If the i nterrupt is enabled , and it l asts
t h ree cyc les or more, the processor w i l l perform the i nterru pt
routine. i f the i nterrupt is masked or i s shorter t h an three cycles, the
processor s i mply cont i n ues to the next i nstruct ion. Wh i l e in the syn
chronizing state, the add ress and data buses are in the hig h
i m pedance state.
This i n struction provides software synchronization with a hardware

process. Consider the fol lowing exam ple for h i g h-speed acq u i s ition
of data:
FAST SYNC WAIT F O R DATA
I nterru pt I
LDA DISC DATA FROM DISC A N D CLEAR I NTERRUPT
STA ,X + PUT IN BU FFER
DECB COUNT IT, DON E?
BNE FAST GO AGA I N I F NOT.
The synchron izing state is cleared by any i nterrupt . Of cou rse, enabl
ed interrupts at this pOint may destroy the d ata transfer and, as
such, shou ld represent only emergency condit ions.
The same con nect ion used for i nterrupt-driven I/O service m ay also
be used for high-speed data transfers by sett i n g the i nterrupt mask
a n d u s i n g the SY N C i n st ruct i o n as t h e above e xa m p l e
demonstrates.
Add ressing Mode: I n herent
A-70
TFR Transfer Register to Register TFR
Source Form: TFR R1 , R2
Operation: R1 - R2
Condition Code: N ot affected unless R2 is the cond ition code reg i ster.
Descri ption: Transfers data between two designated registers. Bits 7-4 of the
postbyte define the sou rce reg i ster, wh i l e bits 3-0 define the dest i na
tion reg i ster, as fol lows:
OOOO = A:B 1 000 = A
0001 = X 1 00 1 = B
001 0 = Y 1 01 0 = CCR
001 1 = US 1 01 1 = CPR
01 00 = S P 1 1 00 = U ndefined
01 01 = PC 1 1 01 = U ndefined
01 1 0 = U ndefi n ed 1 1 1 0 = U n defined
01 1 1 = U ndefined 1 1 1 1 = U n defined
O n ly l i ke size reg isters may be t ransferred . (8-bit to 8-bit, or 1 6-bit to
1 6-bit.)
Addressing Mode: I m med i ate
A-71
TST Test TST
Source Forms: TST Q; TSTA; TSTB
Operation: TEM P - M - 0

N - Set if the resu lt is n eg ative; cleared otherw i se.
Z - Set if the resu lt is zero; c l eared ot herwise .
V - Always cleared.
C - Not affected .
Description: Set the N (negat ive) and Z (zero) bits accordi ng to the contents of
memory location M , and c lear the V (overflow) bit. The TST i n st ruc
t ion provides only m i n i m u m i n formation when testing u n s i g ned
val ues; si nce no unsigned val ue is less than zero, BlO and B lS have
no uti l ity. Wh ile B H I cou l d be used after TST, it provides exactly the
same control as BN E, wh i c h i s preferred. The signed branches are
avai lable.

Extended
Di rect
I ndexed
Comments: The M C6BOO processor clears the C (carry) bit.
A-72
FI RQ Fast Interrupt Request (Hardware Interrupt) FI RQ
Operation: I F F F bit clear, then: S P' - S P - 1 , (S P) - PCL
S P' - S P - 1 , (S P) - PCH
Clear E (subset state is saved)
S P' - S P - 1 , (S P) - CCR
Set F, I (mask f u rther i nterru pts)
PC' - (FFF6):(FF F7)
Description: A F I RQ (fast i nterru pt req uest) with t h e F (fast i nterru pt req uest
mask) bit clear causes t h i s i nterru pt sequence to occur at the end of
the c u rrent i nstruction. The prog ram cou nter and condit ion code
reg i ster are pushed onto the hardware stack. Program control is
transferred through the fast i nterrupt req uest vector. An RTI (retu rn
from i nterrupt) i n st ruction ret u rns the p rocessor to the ori g i nal task.
It is poss i bl e to enter the fast i nterru pt req uest rout ine with the en
t i re mach ine state saved if the fast i nterru pt req uest occurs after a
c l ear and wait for i nterru pt i nstruction. A normal i nterru pt req uest
has lower priority than the fast i nterrupt req uest and is prevented
from i nterrupt i ng the fast i nterrupt req uest routi n e by automat ic set
t i n g of the I (interrupt req uest mask) bit. Th i s m ask bit could then be
reset d u ri n g the i nterrupt rout i ne if priority was not desired. The fast
i nterrupt request al lows o perations on m emory, TST, I N C, DEC, etc.
i n st ruct ions without the overhead of sav i n g the e nt i re mach ine state
on the stack.
A-73
I RQ Interrupt Request (Hardware Interrupt) I RQ
Operation: I FF I bit clear, then: SP' - S P - 1 , (S P) - PCL
SP' - S P - 1 , (S P) - PCH
SP' - SP - 1 , (S P) - USL
SP' - S P - 1 , (S P) - USH
SP' - SP - 1 , (S P) - IYL
SP' - S P - 1 , (S P) - IYH
SP' - SP - 1 , (S P) - IXL
SP' - S P - 1 , (S P) - IXH
SP' - SP - 1 , (S P) - DPR
SP' - S P - 1 , (S P) - ACCB
SP' - SP - 1 , (SP) - ACCA
Set E (ent ire state saved)
SP' - SP - 1 , (SP) - CCR
Set I (mask further I RQ i nterru pts)
PC' - (FFF8):(F FF9)
Description: If the I (i nterrupt req uest m ask) bit is clear, a low level on the I RQ i n
pu t causes this i nterru pt seq uence to occur at the end of the c urrent
i n struction. Control is ret u rned to the i nterru pted prog ram using a
RTI (ret urn from i nterrupt) i n st ruction . A FI RQ (fast i nterrupt req uest)
may i nterru pt a normal I RQ (interrupt req uest) routi n e and be
recogn ized anyt i me after the interru pt vector is take n.
A-74
NMI Non·M askable Interrupt (Hardware Interrupt) NMI
Ope ration: SP' - SP - 1 , (S P) - PCl
S P' - S P - 1 , (S P) - PCH
S P' - S P - 1 , (SP) - USl
S P' - S P - 1 , (S P) - USH
SP' - SP - 1 , (SP) - IYl
S P' - S P - 1 , (S P) - IYH
S P' - SP - 1 , (SP) - IXl
S P' - S P - 1 , (S P) - IXH
S P' - S P - 1 , (S P) - OPR
S P' - S P - 1 , (SP) - ACCB
S P' - SP - 1 , (SP) - ACCA
Set E (enti re state save)
S P' - SP - 1 , (SP) - CCR
Set I, F (mask i nterrupts)
PC' - (FF FC):(FFFO)
Description: A negat ive edge on the N M I (non-maskable i nterru pt) i n put causes
al l of the processor's reg isters (except the hardware stack poi nter)
to be pushed onto the hardware stack, start i n g at the end of the cur
rent i n struction. Program control is transferred t h rough the N M I vec
tor. Successive negat ive edges on the N M I i n put wi l l cause s u c
cessive N M I operations. Non-maskable i nterru pt operat ion can be
i nternal ly blocked by a RESET operation and any non-maskabl e i n
terrupt that occ urs wi l l b e latched . If t h i s happens, the non
maskable i nterru pt operat ion w i l l occu r after the f i rst load i nto the
stack poi nter (lOS; TFR r,s; EXG r,s; etc.) after R ESET.
Add ressing Mode: I nherent
A- 75
R ESTART Restart (H ardware Interrupt) R ESTART
Operation: CCR' - X1 X1 XXXX
D PR' - 00 1 6
PC' - ( F F F E):(F F F F)
Description: The processor is i n itial ized (req u i red after power-on) to start pro
g ram exec ution. The start i ng add ress is fetched from the restart vec
tor.
Addressing Mode: Extended I n d i rect
A-76
APPEN DIX B
ASSIST09 MON ITOR P ROG RAM
B.1 G ENERAL D ESCR I PTION
The M6809 i s a h igh-performance microprocessor which supports modern programm i ng

techn iques such as position-i ndependent, reentrancy, and mod u l ar programming. For a
software mon itor to take advantage of such capabi l ities demands a more refi ned and
sophist icated user i nterface than that provided by previous mon itors. ASSIST09 is a
monitor which su pports the advanced features that the M 6809 makes possi ble.
ASSI ST09 feat ures i n c l ude the fol lowing:
• Coded i n a position (address) i ndependent man ner. Wi l l execute anywhere i n the
64K address space.
• M u ltiple means avai l able for instal l i n g user modificat ions and extensions.
• F u l l com p l ement of commands for prog ram development i nc l uding breakpoi nt and
trace.
• Sop h i st icated mon itor cal l s for completely address-i ndependent user prog ram ser
vices.
• RAM work area is located relative to the ASSIST09 ROM , not at a fixed address as
with other monitors.
• Eas i l y adapted to real-time envi ronments.
• Hooks for user command tables, 110 handlers, and default s pecifications.
• A com plete user i nterface with services normal ly only seen in f u l l disk operat i n g
systems .
The concise i n st ruction set o f the M6809 al lows al l o f these functions and more t o be
contai ned in only 2048 bytes.
The ASSIST09 monitor is easi ly adapted to run u nder control of a real-time operat ing
system . A s pecial f unction i s avai lable which a l l ows vol untary t i me-slicing, as wel l a s
forced time-sl icing u pon t h e use of several service rout ines b y a user program .
B.2 I M PLEM E NTATION REQ U I REM ENTS
Since ASSIST09 was coded i n an add ress-i ndependent manner, it wi l l properly execute
anywhere in the 64K add ress space of the M 6809. However, an assu m ption must be m ade
reg ard i n g the location of a work area needed to hold miscel l aneous variables and the
default stack location. Th i s work area is cal l ed the page work area and it is addressed
wit h i n ASSIST09 by use of the di rect page reg ister. It is located rel at ive to the start of the
B-1
ASSI ST09 ROM by an offset of - 1 900 hexadec i m a l . Assuming ASSI ST09 resides at the
top of the memory address space for d i rect contro l of the hardware i nterru pt vectors, the
memory map wo u l d appear as shown i n Fig u re B-1 .
FFFF A S S I S T09 at Top of

A S S I S T09 Memory Map
Base R O M
FSOO Extension ROM or Other Use

User
Extension R O M
FOOO Un used 2K
( U n used)
ESOO Default PTM and ACIA

Locations
PTM / A C I A
EOOO Work Page and Default

Work Pagel S tack Stack I DF F F and Down)
Figure B-1 . M emory Map
If F800 i s not the start of the mon itor RO M the add resses wou l d change, but the rel ative
locations would remain the same except for the prog rammable t i mer mod u l e (PTM) and
asynchronous com m u n i cat ions i nterface adapter (ACI A) default addresses which are fix
ed .
The defau lt con sole i n put/output hand lers access an ACIA located at EOO8. For t race
commands, a PTM with default add ress EOOO is used to force an N M I so that s i n g l e in
structions may be executed . These default add resses may eas i ly be changed using one
of several methods. The conso l e I/O handlers m ay also be rep laced by user rout i nes. The
PTM is i n it ial ized d uring the M O N ITR service cal l (see Paragraph B.9 SERVICES) to f i reup
the monitor un less its default address has been changed to zero, i n which case no PTM
references w i l l occu r.
B.3 INTE R R U PT CONTROL
U pon reset , a vector table i s created which contai ns, among other things, default i nter
rupt vector handler appendage add resses. These routi nes may easily be rep l aced by user
appendages with the vector swap service descri bed later. The defau lt act ions taken by
the appendages are as fol lows:
RESET - B u i l d the ASSI ST09 vector tabl e and set up mon itor defaults, then i nvoke
the mon itor start u p rout ine.
SWI - Req uest a service from ASS IST09.
FI RQ - An i mmed i ate RTI is done.
SWI2, SWI3, I RQ, Reserved , N M I - Force a breakpo i nt and enter the command
processor.
B-2
The use of I RQ is recom mended as an abort fu nct ion d u ring prog ram debug g i ng ses
sions, as breakpoi nts and ot her ASSI ST09 defaults are rei n itial ized u pon RESET. On ly the
primary software i nterru pt i n struct ion (SWI) is used , not the SWI2 or SWI3. Th i s avoids
page fau l t problems which wou l d otherw i se occur with a memory management u n it as
the SWI2 and SWI3 i n st ruct ions do not d i sable i nterru pts.
Cou nter n u m ber one of the PTM is used to cause an N M I i nterru pt for the trace and break
pOint com m ands. At R ES ET the control reg i ster for t i mer one is i n itial ized for trac i n g pur
poses. If no trac i n g or breakpointing i s done then the ent i re PTM is available to the user.
Otherwise, only counters two and th ree are avai lable. Although control reg ister two m ust
be used to i n itial ize control reg ister one, ASS I ST09 ret urns contro l reg ister two to the
same val ue i t has after a R ES ET occurs. Therefore, the on ly condition i m posed on a u ser
program is that if the "operate/preset " b it in contro l reg i ster one m ust be tu rned on , $A7
sho u l d be stored, $A6 shou l d be stored if it m ust be t u rned off.
B.4 I NITIALIZAT I O N
During ASSI ST09 exec ution , a vector tabl e i s used to add ress certain service routi nes
and default val ues. Th is table is generated to provide easily changed control information
for user mod ifications. The f i rst byte of t he ASSI ST09 ROM contai ns the start of a
subrout i n e which i n it i al izes the vector table along with sett i ng u p certai n default val u es
before ret u rn i n g to the cal ler.
If the ASSI ST09 RESET vector receives contro l , it does three t h i ngs:
1 . Ass i g n s a default stack i n the work space,
2. Cal ls the aforement ioned su brout ine to i n itial ize the vector table, and
3. Fires up the ASSI ST09 mon itor proper w ith a M O N ITR SWI service req uest .
However, a u ser rout i n e can perform the same fu nctions with a bon us. After cal l i n g the
vector i nt i t i al izat ion subroutine, it may exa m i n e or alter any of the vector table val ues
before start i n g normal ASSIST09 processi ng . Th us, a user routi n e may "bootstrap"
ASSIST09 and alter the defau lt standard val ues.
Another method of i n sert i n g user mod ifications i s to have a user routine reside at an ex
tension RO M l ocation 2K bel ow the start of the ASSI ST09 ROM . The vector table i n
itial izat ion routine ment ioned above, looks for a " B RA * " f l ag ($20F E) at this add ress, and
if found cal ls the location fol lowing the flag as a subrout i n e with the U reg i ster poi nting
to the vector table. S i n ce this is done after vector table i n itial ization , any or al l defau lts
may be altered at t h i s t i me. A big advantage to u s i n g t h i s method i s that the mod ifica
t ions are "automat i c" i n that upon a RESET con�ition t h e changes are made without
overt act ion req u i red such as the execution of a memory change command.
N o special stack is u sed during ASSI ST09 processi n g . Th i s means that the stack pOi nter
m u st be val id at al l i nterru ptable t i mes and sho u l d contai n enough room for the stacki ng
of at least 21 bytes of i nformat ion . The stack i n use d u ring the i n itial M O N ITR service cal l
to start u p ASS I ST09 processing becomes the "official " stack. If any l ater stack val idity
checks occu r, t h i s same stack w i l l be re-based before enteri ng the command han d l er.
B-3
ASS IST09 u ses a work area which is addressed at an offset from the start of the
ASSI ST09 ROM . The offset val ue is - 1 900 hexadecimal . Th is poi nts to the base page us·
ed d u ri n g mon itor execution and contains the vector table as wel l as the start of the
default stack. If the default stack is used and it excee d s 81 bytes i n size, then cont ig uous
RAM m u st exist below this base work page for proper extension of the stack.
85. I NP UT/O UTPUT CONT RO L
O utput generated by use o f t h e ASSIST09 services may b e halted b y pressing a n y key,

causing a ' FREEZE' mode to be entered . The next keyboard entry w i l l release this condi·
tion al low i n g normal output to cont i n ue. Com m ands which generate l arge amou nts of
output m ay be aborted by entering CAN CEL (CONTRO L·X). User programs m ay also
mon itor for CAN CEL along with the ' F REEZE' condition even when not perform i n g con·
sole I/O (PAUSE service).
8.6 CO M M AND FORMAT
There are th ree possible formats for a com m and:

< Com m and > CR
< Command > < Expression 1 > CR
< Comm and > < Expression 1 > < Expression2> CR
The space c h aracter is used as the del i m iter between the command and al l arg u ments.
Two spec ial q u ick commands need no carriage return, "." and "/" . To re-enter a com mand
once a m i stake is made, type the CANCEL (CONTROL·X) key.
Each "expression" above consists of one or more val ues separated by an operator.
Val ues can be hex stri ngs, the l etters " P" , " M " , and "W", or the result of a function. Each
hexadeci m a l st ring is converted i nternally to a 1 6·bit binary n u m ber. The l etter " P"
stands for the current prog ram counter, " M " for the last memory examine/change ad·
d ress, and "W" for the w i ndow value. The w i ndow val ue is set by using the W I N DOW
command.
One function exists and it i s the I N DI RECT fu nction. The character " @ " fol lowi n g a val ue
rep laces that val ue with the 1 6·bit n u m be r o btai ned by using that val ue as an address.
Two operators are al l owed, " + " and " - " which cause add ition and subtract ion. Val ues
are operated on in a left·to·rig ht order.
Exam ples:
480 - h exadecimal 480
W + 3 - val ue of wi ndow p l u s three
P·200 - cu rrent program cou nter m i n u s 200 hexadec i mal
M - W - cu rrent memory pointer m i n u s w i ndow val ue
1 00 @ - value of word addressed by the two bytes at 1 00 hexadeci m al
P + 1 @ - val ue add ressed by the word located one byte u p from the cu rrent prog ram
counter
8·4
B.7 COMMAND LIST
Table B·1 l i sts the commands avai l able i n the ASSI ST09 mon itor.
Table B·1 . Command List
Command Name Description Command Entry

B reakpoint Set,clear,display, or delete breakpoints B
Call Cal l program as subroutine C
D isplay Display memory block in hex and A S C I I D
Encode Return indexed postbyte value E
Go Start or resume program execution G
Load Load memory from tape L
Memory Examine or alter memory M
Memory change or examine last referenced /
Memory change or examine hex/
N ull Set new character and new line padding N
Offset Compute branch offsets 0
P u nch Punch memory on tape P
Registers Display or alter registers R
Stlevel Alter stack trace level value S
Trace Trace number of instructions T
Trace one instruction
Verify Verify tape to memory load V
Window Set a window value W
B.8 CO M M ANDS
Each of the com mands are explai ned on the fo l lowi ng pages. They are arrang ed i n
al phabetical order b y t h e command name used i n t h e command l ist . The command name
appears at each marg i n and i n S l i g htly larger type for easy reference.
B·5
•
B REAKPO I NT B R EAKPO I NT
Format: Breakpoi nt
Breakpoint -
Breakpoint < Add ress >
Breakpoint - < Address >
Operation: Set or change the breakpoint table. The f i rst format d i s p l ays a l l breakpoi nts.
The second c lears the breakpoi nt table. The t h i rd enters an address i nto the
table. The fou rth deletes an address from the table. At reset, all breakpo i nts
are deleted. Only i n structions in RAM m ay be breakpoi nted .
CALL CALL
Format: Cal l
Cal l < Address >
Operation: Cal l and execute a user routine as a subrout i ne. The c urrent p rogram cou nter
w i l l be used u n l ess the add ress is specified. The user routi n e shou l d eventual
ly term inate with a " RTS" i nstruct ion. When this occurs, a breakpoi nt w i l l en
sue and the prog ram counter wi l l point i nto the mon itor.
B-6
DISP LAY D I S P LAY
Format: Display < From >
Display < From > < Length >
Display < From > < To >
Operation: Display contents of memory i n hexadeci mal and ASC I I characters. The se
cond arg ument, when entered, is taken to be a length if it is less than the f i rst,
otherwise it is the ending address. A default length of 1 6 decimal is assu med
for the fi rst format. The add resses are adj usted to i n c l ude all bytes with i n the
s u rround i n g mod u lo 16 address byte bou ndary. The CANCEL (CO NTROL-X)
key may be entered to abort the d isplay. Care m ust be exercised when the l ast
1 5 bytes of memory are to be d isplayed . The < Length > o pt ion shou ld always
be used in t h i s case to assure proper term i nat ion: D FFEO 40
Exam ples:
D M 10 - Display 1 6 bytes s urrou nding the l ast memory
location exam i ned.
D EOOO FOOO - Display memory from EOOO to FOOO hex.
EN CO D E E N CO D E
Format: Encode < I ndexed operand >
Operation: The encode command w i l l return the i ndex i n g i nstruct ion mode postbyte
val ue from the entered assembler-l i ke syntax operand. This is useful when
hand cod i n g i n struct ions. The letter " H " i s used.to i n d icate the n u m ber of hex
d i g its n eeded i n the expression as shown i n the fol lowi n g exam ples:
E ,V - Ret urn zero offset to V reg i ster postbyte.
E [H H H H , PCR] - Ret urn two byte peR offset using i n d i rection.
E [,S + + 1 - Ret urn autoi ncrement S by two i n d i rect.
E H ,X - Return 5-bit offset from X.
Note that one " H " specifies a 5-bit offset , and that the result g iven w i l l h ave
zeros in the offset val ue position. Th is comand does not detect all i ncorrect ly
s pec ified syntax or i l l egal i ndex i n g modes.
8-7
GO GO
Format: Go
Go < Add ress >
Operation: Execute start i n g from the add ress g iven . The fi rst format w i l l cont i n ue from
the current program cou nter sett i n g . If it is a breakpo i nt no break w i l l be
taken . This al l ows cont i n u ation from a breakpoint. The secon d format wi l l
breakpoint i f the add ress specified i s i n the breakpoi nt l i st.
LOAD LOAD
Format: Load
Load < Offset >
Operation: Load a tape f i l e created using the 51 -59 format. The offset option, i f u sed , i s
added to t h e address on t h e tape t o specify t h e act ual load address. Al l off
sets are positive , but wrap around memory mod u lo 64K. Depend ing on the
eq u i p m ent i nvolved , after the l oad i s complete a few spurious c haracters m ay
sti l l be sent by the i n put device and i nterpreted as com mand characters. If
t h i s happens, a CANCEL (CONTRO L-X) shoul d be entered to cause such
characters to be ig nored . If the load was not successfu l a " 7 " is d isplayed .
8-8
M EM O RY M EM O RY
Format: M EM O RY < Add ress > /
< Ad d ress > /
I
Operation: I n it i ate the memory exami ne/change fu nct ion. The second format w i l l not ac
cept an expression for the add ress, only a hex stri ng. The t h i rd format
defau lts to the address d isplayed during the l ast memory change/exam i ne
fu nction. (The same val u e is obtai ned i n expressions by use of the letter " M ".)
After act ivation, the fol lowing actions may be taken unt i l a carriage ret u rn is
entered:
< Exp r > Replaces the byte w i t h t h e specified val ue . The value m ay
be an expression.
S PACE Go to next address and print the byte val ue.
(Comma) Go to next add ress without printing the byte
val ue.
LF (Li ne feed) Go to next address and print it along with the
byte value on the next l i ne.
(Circumflex or Up arrow) Go the previous address and pri nt
it along with the byte val ue on the next l i ne.
/ Print the current add ress with the byte val u e on the next
l i ne.
CR (Carriage retu rn) Term inate the com mand.
' < Text > ' Replace succeed i n g bytes with ASCI I characters u nt i l the
second apostrophe i s entered.
I f a change attem pt fai l s (i .e., the locat ion is not vali d RAM) then a q uestion
mark wi l l appear and the next location d i splayed .
8-9
N U LL N U LL
Format: N u l l < Specification >
Operation: Set the new l i ne and character pad d i ng count val ues. The expression value i s
treated a s two val ues. The u p per two hex represent t h e character pad count,
and the lower two the new l i ne pad count (triggered by a carriage retu rn). An
expression of less than three hex d i g its wi l l set the character pad count to
zero. The val ues m ust range from zero to 7F hexadec i mal (1 27 deci m al).
Exam ple:
N 3 - Set the character cou nt to zero and new l i ne count
to t h ree.
N 207 - Set character padding cou nt to two and new l i ne
cou nt to seven.
Sett ings for TI Silent 700 term i na l s are:
Baud Setting
1 00 0
300 4
1 200 31 7
2400 72F
O F FS ET O F FS ET
Format: Offset < Offset add r > < To i n st ruct ion >
Operation: Print the one and two byte offsets needed to perform a branch from the f i rst
expression to the i n struction. Th us, offsets for branches as wel l as i ndexed
mode i n struct ions wh ich use offsets may be obtained. If only a fou r byte
val ue is pri nted , then a short branch count can not be done between th.e two
add resses.
Example:
o P + 2 AOOO - Com pute offsets needed from the c u rrent pro-
g ram cou nter plus two to AOOO.
8-1 0
PUNCH PUNCH
Format: Punch < From > < To >
Operation: Punch or record formatted binary object tape i n 51 -59 (M I KBUG ) form at.
R EG IST E R REG IST E R

Format: Reg ister
Operation: Print the reg ister set and prom pt for a change. At each prom pt the fol lowi ng
m ay be entered .
SPACE Ski p to the next reg ister pro mpt
< Expr > S PACE Repl ace with the specified val ue and pro m pt for the next
reg i ster.
< Expr > CR (carriage retu rn) Replace with the specified val ue and ter
m i n ate the command.
CR Term i n ate the com mand.
M I KBUG i s a trademark o f Motorola I nc.
B-1 1
ST LEVEL STL EVEL
Format: St l evel
St l evel < Ad dress >
Operation: Set the stack trace l evel for i n h i biting tracing information . As long as the
stack is at or above the stack level address, the trace display wi l l cont i n ue.
H owever, when lower than the address it is i n h i bited . This a l l ows trac i n g of a
routi ne without including al l subrout i ne and lower level cal l s i n the trace i n
formation. N ote that tracing t h rough a ASSIST09 "SW I " service req uest m ay
also temporarily supress t race output as explai ned i n the descri pt ion of the
t race com mand. The fi rst form at sets the stack trace level to the cu rrent p ro
g ram stack value.
T RAC E T RAC E
Format: Trace < Cou nt >
. (period)
Operation: Trace the specified n u m ber of i nstruct ions. At each trace, the opcode j u st ex
ecuted w i l l be shown along with the reg ister set. The program counter i n the
reg i ster d i s p l ay pOi nts to the N EXT i n struct ion to be executed. A CAN C E L
(CONTRO L-X) w i l l premat u re l y h a l t t racing. The second format (period) w i l l
cause a s i n g l e trace t o occu r. Breakpoi nts have n o effect d u ring t h e trace.
Selected port ions of a trace m ay be d i sabled using the STLEVEL command.
I nstructions i n ROM and RAM may be traced, whereas breakpoints m ay be
done only in RAM . When tracing t h rough a ASSI ST09 service request, the
t race d isplay wi l l be supressed start i n g two i n structions i nto the mon itor u nt i l
shortly before contro l is retu rned to t h e user program. This is done t o avo id a n
i nord i nate amount o f d isplay i ng because ASSIST09, at t i m es, performs a
sizeable amount of processi n g to provide the req uested services.
B-1 2
V E RI FY VERI FY
Format: Verify
Verify < Offset >
Operation: Verify or com pare the contents of memory to the tape f i le. Th is com mand h as
the same format and operation as a LOAD command except the f i l e i s com
pared to memory. If the verify fai ls for any reason a "?" is d isplayed .
WI N DOW WI N DOW
Format: Wi ndow < Value >
Operation: Set t h e w i ndow t o a val ue. Thi s val ue may b e referred to when entering ex
pressions by use of the l etter "W". The wi ndow may be set to any 1 6-bit val ue.
8-1 3
B.9 SERVICES
The fol lowi ng descri bes services provided by the ASSIST09 mon itor. These servi ces are
i n vo ked by u s i n g the "SWI" instruction fol lowed by a one byte fu nct ion code. Al l services
are designed to al low complete address i ndependence both in i nvocation and operation.
U n l ess spec ified otherwise, a l l reg isters are transparent over the "SW I " cal l . I n the
fol lowing descriptions, the terms " i n put hand ler" and "output hand ler" are used to refer
to appendage rout i nes which may be repl aced by the user. The default rout i nes perform
standard 1/0 through an ACIA for console operations to a term inal . The ASC I I CAN C E L
c o d e can b e entered on most term i nals b y depressing t h e CONTROL and X keys
s i m u ltaneously. A l ist of services is g iven in Table 8-2.
Table B·2. Services
Service Entry Code Description

Obtain input character INCHP 0 Obtain the input character in reg ister A from the input handler
O utput a character O UTCH 1 Send the character in the re g ister A to the output handler
Send stri n g PDATA1 2 Send a strin g of characters to the output handler
Send new line and strin g P DATA 3 Send a carria g e return . line feed . and strin g of characters to the
output handler
Convert byte to hex OUT2 H S 4 Display the byte poi nted to by the X reg ister in hex
Convert word to hex OUT4H S 5 Display the word pointed to by the X reg ister in hex
Output to next line P C R LF 6 Send a carria g e return and line feed to the output handler
Send space S PACE 7 Send a blank to the output handler
Fireup A S S I S T09 MONITR 8 Enter the A S S I ST09 monitor
Vector swap VCTRSW 9 Examine or exchan g e a vector table entry
U ser breakpoint B R K PT 10 Display reg isters a n d enter the command handler
Prog ram b reak and check PAU S E 11 Stop p rocessin g and check for a freeze or cancel condition
8-1 4
B R KPT User Breakpoint B R KPT
Code: 10
Arguments: N one
Result: A d i sabled breakpoint is taken. The reg isters are d i s p l ayed and the com
m and handler of ASSI ST09 is entered .
Description: Establ i shes u ser breakpoints. Both SWI2 and SWI3 default appendages
cause a breakpoint as wel l , but do not set the I and F m ask bits. However,
s i nce they may both be repl aced by user routi nes the breakpoi nt service
always ensures breakpoint avai labi l ity. These user breakpoi nts h ave
noth ing to do with system breakpoi nts which are hand led differently by the
ASSIST09 mon itor.
Example: B R KPT EaU 10 I N PUT COD E FOR B RKPT
SWI REaU EST SERV ICE

FCB BRKPT FU NCTION CODE BYTE
I NCH P Obtain Input Character I NCH P

Code: 0
Arguments: None
Result: Reg ister A contains a character obtai ned from the i n put handler.
Description: Control is not ret urned unt i l a val i d i n put character is received f ro m the in
p ut hand ler. The i n put character wil l have its parity bit (bit 7) stri pped and
forced to a zero. Al l N U LL ($00) and RU BOUT ($ 7 F) characters are i g nored
and not returned to the cal ler. The ECH O flag, which m ay be changed by
the vector SWAP service, determ i nes whether or not the i n put character is
echoed to the output hand ler (f u l l d uplex operation). The defau lt at reset is
to echo i n put. When a carriage retu rn ($00) i s received , l i ne feed ($AO) is
automat i cally sent back to the output hand ler.
Example: I N CH N P Eau o I N PUT COD E F O R I N CH P
SWI PERFORM SERV I C E CALL

FCB I NCHNP FU NCTION FOR I N CH N P
A R EG I STER N OW CO NTAI N S N EXT CHARACTER
B-1 5
MO N IT R Startup ASSISl09 M O N IT R
Code: 8
Arguments: S - Stack to become the "official " stack

D P - Di rect page defau lt for executed user programs
A = 0 Cal l i nput and output conso l e i n itial ization handlers and g ive the
"ASSI ST09" start u p message
A##O Go d i rectly to the com m and handler
Result: ASSIST09 is entered and the com and handler g iven control
Description: The pu rpose for this function is to e nter ASSI ST09, either after a system
reset, or when a user program des i res to term inate. Contro l is not ret urned
u n l ess a "GO" or "CALL" com m and is done without altering the p rogram
counter. ASSI ST09 runs on the passed stack, and if a stack error i s
detected during user program exec ution this is t h e stack that is rebased .
The di rect page reg i ster val ue i n use remains the d efault for user program
execution.
The ASSIST09 restart vector routine uses this funct ion to start u p mon itor
processing after cal l i ng the vector build su brout ine as explai n ed in I N·
ITI ALIZATIO N .
I f i n dicated by the A reg ister, the i n put and output i n itial ization handlers
are cal l ed fol lowed by the send i n g of the string "ASSIST09" to the output
handler. The programm able t i mer (PTM) is i n itial ized, if its address i s not
zero, such that reg i ster 1 can be used for causing an N M I d uring t race com·
mands. The command handler is then entered to perform the com m and re·
qu est prompt.
Example: M O N ITR EQU 8 I N PUT CO D E FO R M O N ITR
LOO P CLRA PREPARE ZERO PAGE REG ISTER AN D

*
I N ITIALIZATIO N PARAM ETER
TFR A, D P S ET DEFAU LT PAG E VALUE
LEAS STACK, PCR S ETUP DEFAULT STACK VALU E
SWI REQ U EST SERVICE
FCB M O N ITR F U N CTION COD E BYTE
BRA LOO P REENTER I F FALLOUT OCCU RS
B-1 6
O UTC H Output a Character O UTC H
Code: 1
Arguments: Reg ister A contains the byte to transmit.
Result: The character is sent to the output handler

The character is set as fol lows O N LY if a Ll N E FEED was the character to
transmit:
CC = 0 if normal output occu rred.
CC = 1 if CAN CEL was entered d u ring output.
Description: If a FREEZE Occu rs (any i n put character is received) then control i s not
retu rned to the user routi n e u nt i l the condition is released. The F REEZE
cond ition i s checked for only when a l i n efeed is being sent. Padd i n g n u l l
characters (SOO) may be sent fol lowi n g the outputted character depend i ng
on the cu rrent sett ing of the N U LLS command. For DLE (Data Link Escape),
character n u l l s are never sent. Otherwise, carriage retu rns (SOO) receive the
n ew l i ne cou nt of n u l ls, all other characters the character count of n u l ls.
Example: OUTCH EQU 1 I N PUT COD E FOR OUTC H
LDA #'0 LOAD CHARACTER "0"

SWI SEN D OUT WITH M O N ITOR COD E
FCB OUTCH SERVICE CO D E BYTE
O UT2H S Convert Byte to Hex O UT2H S

Code: 4
Arguments: Reg ister X points to a byte to d i s p l ay i n hex.
Result: The byte is converted to two hex d i g its and sent to the output handler
fol lowed by a blank.
Example: OUT2HS EQU 4 I N PUT COD E FOR OUT2HS
LEAX DATA, PCR PO I NT TO ' DATA' TO DECODE

SWI REQU EST S ERV ICE
FCB OUT2HS SERVICE COD E BYTE
B-1 7
O UT4H S Convert Word to Hex O UT4H S
Code: 5
Arguments: Reg ister X pOi nts to a word (two bytes) to d i splay i n hex.
Result: The word i s converted to four hex d i g its and sent to the output handler
fol lowed by a blan k.
Example: O UT4HS EQU 5 I N PUT COD E FOR OUT4HS
LEAX DATA, PCR LOAD ' DATA' ADDRESS TO DECODE

SWI REQU EST ASSIST09 SERVICE
FCB OUT4HS SERVICE COD E BYTE
PAU S E Program Break and Check PAUS E

Code: 11
Arguments: None
Result: CC = 0 For a normal return.

CC = 1 If a CAN C E L was entered during the i nterim .
Description: The PAUSE service should b e used whenever a s i g n ificant amount o f pro
cessing i s done by a program without any external i nteraction (such as con
sole 110). Another use of the PAUS E service is for the monitori ng of FREEZE
or CAN C E L requests from the i nput hand ler. Th i s al lows m ult i-taski n g
operat i n g systems t o receive control and possi bly re-d i spatch ot her pro
g rams in a ti mesl i ce-l i ke fash ion. Testing for FREEZE and CAN CEL condi
tions is performed before return. Return may be after other tasks h ave h ad
a chance to execute, or after a F R E EZE condition is l i fted . I n a one task
system , ret u rn is always i mmed i ate u n l ess a FREEZE occu rs.
B·1 8
PC R L F Output t o N ext Line PC R L F
Code: 6
Arguments: None
Result: A carriage retu rn and l i ne feed are sent to the output hand ler.
C = 1 if normal output occurred.
C = 1 i f CONTROL-X was entered d u ring output.
Description: If a FR E EZE occurs (any i nput character is received), then control is not
ret u rned to the user routi ne u nt i l the cond ition is released . The string is
com pletely sent regard less o f any FREEZE or CAN CEL events occ u rri n g .
Pad d i n g characters may b e sent a s descri bed under t h e OUTCH service.
Example: PCRLF EQU 6 I N PUT CO D E PCRLF
SWI REQ U EST SERVICE

FCB PCRLF SERVICE CO DE BYTE
P DATA Send New Line and String P DATA

Code: 3
Arguments: Reg i ster X poi nts to an output stri ng term i n ated with an ASC I I EOT ($04).
Result: The string is sent to the output handler fol lowi ng a carriage retu rn and l i ne
feed .
CC = 0 if normal output occu rred.
CC = 1 if CONTRO L-X was entered d u ring output.
Description: The output string may contai n em bedded carriage ret urns and l i ne feeds
thus al low i n g several l i nes of d ata to be sent with one function cal l . If a
FR E EZE occurs (any i n put character is received), then control is not ret u rn
ed to the user routine until the cond ition is released . The stri ng is com p l ete
ly sent regard less of any FREEZE or CAN CEL events occurri ng. Pad d i n g
ch aracters may b e sent a s descri bed b y the OUTCH fu nction.
B-1 9
Send New Line and String
P DATA (Contin ued) P DATA
Example: PDATA EQU 3 I N PUT CODE FO R PDATA
MSGOUT FCC 'TH IS IS A M U LTI PLE LI N E M ESSAG E:

FCB $OA, $00 LI N E FEED, CARRIAG E RETU RN
FCC 'TH IS IS TH E S ECO N D LI N E.'
FCB $04 STR I N G TERM I N ATO R
LEAX M SGOUT, PCR LOAD M ESSAG E ADDRESS

SWI REQU EST A SERV I C E
F C B P DATA SERVICE CODE BYTE
P DATA1 Send Stri ng P DATA1

Code: 2
Arguments: Reg i ster X poi nts to an output string term i n ated with an ASC I I EOT ($04).
Result: The st ring i s sent to the output hand ler.

CC = 0 if normal output occ urred.
CC = 1 if CONTRO L-X was entered during out put .
Description: The output st ring m ay contai n e m bedded carriage returns and l i ne feeds
thus al lowi ng several l i nes of data to be sent with one function cal l . If a
FREEZE occu rs (any i n put character i s received), then control is not retu rn
ed to the user routi n e unt i l the condition is released . The stri ng i s com p l ete
ly sent regard less of any FREEZE or CAN CEL events occurri n g . Pad d i n g
characters may b e sent as described b y t h e OUTCH function.
Example: PDATA EQU 2 I N PUT COD E FOR P DATA1
MSG FCC 'TH IS IS AN OUTPUT STR I N G '

FCB $04 STR I N G TERM I N ATO R
LEAX M SG , PCR LOAD ' M SG ' STR I N G ADDRESS

SWI REQU EST A SERV I C E
FCB PDATA1 SERVICE COD E BYTE
B-20
SPAC E Single Space O utp ut SPAC E
Code: 7
Arguments: N one
Result: A space is sent to the output hand l er.
Descript ion: Padd ing characters may be sent as descri bed under the OUTCH service.
Example: SPACE EQU 7 I N PUT CO DE SPACE

SWI REQU EST ASS IST09 SERV ICE
FCB SPACE SERVICE COD E BYTE
VCT RSW Vector Swap VCT RSW

Code: 9
Arguments: Reg ister A contai ns the vector swap i n put code.

Reg i ster X contains zero or a rep l acement val ue.
Result: Reg ister X contai ns the previous val ue for the vector.
Description: The vector swap service exam i nes/alters a word entry in the ASSI ST09 vec
tor table. Th is tabl e contai n s pOi nters and default val ues used d u ri n g
mon itor processing. The entry is repl aced w i t h the value contained i n the X
reg i ster un less it i s zero. The codes ava i l able are l i sted i n Tab l e B·3.
Example: VCTRSW EQU 9 I N PUT CODE VCTRSW

. I RQ EQU 12 I RQ APPEN DAG E SWAP FU N CT I O N
CO DE
LEAX MYIRQ H , PC R LOAD N EW I RQ HAN DLER A D D R ESS

LOA I. I RQ LOAD SU BCOD E FOR V ECTOR SWAP
SWI R EQU EST SERVICE
FCB VCTRSW S ERVICE CO DE BYTE
X N OW HAS TH E PREVIOUS APPEN DAG E ADDRESS
B·21
B.1 0 V ECTO R SWAP SERV I C E
The vector swap service al lows u ser modifications of the vector table to be easily i nstal l
ed. Each vector hand ler, i n c l u d i n g the one for SWI , perform s a val i d ity check on the stack
before any other processi n g . If the stack is not pOinting to val i d RAM , it is reset to the in
itial val ue passed to the M O N ITR request which f i red-up ASSIST09 after RESET. Al so, the
cu rrent reg i ster set i s pri nted fol low ing a "?" (q uestion m ark) and then the command
hand l er is entered . A l i st of each entry i n the vector tabl e i s g iven in Table 8-3.
Table B·3. Vector Table Entries
Entry Code Description

. AVTB L 0 Returns address of vector table
. C M D Ll 2 Primary command list
. R SVD 4 Reserved M C6809 interru pt vector a ppendage
. SWI3 6 Software interrupt 3 interrupt vector appendage
. SWI2 8 Software interrupt 2 interrupt vector appendage
. FI R O 10 Fast interrupt request vector appendage
. I RO 12 Interrupt request vector appendage
. SWI 14 Software interrupt vector appendage
.NMI 16 Non-maskable interrupt vector appendage
. R ES ET 18 Reset interrupt vector a ppendage
. CION 20 I nput console intiialization routine
. C I DTA 22 I nput data byte from console routine
. CIOFF 24 I nput console shutdown routine
. COON 26 Output console initialization routine
. CO DTA 28 Output/ data byte to console routine
. COOFF 30 Output console shutdown routine
. H S DTA 32 High speed display handler routine
. B SON 34 Punch/ load initialization routine
. B S DTA 36 Punch / l oad handler routine
. B SOFF 38 Punch / l oad shutdown routine
. PAU S E 40 Processing pause routine
. C M D L2 44 S econdary command list
. ACIA 46 Address of ACIA
. PAD 48 Character and new line pad counts
. ECHO 50 Echo flag
. PTM 52 Programmable timer module address
The follow i n g pages describe the p urpose of each entry and the req u i rements which
m u st be met for a user replaceable val ue or routi n e to be successf u l ly substituted .
8-22
.ACIA ACIA Address .ACIA
Code: 46
Description: This entry contains the add ress of the ACIA used by the defau lt console in
put and output device handlers. Standard ASSI ST09 i n itial ization sets this
val ue to hexadec imal E008. If this m ust be altered , then it m ust be done
before the M O N ITR start u p service i s i nvoked , si nce that service cal l s the
.COO N and .CO I N i nput and output device i n itial ization routi nes which i n
itial ize the ACIA pOi nted to by this vector slot.
.AVT B L Return Address of Vector Table .AVT B L

Code: 0
Description: The add ress of the vector table is ret u rned with this code. Th is al lows m ass
changes to the table without i n d ividual cal l s to the vector swap service.
The code val ues are i dentical to the offsets i n the vector table. Th is entry
shou l d n ever be changed , only exam i ned.
8-23
. BS OTA P unch/Load H andler Routine . BS OTA
Code: 36
Description: Th i s entry contains the address of a routine which performs p u n c h , load ,

a n d verify operat ions. The . BSON routine is always executed before the
rout i n e is g iven contro l . Th is routine is g iven the same parameter l i st
documented for . BSO N . The default hand ler uses the .CO OTA ro ut i n e to
punch or the .CI OTA rout ine to read data i n S1 /S9 (M I KBUG) format. The
function code byte must be exami ned to determ ine the type req uest bei n g
hand led .
A ret u rn code m ust be given which reflects the f inal processing d i s position :
Z= 1 Successfu l com plet ion
or
Z=0 Unsuccessful com plet ion .
The . BSOFF rout i n e w i l l be cal l ed after this rout ine i s completed .
. BSO F F Punch/Load Sh utdown Routine . BSO F F

Code: 38
Description: This entry points to a su broutine which i s des i g n ated to term i n ate d evice
processing for the punch, load , and verify handler . BS OTA. The stack con
tains a parameter l i st as documented for the . BSO N entry. The d efault
ASSIST09 routine issues OC4 ($1 4 or stop) and OC3 ($1 3 or x-off) fol lowed
by a one second delay to g ive the reader/punch t i m e to stop. Also, an i nter
nally used fl ag by the I N CH P service rout ine is c leared to reverse the ef
fect caused by its sett ing in the . BSON handler. See that descri ption for an
exp l anation of the proper use of this f l ag .
B-24
. BSO N Punch/Load Initialization Routine . BSO N
Code: 34
Description: T h i s entry poi nts to a su brout ine with the assig ned task of turning on the
device used for punch, load, and verify processi n g . The stack contai ns a
parameter l i st descri bing which funct ion is req uested. The defau lt rout i ne
sends an ASC I I "reader on" or "punch on" code of DC1 ($1 1 ) or DC2 ($1 2)
respectively to the output handler ( .CODTA) . A flag is a lso set which
d i sables test for FREEZE conditions d uri ng I N CH N P processi n g . Th is is
done so characters are not lost by be i n g i nterpreted as FREEZE mode in
d i c ators. If a user replacement rout i n e a lso uses the I N CH N P service, then
it a l so should set this same byte non-zero and clear it i n the . BSO F F
routi ne. The ASSIST09 source l i sting should b e consu lted for t h e location
of this byte.
The stack is setup as fol l ows:

S + 6 = Code byte, VERI FY ( - 1 ), PU NCH (0) , LOAD (1 )
S + 4 = Start address for punch o n ly
S + 2 = End address for punch, or offset for READ/LOAD
S + 0 = Return address
.CI OTA Input Data Byte from Console Routine .CI OTA
Code: 22
Description: This entry determ i nes the console i n put handler appendage. The respon
s i b i l ity of this routine i s to furnish the req uested next i n put character in the
A reg ister, if avai lable, and ret urn with a cond ition code. The I N CH P ser
vice routine cal l s this appendage to supply the next ch aracter. Also, a
" F R E EZE" mode routine cal ls at various ti mes to test for a FREEZE condi
tion or determ ine if the CAN CEL key has been entered . Processi n g for t h i s
appendage m ust abide by t h e follow i n g conventions:
Input: PC - ASSIST09 work page
S- Return add ress
Output: C = 0, A = i n put character
C = 1 if no i n put character is yet avai l able
Vol atile Registers: U , B
The hand ler shou ld always pass contro l back i m med i ately even if no
character i s yet available. Th is enables other tasks to do product ive work
w h i l e i n put is unavai lable. The defau lt rout ine reads an ACI A as explai ned
in Parag raph B.2 Implementation Req u i rements.
B-25
.CI O F F Input Console Shutdown Routine .CIO FF
Code: 24
Description: Th is entry points to a rout i n e which is cal led to term i nate i n put processing.
It is not cal l ed by ASS IST09 at any time, but is incl uded for consistency.
The defau lt routine merely does an " RTS". The environment is as fol l ows:
Input: None
Output: I n put device term i nated
Volatile Registers: None
.CI O N Input Console I nitialization Routine .CI O N

Code: 20
Description: Th i s entry i s cal led to i n itiate the in put device. It is cal led once d u ring the
M O N ITR service which i n itial izes the monitor so the . command processor
m ay obtain commands to p rocess. The defau lt hand ler resets the ACIA
used for standard i nput and output and sets up the fol lowing default condi·
tions: 8-bit word length, no parity checki ng, 2 stop bits, divide·by·1 6 counter
ratio. The effect of an 8·bit word with no parity checking is to accept 7·bit
ASCI I and i g nore the parity bit.
Input: .ACIA Memory address of the ACIA
Output: The output device is i n itial ized
Volatile Registers: A, X
8·26
.CM D L 1 Primary Comm a nd List .C M D L 1
Code: 2
Description: User suppl ied com mand tables m ay either subst itute or re place the
ASSI ST09 standard tables. The co mmand hand ler scans two l i sts, the
primary table f i rst fo l lowed by the secondary table. The primary table is
poi nted to by this entry and contains, as a defau lt, the ASSIST09 com m and
table. The secondary table defaults to a n u l l l i st . A user may insert their own
table i nto either position. If a user l i st is i nstal led i n the secondary table
position, then the ASSI ST09 l i st wi l l be searched f i rst . The default
ASS I ST09 l i st contains all one character com m and names. Th us, a user
com mand " PRI NT" would be matched if the l etters " PR" are typed , but not
j ust a " P" si nce the system command l ist wou l d match first . A user m ay
rep l ace the primary system l i st if des i red . A command is chosen on a f i rst
match basis com pari ng only the character(s) entered . Th is means that two
or more commands may have the same i n itial characters and that if only
that much i s entered then the fi rst one i n the l i st(s) i s chosen.
Each entry i n the users com mand l i st m ust have the fo l l owing form at :
+0 FCB L Where " L" is the s ize of the entry i n
c l ud i n g t h i s byte
+1 FCC ' < stri ng > ' Where " < stri ng > " is the com m and
name
+N FOB EP - * Where " EP" represents the sym bo l de
f i n i ng the start of the command rou
t i ne
The f i rst byte is an entry length byte and is always three more than the
lengt h of the command stri ng (one for the length itself plus two for the
routi ne offset). The command st ri ng m ust contai n only ASC I I al phan u meric
characters, no spec ial characters. An offset to the start of the com mand
routine i s used i n stead of an absol ute add ress so that position
i ndependent prog rams may contain command tables. The end of the com
mand table is a one byte flag . A - 1 ($F F) spec ifies that the secondary table
i s to be searched , or a -2 ($FE) that command l i st search ing is to be ter
m i n ated. The table represented as the secondary command l i st m u st end
with - 2. The f i rst l i st m ust end with a - 1 if both l i sts are to be searched , or
a - 2 i f o n ly one l i st i s to be used .
A com mand rout ine i s entered with t h e fol l ow i n g reg isters set:
DPR- ASS IST09 page work area.
S- A ret urn address to t h e command processor.
Z= 1 A carriage return term i nated the command name.
Z=0 A space del i m iter fol lowed the com m and name.
B-27
.CM D L 1 Primary Command List
(Continued) .CM D L 1
A com m and ro utine is entered after the del i m iter fol low ing the command
name is typed i n . Th is means that a carriage ret u rn m ay be the d e l i m iter
entered with the i n put device rest i n g on the next l i ne. For this reason the Z
bit i n the condition code is set so the command routi n e m ay determ i ne the
c u rrent position of the i n put device. The com mand routine sho uld ensure
that the console device is left on a new l i ne before returning to the com
m and h andler.
.CM D L2 Secondary Command List .C M D L2

Code: 44
Description: T h i s entry poi nts to the second l i st table. The defau lt is a n u l l l i st fol lowed
by a byte of 2. A com plete expl an ation of the use for t h i s entry is provided
-
under the description of the .CM D L 1 entry.
.CO DTA Output Data Byte to Console Routine .CO DTA

Code: 28
Description: The responsib i l ity of this handler i s to send the character i n the A reg i ster
to the output device. The default rout ine al so fol lows with paddi ng
characters as explai ned i n the description of the O UTCH service. If the out
put device is not ready to accept a character, then the " pause" subroutine
should be cal led repeated ly wh i l e this cond ition l asts. The address of the
pause routine i s obtained from the . PAUSE entry i n the vector table. The
character counts for padding are o btai ned from the . PAD entry i n the table.
Al l ASSI ST09 output is done with a cal l to this appendage. Th is incl udes
punch p rocessi n g as wel l . The default routine sends the character to an
ACI A as explai ned i n Paragraph 8.2 I m plementation Req u i rements. The
operat i n g environment i s as fol lows:
Input: A = Character to send
DP = ASSI ST09 work page
. PAD = Character and new l i n e padd ing cou nts
(i n vector table)
. PAUSE = Pause routine (i n vector table)
O ut put: Character sent to the output d evice
Volatile Registers: None. Al l work reg isters m ust be restored
8-28
.COO F F Output Console Sh utdown Routine . COO F F
Code: 30
Descript ion: This entry addresses the rout ine to term i n ate output device processi n g .
ASSIST09 does not cal l t h i s rout ine. It is incl u ded for com pleteness. The
defau lt routine is an " RTS".
Input: D P - ASSI ST09 work page
Output: The output device is term i n ated
Vol at i l e Registers: None
.COO N Output Console Initial ization Routine .COO N

Code: 26
Description: This entry points to a routine to i n itial ize the standard output device. The
defau lt ro ut i ne i n it i a l izes an ACIA and is the very same one descri bed
u nder the .CI O N vector swap def i n ition.
Input: .ACIA vector entry for the ACIA add ress
O utput: The output device is i n it i al ized
Vol atile Registers: A, X
8·29
. EC H O Echo Flag . EC H O
Code: 50
Description: The fi rst byte of this word is used as a flag for the I N CH P service rout ine
to determ i ne the requ i rement of echoing i n p ut received from the i n put
hand ler. A non-zero value means to echo the i n p ut; zero not to echo. The
ec hoing w i l l take place even if user handlers are substituted for the defau lt
.CI DTA handler as the I N C H P service routine performs the echo .
. FI RQ Fast Interrupt Request Vector Appendage . FI RQ

Code: 10
Description: The fast i nterru pt request rout i n e is located via this poi nter. The M C6809
add resses hexadecimal FFF6 to l ocate the hand le r when p rocessi ng a
F I RQ. The stack and mach ine status is as defi ned for the F I RQ i nterrupt
u pon entry to this appendage. It should be noted that t h i s rout i ne is
"j u m ped " to with an i n d i rect jump i n struction which adds eleven cycles to
the i nterru pt time before the handler actual ly receives contro l . The default
handler does an i m med i ate " RT I " which, i n essence, i g nores the i nterrupt.
8-30
. H S DTA High Speed Display Handler Routine . H S DTA
Code: 32
Description: This entry is i nvoked as a su broutine by the D ISPLAY command and passed
a parameter l i st contai n i ng the "TO" and " FROM " add resses. The from
val u e is rou nded down to a 1 6 byte add ress boundary. The defau lt routine
displays memory i n both hexadecimal and ASC I I rep resentations, with a
t itle produced on every 1 28 byte boundary. The p urpose for this vector table
entry i s for easy i m plementation of a user rout ine for spec ial pu rpose
hand l i n g of a block of data. (The data cou l d , for exam ple, be sent to a high
speed pri nter for l ater analysis.) The parameters are a l l passed on the
stack. The envi ronment is as fol lows:
Input: S + 4 = Start add ress
S + 2 = Stop address
S + 0 = Return Add ress
D P - ASSIST09 work page
Output: Any p urpose desi red
Volatile Registers: X, 0
.I RQ Interrupt Request Vector Appendage . I RQ

Code: 12
Description: A l l i nterrupt req uests are passed to the rout i n e poi nted to by this vector.
H exadeci m a l FFF8 is the M C6809 location w here t h i s i nterrupt vector i s
fetched. The stack a n d processor status i s that defined f o r t h e I RQ i nter
rupt upon entry to the hand ler. Since the routi ne's address is in the vector
table, an i n d i rect j u m p must be done to i nvoke it. Th is adds eleven cycles to
the i nterrupt ti me before the I RQ handler receives contro l . The default I RQ
handler pri nts the reg isters and enters the ASSIST09 command handler.
8·31
.N M I Non·M askable Interrupt Vector Appendage .N MI
Code: 16
Description: Th is entry pOints to the non-maskable interrupt handler to receive control

whenever the processor branches to the address at hexadeci m a l FF FC.
S i nce ASSIST09 uses the N M I i nterru pt d u ring trace and breakpoi nt pro
cess i n g , such commands sho u l d not be used if a user handler is in control .
Th is is true u n less the user handler has the i ntel l i gence to forward control
to the default handler if the NMl i nterrupt has not been generated d u e to
u ser fac i l ities. The NMT handler g iven control wi l l have an e l even cycle
overhead as its address m u st be fetched from the vector table .
. PA D Character and New Line Pad Count . PAD

Code: 48
Description: Th is entry contains the pad count for characters and new l i nes. The f i rst of
the two bytes is the count of n u l l s for other characters, and the second is
the n u m ber of n u l ls (SOO) to send out after any l i ne feed is transmitted . The
ASCI I Escape character (S1 0) never has n u l l s sent fol lowing it. The d efault
.CODTA handler is responsible for transm itting these n u l ls. A user handler
m ay or may not use these counts as req u i red .
The " N U LLS" com mand a lso sets these two bytes with user specified
values.
8-32
. PAUS E Processing Pause Routine . PAU S E
Code: 40
Description: I n o rder to support real-t i m e (also known as mult i-taski ng) envi ronments
ASSI ST09 cal ls a dead-time ro ut i ne whenever processing must wait for
some external change of state. An exa mple would be when the OUTCH ser
vice routine attem pts the sendi n g of a character to the ACIA through the
default .CODTA hand ler and the ACI A status reg isters shows that it can not
yet be accepted. The defau lt dead-t i m e rout ine resides in a reserved fou r
byte area which contains t h e s i n g l e i n struction, " RTS". The . PAUSE vector
entry poi nts to this routine after standard i n itial ization. This poi nter m ay be
changed to point to a user routine w hich d ispatches ot her prog rams so that
the M C6809 may be ut i l ized more efficiently. Another exam ple of use wo u l d
be t o i n c rement a cou nter s o that dead-t i m e cycle counts may be ac
c u m u l ated for stat i st ical or debug g i ng p urposes. The reason for the fou r
byte reserved area (wh i ch exists i n the ASSI ST09 work page) is so other
code may be overlayed without the need for another space i n the address
map to be assigned. For example, a master mon itor may be usi ng a memory
management unit to assign a com plete 64 K block of memory to ASSI ST09
and the prog rams bei n g executed/tested under ASS I ST09 contro l . The
master mon itor wishes, or course, to be reentered when any "dead t i m e "
occ u rs, s o it overlays the default rou t i n e (" RTS") w i t h i t s o w n "SW I " . S i nce
the m aster mon itor wou l d be "front e nd ing" al l "SWI 's" anyway, it knows
when a "pause" call is being pe rformed and can red i spatch ot her systems
on a t i me-sl ice basis.
Al l reg i sters m ust be transparent across the pause hand l er. Along w ith
selected poi nts i n ASSIST09 user service processi n g , there i s a special ser
vice cal l specifical ly for user program s to i nvoke the pause rout ine. It m ay
be suggested that i f no servi ces are bei ng req uested for a g iven time period
(say 10 ms) user programs should cal l the . PAUSE service rout ine so that
fai r-task d ispatch i n g can be g uaranteed .
. PTM Programm able Timer Module Address . PT M

Code: 53
Description: Th i s entry contains the add ress of the M C6840 program mable timer mod u le
(PT M ). Alterat ion of t h i s slot shoul d occur before the M O N ITR start u p ser
vice i s cal led as explai ned i n Parag raph 8.4 I n itial izat ion. If no PTM i s
ava i lable, then t h e address s h o u l d b e changed t o a zero s o that no i n
it ial izat ion attem pt w i l l take p l ace. N ote that i f a zero i s suppl ied, ASSI ST09
B reakpo i nt and Trace com mands should not be issued.
8-33
. RESET Reset Interrupt Vector Appendage . R ESET
Code: 18
Description: T h i s entry returns the add ress of the RES ET rout i ne which i nitial izes
ASS IST09. Chang i n g it has no effect , but it is i nc l uded in the vector table i n
c ase a user program w ishes to determi ne where t h e ASS I ST09 restart code
resides. For exam ple, if ASSIST09 resides in the memory map such that it
does not control the MC6809 hardware vectors, a user routine m ay wish to
start it up and thus need to obtai n the standard R ESET vector code ad
d ress. The ASSI ST09 reset code assigns the default in the work page, cal l s
the vector b u i l d subrout ine, and then starts ASSI ST09 proper w i t h the
M O N ITR service cal l .
. RSV D Reserved M C6809 Interrupt Vector Appendage . RSV D

Code: 4
Description: Th i s i s a poi nter to the reserved i nterrupt vector rout ine addressed at hex
adec imal F F FO. Th is M C6809 hardware vector is not defi ned as yet. The
default rout i n e setup by ASSIST09 w i l l cause a reg ister d i sp l ay and en
trance to the com m and handler.
.SWI .SWI
Softare Interrupt Vector Appendage
Code: 14
Description: This vector entry contains the address of the Software I nterru pt routine.
N ormal ly, ASSIST09 hand les these i nterrupts to provide services for user
p rog rams . If a user handler is i n place, however, these fac i l ities cannot be
u sed u n l ess the user routi n e "passes on" such requests to the ASS IST09
default handler. Th is is easy to do, si nce the vector swap fu nct ion passes
back the address of the default handler when the switch is m ade by the
u ser. Th i s "front ending" allows a user routine to exam ine all serivce cal l s ,
or alter/replace/extend them to his requ i rements. Of cou rse, the reg i sters
m u st be t ransparent across the transfer of control from the user to the
standard handler. A "J M P" i n struction branches d i rect ly to the routi ne
poi nted to by this vector entry when a SWI occurs. Therefore, the envi ron
ment is that as defined for the "SWI " i nterrupt.
.SWI2 Software Interrupt 2 Vector Appendage .SWI2

Code: 8
Description: Th i s entry contains a poi nter to the SWI2 hand ler entered whenever that in
struction i s executed . The status of the stack and machine are those defi n
ed for the SWI2 i nterrupt which has its i nterrupt vector add ress at F F F4
h exadec i m a l . The default handler pri nts the regi sters and enters the
ASSIST09 command handler.
B-35
.SWI3 Software Interrupt 3 Vector Appendage .SWI 3
Code: 6
Description: Th is entry contai ns a poi nter to the SWI3 handler entered whenever that i n
struction is executed . The status of the stack and m ach ine are those defin
ed for the SWI3 i nterurpt which h as its i nterru pt vector add ress located at
hexadecimal F F F2. The default handler prints the reg isters and enters the
ASSIST09 co mmand handler.
8-36
8.1 1 MON ITO R LIST I N G
T h e follow i n g pages contai n a l i st i n g of the ASSI ST09 mon itor.
PAG E 001 AS S I ST0 9 . S A : 0 ASS I S T0 9 - M C 6 8 0 9 MON I TOR
00001 TTL AS S I ST 0 9 - M C 6 8 0 9 MON I TOR

00002 OPT ABS , L LE= 8 5 , S , C RE
00004 *************************************
00005 * COPY RIGHT ( C ) M OTO ROLA , I N C . 1 9 7 9 *
00006 ***** ********************************
0 00 0 8 *** * * * * * * ******************* *********

0 00 0 9 * TH I S IS THE BAS E AS S I ST 0 9 ROM .
00010 * IT MAY RUN W I T H OR WITHOUT TH E
00011 * EXTENS I ON ROM WH I CH
00012 * WHEN PRE S ENT W I L L BE AUTOMAT I CALLY
00013 * INCORPORAT E D BY THE BLDVTR
00014 * SUBROUT I N E .
00015 *************************************
00017 *********************************************
0 00 1 8 * G LOBAL MODU LE EQUAT E S
00019 ********************************************
0 00 2 0 F800 A ROMBEG E Q U $F800 ROM START ASS EMBLY ADDRE S S
00021 E7 0 0 A RAMOFS EQU -$ 1 9 0 0 ROM OF F S ET TO RAM WORK PAGE
00022 0800 A ROM S I Z E QU 20 4 8 ROM S I Z E
00023 FOOO A ROM 20F E QU ROMBEG- ROMS I Z START OF EXTENS ION ROM
00024 E0 0 8 A AC I A EQU $E0 0 8 DEFAULT AC I A ADDRES S
00025 EO O O A PTM EQU $EO OO DEFAULT PTM ADDRE S S
00026 0000 A DFTC H P EQ U 0 DE FAULT CHARACTER PAD COUNT
00027 0005 A DFTN LP EQU 5 DE F AU LT NEW L I N E PAD COUNT
0 00 2 8 003E A PROMPT EQU ,> P ROMPT CHARACTER
00029 OQ 0 8 A NUMBKP EQU 8 NUMB E R OF BREAK PO I NTS
0 00 3 0 *********************************************
0 00 3 2 *********************************************
00033 * M I SC E LANEOUS EQU AT E S
0 00 3 4 ************** ************* ******************
0 00 3 5 0004 A EOT EQU $04 E N D O F TRANSM I S S I ON
00036 0007 A BELL EQU $07 BE L L CHARACTER
00037 OOOA A LF EQU $OA LINE FEED
00038 0000 A CR EQU $00 CARR I AGE RETU RN
0 00 3 9 0010 A DLE EQU $10 DATA L I N K ESCAPE
00040 0018 A CAN EQU $18 CAN C E L ( CTL- X )
00041 * p'rM ACC E S S DEF I N I T IONS
00042 EO O l A PT M ST A EQU PTM+ l RE AD STATUS REG I STER
00043 EO O O A PTMC 1 3 EQU PTM CONTROL REG I STERS 1 AN D 3
0 00 4 4 EO O l A PTMC 2 EQU PTM+ l CONT ROL REG ISTER 2
0 00 4 5 E0 0 2 A P T M T M l BQU PTM + 2 LATCH 1
0 00 4 6 E0 0 4 1\ PTMTM2 EQU PTM+ 4 LATCH 2
00047 E0 0 6 A PTMTM3 EQU PTM+6 LATCH 3
00049 008C A SKIP2 EQU $8C " CM P X # n O PCODE - SK I P S TWO BYTES
00051 *******************************************
00052 * AS S I ST0 9 MON ITOR SW I F U N C T I O N S
8-37
PAG E 00 2 ASS I ST0 9 . SA : 0 AS S I S T0 9 - MC6 8 0 9 MON I TOR
0 00 5 3 * THE FOLLOW I NG EQUA'fES DE F I NE F U NC'nONS PROV I D E D

00054 * B Y THE ASS I S'r0 9 MON ITOR V I A THE SWI INSTRUCT ION .
00055 ******************************************
00056 0000 A I N CHNP EQU 0 I NPUT CHAR IN A REG - NO PAR I TY
0 00 5 7 0001 A OUTCH EQU 1 OUT PUT CHAR FROM A REG
00058 00 0 2 A PDATAl EQU 2 OUTPUT STRI NG
0 00 5 9 0003 A PDATA EQU 3 OUTPUT CR/LF THEN STRI NG
00060 0004 A OUT 2 H S EQU 4 OUTPUT TWO HEX AN D S PAC E
00061 000 5 A OUT4 HS EQU 5 OUTPUT FOU R HEX AN D S PAC E
00062 0006 A PCRLF EQU 6 OUT PUT CR/LF
0 00 6 3 0007 A SPACE EQU 7 OUTPUT A S PACE
0 00 6 4 0008 A MON ITR EQU 8 ENT E R AS S I ST0 9 MON I TOR
00065 0009 A VCTRSW EQU 9 VECTOR EXAM I NE/SWITCH
00066 OOOA A SRKPT E QU 10 USER PROGRAM BREAK PO I NT
00067 OOOB A PAUS E EQU 11 TAS K PAU S E F UNCT ION
0 00 6 8 OOOB A NUMFUN EQU 11 NU MBER O F AVA I LAB LE FUNCTIONS
00069 * N EXT S U B-CODES FOR ACC E S S I NG THE VECTOR TAB LE .
0007 0 * THEY ARE EQU IVALENT To O F F S ETS I N THE TAB LE .
00071 * RE LAT IVE POS l 'r I ON I NG MUST BE MA I NTAI N F; D .
00072 0000 A . AVTBL EQU 0 ADDRE S S OF VECTOR TABLE
0 00 7 3 000 2 A . C M DLl EQU 2 F I RST COMMAND L I ST
00074 0004 A . RSVD EQU 4 RE S E RVED HARDWARE VECTOR
00075 0006 A . SW I 3 EQU 6 5W I 3 ROUT I NE
0 00 7 6 0008 A . SW I 2 EQU 8 SWI 2 ROUT I NE
0 00 7 7 OOOA A . F I RQ EQU 10 F I RQ ROUT I NE
00078 OOOC A . I RQ EQU 12 I RQ ROUT I N E
0 00 7 9 OOOE A . SWI EQU 14 SW I ROUT I N E
00080 0010 A .NMI EQU 16 NM I ROUT I N E
00081 0012 A . RE S ET EQU 18 RE S ET ROUT I NE
0 0082 0014 A . C ION EQU 20 CONSOLE ON
0 00 8 3 0016 A . C I DTA EQU 22 CONSOLE INPUT DATA
00084 0018 A . C IOFF EQU 24 CONSOLE I N PUT OFF
00085 001A A . COON E QU 26 CONSOLE OUTPUT O N
0 00 8 6 001C A . C O DTA EQU 28 CON SOLE OUTPUT DATA
0 0087 001E A . COOF F EQU 30 CONSOLE OUTPUT O F F
0 00 8 8 0020 A . H SDTA EQU 32 H I GH S P E E D PRI NTDATA
00089 0022 A . SSON EQU 34 PUNCH/LOAD ON
0 00 9 0 00 24 A . SS DTA EQU 36 PUNCH/LOAD DATA
00091 0026 A . SSOFF EQU 38 PUNCH/LOAD OF F
00092 0028 A . PAUSE EQU 40 TAS K PAUSE ROUT I N E
0 00 9 3 0 0 2A A . EX PAN EQU 42 EXP RE S S ION ANALY Z E R
0 00 9 4 0 0 2C A . CM DL2 EQU 44 SECOND COMMAND LI ST
00095 002E A . AC I A EQU 46 AC I A ADDRE S S
00096 00 3 0 A . PAD EQU 48 CHARACTER PAD AND NEW L I N E PAD
00097 0032 A . ECHO E QU 50 ECHO/LOAD AN D NULL BKPT F LAG
0 00 9 8 0034 A . PTM EQU 52 PTM ADDRE S S
0 00 9 9 001B A NUMVTR EQU 52/2+1 N U M B E R OF VECTORS
0 0100 0034 A H I VTR EQU 52 H I G H EST VECTOR O F F S E T
8-38
PAG E 003 AS S I ST0 9 . S A : 0 AS S I ST0 9 - M C 6 S 0 9 MON ITOR
0010 2 ******************************************
00103 * WORK AREA
00104 * TH I S WORK AREA IS AS S I G N E D TO THE PAGE ADDRE S S E D BY
0010 5 * -S l S 0 0 , PCR FROM THE BAS E ADDRE S S OF THE AS S I S T 0 9
0 0106 * ROM . THE D I RE CT PAGE RE G I ST E R DURI NG MOST ROUT I NE
00107 * OPERAT I ONS WI LL PO I NT TO TH I S WORK AREA . THE STACK
0 010S * I N I T I ALLY STARTS U N D E R THE RE S E RV E D WORK AREAS AS
00109 * DEF I N E D HERE I N .
00110 ******************************************
0 0111 DFO O A WORKPG EQU ROMB E G + RAMO F S S ETU P D I RECT PAG E ADDRE S S
00112 O O DF A SETDP WORK PG ! > S NOT I F Y AS S E MB LER
0 0 1 l 3 A EO O O ORG WORKPG+ 2 5 6 READY PAG E DEF I N I T I ONS
0 0114 * THE FO LLOW I NG THRU BK PTOP MUST RE S I DE I N TH I S ORDE R
00115 * FOR PROPER I N I T I AL I Z AT I ON
0 0 1 l 6A DFFC ORG *-4
00117 DFFC A PAU S E R EQU * PAUS E ROUT I N E
O O l l S A DFFB ORG *-1
00119 DF F B A SW I B F L EQU * BYPASS SWI AS BREAK PO I NT F LAG
0 0 1 2 0 A DFFA ORG *-1
00121 DFFA A BK PTCT EQU * BREAK PO I NT COUNT
0 0 1 2 2A DF F S ORG *-2
00123 DF F S A SLEVEL EQU * STACK TRAC E LEVEL
0 0 1 2 4 A DFC 2 ORG *-NUMVTR* 2
00125 DFC 2 A VECTAB EQU * VECTOR TAB LE
0 0 1 2 6 A DF B 2 ORG * - 2 * NU M B K P
00127 DF B 2 A BK PTBL EQU * BREAKPO I NT TABLE
0 0 1 2 S A DFA2 ORG *-2* NUMBKP
00129 DFA2 A BK PTOP EQU * BREAK PO I NT OPCODE TAB LE
0 0 l 3 0 A DFAO ORG *- 2
00131 DFAO A WI NDOW EQU * W I N DOW
0 0 1 3 2A DF 9 E ORG *-2
00133 DF9E A ADDR EQU * ADDRES S PO I NT E R VALUE
0 0 1 3 4A D F 9 D ORG *-1
00135 DF 9 D A BAS E PG EQU * BAS E PAG E VALU E
*- 2
0 0 1 3 6 A DF 9 B ORG
00137 DF 9 B A NUMBE R EQU * B INARY BU I LD AREA
0 0 1 3 SA DF99 ORG *-2
00139 DF 9 9 A LASTOP EQU * LAST OPCODE TRACE D
0 0 1 4 0 A DF 9 7 ORG *-2
00141 DF 9 7 A RSTACK EQU * RE S ET STAC K PO I NT E R
0 0 1 4 2A DF 9 5 ORG *-2
00143 DF 9 5 A PSTACK EQU * COMMAN D RECOVE RY STACK
0 0 1 4 4 A DF 9 3 ORG *-2
00145 DF 9 3 A PCNTER EQU * LAST PROG RAM COUNTER
0 0 1 4 6 A DF 9 1 ORG *-2
00147 DF 9 1 A TRAC E C EQU * TRAC E COUNT
0 0 1 4 S A DF 9 0 ORG *-1
*
00149 DF 9 0 A SW I C NT EQU TRACE " SW I " N E ST LEVE L COU NT
0 0 1 5 0 A DF S F ORG *-1 ( M I S F LG MUST FOLLOW SW I CN T )
00151 DF S F A M I S F LG EQU * LOAD CMD/T H RU BREAK PO I NT F LAG
0 0 1 5 2A DF S E ORG *-1
00153 DF S E A DEL I M EQU * EXPRESS I ON DE L I M IT E R/WORK BYTE
0 0 1 5 4 A DF 6 6 ORG *-40
00155 DF 6 6 A RO M2WK EQU * EXTE NS ION ROM RE S E RVED AREA
0 0 1 5 6 A DF 5 1 ORG *-21
00157 DF 5 1 A TSTACK EQU * TEMPORARY STACK HOLD
0015S DF 5 1 A STACK EQU * START OF I N IT I A L STACK
8-39
P AG E 004 AS S I ST0 9 . SA : 0 ASS I ST0 9 - MC6 8 0 9 MON I TOR
00160 ******************************************
0 0161 * DEFAULT THE ROM BEG I N N I NG ADDRES S TO ' ROMBEG '
00162 * AS S I ST0 9 IS POS I T I ON ADDRE S S I N DE P E N DENT , HOWEVE R
00163 * WE AS S EM B LE AS S UM I NG CONTROL OF TH E HARDWARE VECTORS .
00164 * NOTE THAT THE WORK RAM PAG E MUST BE ' RAMOFS '
00165 * F ROM THE ROM BEG I N N I NG ADDRE S S .
0 0166 * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * *
0 01 67A F 8 0 0 ORG ROMBEG ROM ASS EM B LY/DEFAULT ADDRE S S
0 0169 ************* ****************************************

00170 * BLDVTR - BU I L D AS S I ST0 9 VECTOR TAB LE
00171 * HARDWARE RE SET CALLS TH I S SUBROUT I N E TO BU I LD TH E
0 01 7 2 * AS S I ST0 9 VECTOR TABLE . TH I S S U B ROU T I N E RE S I DE S AT
00173 * THE F I RST BYTE OF THE AS S I ST0 9 ROM , AN D CAN BE
0 01 7 4 * CALLED V I A EXT E RNAL CONTROL CODE FOR RE MOTE
00175 * A S S I ST0 9 EXECUT I ON .
00176 * I NPUT : S- > VAL I D STACK RAM
00177 * OUTPUT : U- >VECTOR TABLE ADDRE S S
0 0178 * DPR- > AS S I ST0 9 WORK AREA PAGE
0 0 1 79 * THE VECTOR TAB LE AND DEFAULT S ARE I N I 'r I AL I Z E D
0 0 1 80 * ALL REG I ST E RS VOLAT I LE
00181 *************************************************
0 0 1 8 3A F800 30 8 0 E7 BE BLDVTR LEAX VECTAB , PCR ADDRE S S VECTOR TABLE

0 0 1 8 4A F804 IF 10 A TFR X,D OBTA I N BAS E PAGE ADDRE S S
0 0 1 8 5A Fa06 IF 8B A TF R A , DP SETU P DP R
0 0 1 86A F808 97 90 A STA BAS E PG STORE FOR QU I C K RE F E RENCE
0 0 1 87A F aOA 33 84 A LEAU ,X RETURN TABLE TO CALLER
0 0 1 88A F 80C 3l 8C 3 5 LEAY < I N I TVT , PC R LOAD F ROM ADDR
0 0 1 89A F80F EF 81 A STU , X++ I N I T VEc'rOR TABLE ADDRE S S
0 0 l 90A Fall C6 16 A LOB # NU MVTR- 5 NUMB E R RE LOCATABLE VECTORS
0 0 1 9 1A F813 34 04 A PSHS B STO RE INDEX ON STACK
0 0 1 9 2A F815 IF 20 A BLD2 TF R Y,D PRE PARE ADDRES S RE SOLVE
0 0 1 9 3A F817 E3 Al A ADDD , Y+ + TO ABSOLUTE ADDRE S S
0 0 1 94A F819 ED 81 � STD , X++ I NTO VECTOR TABLE
0 0 1 9 5A F81B 6A E4 A DEC ,S COUNT DOWN
0 0 1 96A F81D 26 F6 F815 BNE BLD2 BRANCH I F MO RE TO I N S E RT
0 0 1 9 7A F81F C6 00 A LOB # I NTVE- I NTVS STAT I C VALUE I N I T LE NGTH
0 0 1 98A F821 A6 AO A BLD3 LOA , Y+ LOAD NEXT BYTE
0 0 1 9 9A F823 A7 80 A STA , X+ STORE I NTO POS I T ION
0 0200A F825 SA DE C B COUNT DOWN
0 0 2 0 1A F826 26 F9 F821 BNE BLD3 LOOP UNT I L DONE
0 0 2 0 2A F828 31 8 0 F 7 D4 LEAY ROM 2 0 F , PCR TEs'r POS S I B L E EXTENS I ON ROM
0 0 2 0 3A F 8 2C 8E 20FE A LDX # $ 20FE LOAD " B RA * - F LAG PATTE RN
0 0 20 4A F82F AC Al A CMPX , Y+ + ? EXTEN D E D ROM HE RE
0 0 20 5A F83l 26 02 F835 BNE BLDRTN BRAN CH NOT OU R ROM TO RETU RN
0 02 0 6A F833 AD A4 A JSR ,Y CALL EXTENDED ROM I N I T I AL I Z E
0 0 207A F835 35 84 A B LORTN P U LS PC , B RETURN TO I N I T I AL I Z E R
0 0209 *****************************************************
0 0210 * RE S ET ENTRY PO I NT
0 0211 * HARDWARE RE SET ENTE RS H E RE I F AS S I ST0 9 IS ENAB L E D
00212 * T O REC E I V E TH E MC 6 8 0 9 HARDWARE VECTORS . WE CALL
0 0213 * THE BLDVTR SUBROUT I N E TO I N I T I AL I Z E THE VECTOR
8-40
PAG E 00 5 AS S I ST0 9 . SA : 0 AS S I ST0 9 - M C 6 8 0 9 MON I TOR
00214 * TA B L E , S TAC K , AN D TH E N F I RE U P TH E MON I TOR V I A S W I

00215 * CALL .
00216 *******************************************************
0 0 2 1 7A F837 32 8 0 E7 1 6 RE S ET LEAS STACK , PCR S ET U P I N I T I AL STA C K
0 0 2 1 8A F83B 80 C3 F800 BSR B LDV T R B U I L D V E CTO R TABL E
0 0 2 1 9A F83D 4F RESET2 C L RA I S S U E STARTU P MESSAGE
0 0220A F83E IF 8B A TFR A , DP DE F AU L'r TO PAGE Z E RO
0 0 2 2 1A F840 3F SW I P ERFO RM MON ITOR F I RE U P
0 0 2 2 2A F841 08 A FC B MON I T R T O E N T E R CO MMAN D P RO C E S S I N G
00223A F842 20 F9 F8 3 D BRA RE S E T 2 RE ENTER MON ITOR I F ' CONT I NU E '
00225 ******************************************************
0 0226 * I N I TVT - I N I T I AL VECTOR TABLE
0 0 227 * TH I S TABLE IS RE LOCAT E D TO RAM AN D RE P RE S E NTS TH E
00228 * I lH T I AL STAT E OF THE VECTOR TABLE . ALL ADDRE S S E S
00229 * ARE CONVE R'£E D TO ABSOLU T E FORM . TH I S TABLE STARTS
0 0230 * W I TH TH E SECON D ENTRY , E N DS WITH STAT I C CON STANT
00231 * I N I T I A L I Z AT I ON DATA WH I C H CARRI E S BEYOND TH E TAB LE .
00232 ************************************************
0 0 2 3 3A F844 0158 A I N I TVT F OB CM DT B L - * DEF AU LT F I RST COMMAND TAB LE
00234A F846 0292 A F OB RS RVDR- * DEF AULT UNDEF I N E D HARDWARE VECTOR
0 0 2 3 5A F848 0290 A F DB S W I 3 R- * DE FAULT SW I 3
00236A F84A 028E A F OB S W I 2 R- * DEF AULT SW I 2
0 0237A F84C 0 27 0 A F DB F I RQ R- * DEFAU LT F I RQ
0 0238A F84E 028A A FDB I RQ R- * D E F AUL 'r I RQ ROUT I N E
00239A F850 0045 A FDB S W I R- * DE F AU LT SWI ROU T I N E
0 02 4 0A F852 022B A F DB NM I R- * DEFAULT NMI ROUT I N E
0 0 2 4 1A F854 FFE3 A F OB RE S ET- * RESTART VECTOR
0 0 2 4 2A F856 0290 A F OB C I ON- * DE F A U LT C I ON
0 0 2 4 3A F858 0284 A F DB C I D'£A- * DE F A U LT C I DTA
00244A F85A 0296 A F OB C IOF F- * DE F A U LT C IOFF
00245A F85C 0 28A A F OB COON- * DE FAU LT COON
0 0246A F85E 0293 A F OB CODTA- * DE F A U LT CODTA
0 0 2 4 7A F860 0290 A FOB COOFF- * DE F AU LT COOF F
0 0 2 4 8A F862 039A A F OB H S DTA- * DE F A U LT HS DTA
0 0249A F864 02B7 A F OB B S ON- * DE F AU LT BSON
0 0 2 5 0A F866 0 2 02 A F OB B S D TA- * DE F AULT B S DTA
0 0 2 5 1A F868 02BF A F OB BSO F F - * D E F AULT B SOF F
0 0 2 5 2A F86A E7 9 2 A FOB P A U S E R- * DEFAU LT PAUSE ROU T I N E
0 0 2 5 3A F86C 0470 A F OB EX P1 - * DE F AULT EXPRE S S ION ANALY Z E R
00254A F86E 012 D A F OB C M DT B 2 - * DEFAULT S E COND COMMAN D TABL E
00255 * CONSTANTS
002 56A F870 E0 0 8 A I NTVS F DB AC I A DE FAU L'£ AC IA
00257A F87 2 00 A FCB DFTCH P , DFTNLP D E F A U LT NU LL PADDS
0 0 2 5 8 1\ F874 0000 A FOB 0 DE FAULT ECHO
0 0259A F876 EO O O A FOB PTM DEFAU LT PTM
0 0 2 6 0A F878 0000 A F OB 0 I N I T I AL STACK TRAC E LEVEL
0 0 2 6 1A F87A 00 A FCB 0 I N I T IAL BREAK PO I NT COUNT
0 0 2 6 2A F87B 00 A FCB 0 SWI BREAK PO I NT L E V E L
0 0 2 6 3A F87C 39 A FCB $39 DE FAU LT PAU S E ROUT I NE ( RTS )
00264 F8 7D A I N TV E EQU *
00265 *B
00267 ***********************************************
B-41
PAGE 006 AS S I S'r0 9 . SA : 0 ASS I ST 0 9 - MC 6 8 0 9 MON I 'fOR
00268 * AS S I ST0 9 SW I HANDLER

0 0269 * TH E SWI HAN DLER PROV I DE S AL L I NTE RFAC I NG N E C E S SARY
0 0270 * FOR A USE R PROG RAM . A FU NCT ION BYTE IS AS S U M E D TO
00271 * FOLLOW TH E SWI I N STRUCT ION . IT IS BOUND CHECK ED
00272 * AN D TH E P RO P E R ROUT I N E I S G I VEN CONTROL . TH I S
00273 * I N VOCAT I O N MAY ALSO BE A BREAK PO I NT I NTE RRU PT .
0 0274 * I F SO , TH E BREAK PO I NT HAN DLER I S ENTERE D .
0 0275 * I NPUT : MAC H I NE STA'rE DEF I N E D FOR SWI
0 0276 * OUTPUT : VAR I E S ACCORD I NG TO FUNCT ION CALLE D . PC ON
00277 * CALLERS STACK I NCREMENTED BY ON E I F VAL I D CALL .
0 02 7 8 * VOLAT I LE REG I ST E RS : SE E F UNCT IONS CALLE D
0 0279 * S TATE : RUNS D I SAB LED UNLESS FUNCT ION CLEARS I F LAG .
00280 ************************************************
0 0282 * SWI F U N CT I ON VECTOR TABLE

0 0 2 8 3A F87D 0194 A SW I VTB F DB Z I NCH-SW IVTB I NCHNP
0 0 2 8 4A F87F OlBl A F DB ZOTC H 1 -SWIVTB OUTCH
0 0 2 8 5A F88 1 OlCB A F DB Z P D'fAl - SW I VTB PDA'fAl
0 0 286A F88 3 01C3 A F OB Z P DATA-SWIVTB PDATA
0 0 2 87A F88S 0175 A F DB Z OT 2 H S- SWIVTB OUT2 H S
0 0 2 8 8A F887 017 3 A F DB Z OT 4 H S -SWIVTB OUT4 HS
0 0 2 8 9A F889 OlCO A F DB Z PCRLF-SWIVT B PCRLF
0 0 2 9 0A F88B 0179 A FDB Z S PAC E - SWIVTB S PACE
0 0 2 9 1A F88D 0055 A F DB ZMON T R-SWIVTB MON ITR
0 0 2 9 2A F88F 017D A F DB ZVSWTH-SWIVTB VCTRSW
0 0 2 9 3A F891 0256 A F DB Z BK PNT- SWI VTB BREAK PO I NT
0 0 2 9 4A F89 3 O l Dl A F OB Z PAUSE-SWIVTB TASK PAUSE
0 0 2 9 6A F89S 6A 8 D E6 F 7 SW I R DEC SWI CNT , PCR U P " SWI " LEVEL FOR TRACE
0 0 2 97A F899 17 0 2 2 5 FACl LBSR LDDP SETUP PAGE AND VER I FY STAC K
0 029B * C H E C K FOR BREAK PO I N'f TRAP
0 0 2 99A F89C EE 6A A LDU 10 , S LOAD PROGRAM COUNTER
0 0300A F89E 33 SF A LEAU -l , U BACK TO SWI ADDRESS
0 0 3 0 1A F BAO O D FB A TST SWI B F L ? TH I S · SW I " BREAK PO I NT
0 0 3 0 2A F 8 A2 2 6 11 FBBS BNE SW I DNE BRANCH IF SO TO LET TH ROUGH
0 0 3 0 3A F 8 A4 1 7 069B FF42 LBSR C B K LDR OBTA I N BREAK PO I NT PO I N T E RS
0 0 3 0 4A F BA7 5 0 NEGB OBTA I N POS I T I VE CO UNT
0 0 3 0 SA F B A B SA SWI LP DEC B COU NT DOWN
0 0 3 0 6A F 8 A9 2B OA F8BS BM I SW I DN E BRANCH WHEN DONE
00307A F B AB l l A 3 Al A CMPU , Y+ + ? WAS TH I S A BREAK PO I NT
0 0 3 0 BA F BAE 2 6 F8 F B AB BNE SW I LP BRANCH I F NOT
0 0 3 0 9A F B BO E F 6A A STU 10 , 5 SET PROGRAM COU NTER BACK
00310A F 8 B2 1 6 0 2 1 E FAD3 LBRA Z B K PNT GO DO BREAK PO I NT
0 0 3 l lA FBBS O F FB A SW I DN E C L R SWI B F L C LE AR I N CAS E SET
0 0 3 1 2A F 8 B7 37 06 A PU LU 0 OBTA I N F UNCT ION BYTE , U P PC
0 0 3 1 3A FBB9 Cl OB A CMP B # NUMFUN ? TOO H I GH
0 0 3 1 4A F B BB 1 0 2 2 0 2 0 F FAC E LBH I ERROR YES , DO BREAK PO I NT
0 0 3 1 SA F B BF E F 6A A STU 10 , 5 BUMP PROGRAM COUNTER PAST SWI
0 0 3 16A FBCl SB AS L B F UNCTION C O D E T I M ES TWO
0 0 3 1 7A F8C2 33 BC B8 LEAU SWI VTB , PCR OBTAIN VECTOR BRANCH ADDRE S S
0 0 3 l 8A F 8 C S EC CS A LDO B,U LOA D OF F S ET
0 0 3 1 9A F 8 C7 6E CB A JMP D,U JUMP TO ROUT I N E
0 0321 **********************************************
00322 * REG I ST E RS TO FUNCT ION ROUT I NES :
00323 * DP- ) WORK AREA PAG E
0 0 3 24 * D , Y , U = U N RE L I ABLE X=AS CALLED FROM US E R
8-42
PAGE 007 AS S I s 'r0 9 . S � : 0 �S S I s' r 0 9 - MC 6 8 0 9 MON I 'rOR
00325 * S=hS F RO M SWI I N'r r; R RU P'r

0 0326 ************************************ *********
00328 **************************************************
0 0329 * [ S ri I P U N C T I U N 8 )
00330 * M O N I 'rU i{ E N 'r RY
0 0331 * F I R E U P 'ru E AS S I ST0 9 MON I 'rU R .
0 0332 * THE S T A C K WITH I'rs VA L ll E S P O R TI I l� l > I jU� CT PAm:
0 0333 * REG I S T E l{ AN D CO N D I 'r I O N CO D E F L AG S A R E U l:> t:: l) AS I ::i .
00334 * 1 ) I N I T I A L I Z 8 CO N l:> U L E I /O
00335 * 2 ) O P T I U N A L L Y P R I N T S I G NON
00336 * 3 ) I N I T I A L I Z E PTM P O R S I NG L � ST � P P I N G
00337 * 4 ) E N T E R COMMAND P ROC E � S O R
00338 * I N P U T : A= O I N l 'r CON S O L E A N D P IU N 'r STAH'ru p �I E S S A G E
0 0339 * A # O OM I 'r CO N SO L E m I 'l' AN D STA RTU P �If'; S S AG E
0 0 340 *** ************ ******************************** **
0 0 3 4 2A F 8 C 9 41 A S I G NO N FCC /ASS I S'l'0 9/S I G NUN EY \:: - C A'rC H E R

0 0 3 4 3A F8D1 04 A FCB Eo'r
0 0 3 4 5A F8D2 1 0 DF 97 A ZMONTR STS RSTACK SAVE FOR BAO s'rACK RECOVERY

0 0 3 4 6A F8D5 60 61 A TST 1,S ? I N IT CONSOLE AN D S E N D MSG
0 0 3 47A F 8 D7 26 00 F8E6 BNE Z MONT2 BRANCH IF NOT
00348A F 8 D9 AD 9 0 E6 F 9 JS R [ V ECT A B+ . C I O N , PCR] READY CO N SO L E I N P UT
0 0349A F8DD AD 90 E6FB JSR [ VECTAB+ . COON , PC R ] READY CO NSOL E OUTPUT
0 0350A F8E1 30 8C E5 L F. AX S I GNON , PCR READY S IGNON EYE- CATCH E R
0 0 3 5 1A F8E4 3F SWI PERFORM
0 0 3 5 2A F8E5 03 A FCB PDATA P RI NT S T R I NG
0 0 3 5 3A F8E6 9E F6 A ZMONT2 L O X VECTAB+ . PTM LOAD PTM ADDRE SS
0 0 3 54A F8E8 27 00 F8F7 BEQ CMD BRANCH I F NOT TO U S E A PTM
0 0 3 5 5A F 8 EA 6F 02 A C LR PTMTMI- PTM , X SET LATCH TO CLEAR RE S ET
003 56A F8EC 6F 03 A CLR PTMTM 1 + 1-PTM , X AN D SET GATE H IG H
00357A F 8EE CC 0 1A 6 A LDO # $ 0 1A6 S E T U P T I M ER 1 MODE
0 0 3 58A F8F1 A7 01 A STA PTMC 2 -PTM , X S ETUP FOR CONTROL REG I ST E Rl
00359A F8F3 E7 84 A STB PTMC 1 3 - PTM , X SET OUTPUT ENABLE D/
0 0360 * S I NGLE SH O T/ DUAL 8 B I T/ I NTERNAL MODE/OP E RATE
0 0 3 6 1A F8F5 6F 01 A C LR PTMC 2 -PTM , X SET CR2 RACK TO RE S E T FORM
0 0362 * FALL I NTO COMMAN D PROC E S S O R
00364 *** * * * * * * * * * * * * * ************* ******************* ***

0 03 6 5 * COMMAN D HAN DLER
00366 * BREAK PO I NTS ARE REMOVED AT TH I S T I ME .
00367 * P ROMPT FOR A COM MAN D , AN D STORE ALL CHARA C T E RS
0 0368 * U N T I L A S E PARATOR ON TH E STACK .
0 0369 * S EARCH FOR F I RST MATCH I NG COMMAN D SUBSET ,
0 0370 * CALL IT OR G IV E 1 1 1 RES PON SE .
00371 * DU RING COMMAN D SEARC H :
00372 * B=O F F S ET TO NEXT ENTRY ON X
00373 * U =SAV E D S
00374 * U- l = E NTRY S I Z E + 2
00375 * U- 2 =VAL I D NUMBER FLAG ( > = 0 VAL I O ) /COMPARE CNT
00376 * U- 3 =CARRIAG E RE 'r U RN F LAG ( O =C R HAS B E E N OON E )
0 0377 * U-4=START OF COMMAN D s'rO RE
0 0378 * S+O = E N D OF COMMAN D STORE
8-43
PAG E 008 ASS I S'ro 9 . S A : 0 AS S I ST 0 9 - M C 6 13 0 9 1>1 0 N I 'l'O R
00379 ***********************************************
0 0 3 8 0A F8F7 3F C 1>1 D S I'l I TU NEW L I N E
0 0 3 8 1A F 8 F 8 06 A FeB PCRLF F UN C T I O N
0 0 38 2 * D I SARM TiU': B H C A K PO I 1'�'l' S
0 0 383A F8F9 17 U646 F F 4 2 C M D tJ t:: P L B S R C B K I. D R OBTA I N B R E A K PO Hl 'r PO I NT E RS
0 0 3 8 4A F 8 FC 2A OC F90A BP L C !'t DNOL B RAN CH I F' NO'I' ARM E D OR N O N E
0 0385A F 8 FE 50 NEGB MAK E POS I 'r I V t::
0 0 3 8 6A F 8 F £o' D7 FA A ST� 13K P'rCT F LAG AS D I S A RM E D
0 0 3 8 7A F901 5 11. CM D D D L D E C B ? F ! N I S H E: D
0 0 3 88A F902 2B 06 F 9 0 /\ 8M I C�DNOLH� SO BRAN C H
00389A F904 A6 30 A I.J)A LOA D O P CODE S T O RE D
-NUMBK P * 2 , Y
0 0 3 9 0 A F 9 0 6 A7 B1 1\ [ , Y+ + )
STA STO RE BACK OV E R II S W I
It
0 0 3 9 1A 1" 9 0 8 2 0 F7 F901 C M D DD L
B RA LOOP UNT I L DON E
0 0 3 9 2A 1" 9 0 A AE 6A A CMD N O L LOX 10 , S LOAD U S E RS PROG RAM COUNT E R
0 0 3 9 3A F 9 0 C 9 F 93 A STX PCNT E R SAVE FOR EXPRE S S ION ANALY Z E R
0 0 3 9 4A F 9 0 E 8 6 3E A LOA # P ROM P T LOAD PROMPT CHARACTER
0 0 3 9 5A F 9 1 0 3 F SWI SEND TO OUTPUT HANDLER
0 0 3 9 6A F 9 1 1 01 A FCB DUTCH F UNCT ION
0 0 3 97A F912 3 3 E4 A LEAU ,S REMEMBER STACK RESTORE ADDRES S
0 0 3 9 8 A F 9 1 4 OF 95 A STU PSTACK REMEMBER STACK FOR ERROR USE
0 0 3 9 9A F 9 1 6 4 F CLRA PRE PARE Z E RO
0 0 4 0 0A F 9 1 7 S F CLRB PRE PARE Z ERO
0 0 4 0 1A F 9 1 8 DO 9B A STD NUM B E R C LEAR NUMBE R BU I LD AREA
0 0 4 0 2A F 9 1 A DO 8F A STD M I S F LG CLEAR M I S CE L . AND SW I CNT F LAGS
0 0 4 0 3 A F 9 1C DO 91 A STD TRAC E C CLEAR TRACE COUNT
0 0 4 0 4A F 9 1 E C6 02 A LO AS #2 SET 0 TO TWO
0 0 4 0 5A F 9 20 34 07 A PSIi S D , CC P LACE DEFAULTS ONTO STACK
00406 * C H E C K FOR " QU I C K " COMM A N DS .
0 0407A F922 17 0 4 5 4 F D7 9 LBS R READ OBTA I N F I RS T CHARACTER
0 04 0 8 A F925 30 80 0581 LEAX C DOT+ 2 , PCR PRE S ET FOR S I NGLE TRACE
0 04 0 9A F929 81 2E A CMPA iI ? QU I C K TRACE
•
0 04 1 0 A F 9 2B 27 5A F987 BEQ CMDXQT BRANCH EQUAL FOR TRACE ONE

0 0 4 1 1A F 9 2 D 30 80 04E9 LEAX CMPADP+ 2 , PCR READY MEMORY ENTRY POI NT
0 0 4 1 2A F 9 3 1 8 1 2F A CMPA i'l ? OPEN LAST USED MEMORY
0 0 4 1 3 A F 9 3 3 27 52 F987 BEQ CM D XQT BRANCH TO DO IT I F SO
0 04 1 4 * P ROCE S S NEXT CHARACT ER
0 04 1 5A F 9 3 5 8 1 20 A CMD2 CMPA t' ? B LANK OR DEL I M ITER
0 0 4 1 6A F 9 3 7 2 3 14 F94D BLS CMDGOT BRANCH YES , WE HAVE IT
0 0 4 1 7A F 9 3 9 34 02 A PSHS A BU I LD ONTO STACK
0 0 4 1 8A F93B 6C SF A INC -l , U COUNT TH I S CHARACT E R
0 0 4 1 9A F 9 3 D 8 1 2F A CMPA til ? MEMORY COMMAN D
0 04 20A F93F 27 4F F990 BEQ CMDMEM BRANCH I F SO
0 04 21A F941 17 0 4 0 B F D4 F LBS R B L D HXC TREAT AS H E X VALU E
0 0 4 2 2 A F 9 4 4 27 02 F948 BEQ CMD 3 BRANCH I F ST I LL VAL I D NUMBER
0 04 23A F946 6A 5E A DEC -2 , U F LAG AS I NVA L I D NUM B E R
0 04 2 4A F 9 4 8 17 0 4 2 E F D7 9 C M D 3 LBS R READ OBTA I N NEXT CH ARACTER
0 0 4 25A F94B 20 E8 F935 BRA CMD 2 TEST NEXT CHARACTE R
0 04 2 6 * G O T COMMAN D , NOW S EARC H TABLES
0 0427A F94D 80 00 A CM DGOT SUBA I CR SET Z E RO I F CARRI AG E RETU RN
0 0 4 2 8A F 9 4 F A7 50 A STA -3 , u SE'fUP F LAG
0 04 2 9A F 95 1 9 E C4 A LOX VECTAB+ . CMDL1 START W I TH F I RST CMD L I ST
0 0 430A F953 E6 80 A CMDSCH LOB ,X+ LOAD ENTRY LENGTH
0 0 4 3 1A F 9 5 5 211. 10 F967 BP L CM DS M E BRANCH IF NOT L I ST END
0 0 4 3 2A F 9 5 7 9 E EE A LOX VECTAB+ . C MDL2 NOW TO SECOND CMD L I ST
0 04 3 3A F 9 5 9 5 C I NC B ? TO CONT I NU E TO DE FAULT L I ST
0 0 4 3 4 A F 9 5A 27 F7 F9 5 3 BEQ CMDseH BRANCH I F SO
0 0 4 3 5 A F 9 5 C l O DE 9 5 A CM DB A D LOS PSTACK RESTORE STACK
0 04 3 6 A F95F 30 80 015A L E AX E RRMSG , PCR PO I NT TO E RROR STRING
8·44
P AG E 009 AS S I ST0 9 . SA : 0 ASS I S T 0 9 - M C 6 8 0 9 MON I TOR
0 0437A F963 3F SWI S E N D OUT

00438A F964 02 A FCB PDATAI TO CONSOLE
0 0 4 3 9A F965 20 90 F8F7 BRA CMD AN D T R Y AGA I N
0 0440 * S E ARCH NEXT ENTRY
0 0 4 4 1A F967 5A CM DSME DECR TAK E ACCOU NT OF LE NGTH BYTE
0 04 4 2A F968 El 5F A CMPB -l , U ? E N T E R E D LON G E R THAN ENTRY
0 04 4 3A F96A 24 03 F96F BHS C M DS I Z BRANC H I F NOT TOO LO NG
0 0 4 4 4A F96C 3 .11. CMDFLS ABX SK I P 'ro NEXT ENTRY
0 0 4 4 5A F96D 20 E4 F953 B RA CMDSCH AN D 'fRY NEXT
0 0 4 4 6A F96F 31 5D A CMDS I Z LEAY -3 , U PRE PARE TO COMPARE
0 0447A F971 A6 5F A LOA -l , U LOA D S I Z E + 2
0 0448A F973 80 02 A SUBA #2 TO ACTUAL S I Z E E N T E R E D
0 04 4 9A F97 5 A7 5E A STA -2 , U SAVE S I Z E FOR COUNTDOWN
0 0450A F977 5A CMDCMP DEC B DOWN ONE BYTE
0 0 451A F978 A6 80 A LOA , X+ NEXT COMMAN D CH ARA C T E R
0 0 4 5 2A F97A Al A2 A CMPA , -Y ? S AME AS T H AT E N T E R E D
0 04 5 3A F97C 26 EE F96C SNE CMDF LS B RANCH TO F LU S H I F NOT
0 04 5 4A F97E 6A 5E A DEC -2 , U COU NT DOWN LENGTH OF ENTRY
0 0 4 5 5A F980 26 F5 F977 BNE CMDCMP 8RAN CH IF MORE TO T E ST
0 0 4 5 6A F98 2 3A ABX TO NEXT EN'f RY
0 0457A F983 EC 1E A LDD -2 , X LOAD O F F S E T
0 0 4 5 8A F985 30 8B A LEAX D,X COMPUTE ROUT I N E A DD RES S + 2
0 0 4 5 9A F987 60 50 A CMDXQT TST -3 , U SET CC FOR CARR I AG E RETURN TEST
0 0 4 6 0A F989 32 C4 A LEAS ,U DELETE STACK WORK AREA
0 0 4 6 1A F98B AD IE A JSR -2 , X C AL L C O MMAN D
0 0 4 6 2A F98D 16 FF7A F90A LBRA C M DN O L GO GET NEXT COMMAND
0 0 4 6 3A F990 60 5E A CMDMEM TST -2 , U ? VAL I D HEX NUMB E R ENTERED
0 0 4 6 4A F99 2 2B C8 F9 5C BM I C M D BA D BRANCH ERRO R I F NOT
0 0 4 6 5A F994 30 8 8 AE A LEAX <CMEMN-CMPADP , X TO DI F F E RENT ENTRY
0 0 4 6 6A F997 DC 9B A LCD N UM B E R LOAn NUMBE R ENTERE D
0 0467A F999 20 EC F987 B RA CM DXQT AN D ENT ER MEMORY COMMAN D
0 0469 * * COMMAN DS ARE E NT E RE D A S A SUBROUT I N E W I 'fH :

0 0470 ** DP R- > ASS I ST0 9 DI RECT PAGE �ORK ARE A
00471 ** Z = l CARRI AGE RE'fURN ENTE RED
0 047 2 ** Z = O NON CARR I AG E RETU RN DE L I M ITER
00473 ** S-NORMAL R ET U RN ADDRE S S
0 0474 * * THE LAB E L n CMDBA D n MAY BE ENTERED TO I S S U E AN
00475 * * A N ERROR F LAG ( * ) .
00477 **** **********************************************

0 0478 * ASS I ST0 9 COMMAN D 'fABLES
0 0479 * TH E S E ARE THE D E F .e.1J [,1' CO M MA N D TABLE S . EXTERNAL
00480 * 'fAB L E S OF THE SAME FORMAT MAY EXTE N D/ RE PLACE
00481 * TH E S E BY US I NG THE VECTOR SWAP FUNCT I ON .
0 04 8 2 *
00483 * E NTRY FORMAT :
0 04 8 4 * +O • •TOTAL S I Z E OF E NT RY ( I NC L U D I NG TH I S BYT E )
•
00485 * +l • •COMM A N D STR I NG

•
00486 * +N • •TWO BYTE OF F SE'r TO COM M A N D ( E N T RYA D DR- * )

•
00487 *
0 0488 * THE 'fAB LES TE RM I NATE WITH A ON E B YT E - l OR - 2 .
0 0489 * 'l'H E - 1 CONT I N U E S TH E COMMA N D SEARC H W I T H TH E
00490 * SECO N D CO MM A N D TAB LE .
0 04 9 1 * THE -2 TERM I NA'r E S COMMA N D S EARCH E::> .
00492 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *� * * * * * * * * * * * * *
B-4 5
PAG E 010 AS s I ST0 9 . sA : 0 AS S I ST 0 9 - MC6 8 0 9 MON I'fOR
0 0494 * T H I S I S THE DE FAU LT LIST (O'OR THE SECOND COMMAN D

0 04 9 5 * L I ST ENTHY .
0 0 4 9 6A F998 FE A CM DT82 FCB -2 STOP COMMAN D SEARCHES
0 0498 I S 'fH E DE FAULT L I ST FOR THE F I RST COMMAN D

* TH I S
00499 * ENTRY .
L I ST
00500 F99C A CMDTBL EQU * MON I'fOR COMMAND TABLE
0 0 5 0 1A F99C 04 A FCB 4
0 0 5 0 2A F99D 42 A FCC I BI ' BREAK PO I NT ' COMMAN D
0 0 5 0 3A F99E 0540 A F OB CSK PT- *
0 0 5 0 4A F 9AO 04 A FCB 4
0 0 5 0 5A F 9A1 43 A FCC IC I ' CALL ' COMMAN D
00506A F 9 A2 0417 A FOB CC A L L - *
0 0 5 0 7A F 9 A4 04 A FCB 4
0 0 5 0 8A F 9 A5 44 A FCC 1 01 ' D I S P LAY ' COMMAN D
00509A F 9 A6 0490 A F OB C D I S P- *
0 0 5 10A F 9 A8 04 A FC B 4
O O S l lA F9A9 45 A FCC lE I ' E N C ODE ' C OMM AN D
O O S loil A F 9 AA OS9F A F OB C E NC DE- *
0 0 S 1 3A F 9 AC 04 A FCB 4
0 0 S 14A F 9 AD 47 A FC C IGI ' GO ' COMMAN D
0 0 S 1 5A F 9 AE 0 3 02 A F DB CGO- *
0 0 S 1 6A F 9 BO 04 A FCB 4
0 0 S 1 7 A F 9 Bl 4C A FC C ILl ' LOAD ' COMMAND
0 0 S 1 8A F 9 B2 0 4 00 A F OB C LOAD- *
0 0 S 1 9A F 9 B4 04 A FCB 4
0 0520A F 9 &S 40 A FCC IMI ' MEMORY ' COMMAN D
0 0 5 2 1A F 9 B6 040 0 A F OB CMEM- *
0 0 5 2 2A F9B8 04 A FCB 4
0 0 5 2 3A F9B9 4E A FCC INI ' NU LLS ' COMMAN D
0 0 5 2 4A F 9 BA 04FD A F OB CNU LLs- *
0 0525A F 9 BC 04 A FC B 4
0 0526A F9BD 4F A FCC 101 ' OF F S ET ' COMMAN D
0 0527A F 9 BE 050A A F OB COF F S- *
0 0 5 2 8A F9CO 04 A FCB 4
0 0 5 29A F 9C1 50 A FCC IPI ' PUNCH ' COMMAND
0 0 5 3 0A F9C2 0 4 AF A F OB CPUNCH - *
0 0 5 3 1A F9C4 04 A FCB 4
0 0 5 3 2A F9C5 52 A FCC IRI ' REG I ST E RS ' COMMAN D
0 0 5 3 3A F9C6 0284 A FOB C REG- *
0 05 3 4A F9C8 04 A FCB 4
00535A F9C9 53 A FCC lSI ' STLEVEL ' COMMAND
0 0 5 36A F 9 CA 04F2 A FOB CSTLEV-*
0 0 5 37A F 9 CC 04 A FCB 4
0 0 538A F9CD 54 A FCC IT I ' TRACE ' COMMAND
0 0539A F9CE 0 4 06 A F OB CTRAC E - *
00540A F 9DO 04 A FCB 4
0 0 5 4 1A F9Dl 56 A FCC IVI ' VERI FY ' COMMAND
0 0 5 4 2A F9D2 04CF A FOB CVE R- *
0 0 5 4 3A F 9 D4 04 A FCB 4
0 0 5 4 4A F 9 D5 57 A FC C IWI ' W I NDOW ' COMMAND
0 0 5 4 5A F 9 D6 0468 A FOB CW I N DO- *
0 0 5 4 6A F 9 D8 FF A FCB -1 EN D , CONT I NU E WITH THE S ECOND
00548 *************************************************
00549 * [ SW I F U NCT I ONS 4 AN D 5 )
8-46
P AG E 011 ASS I ST 0 9 . SA : 0 ASS I ST0 9 - MC 6 8 0 9 MON I TOR
0 0550 * 4 - OUT 2HS - De CODE BYTE TO HEX AN D ADD S PACE

0 0551 * 5 - OUT 4 H S - DE CODE riORD TO HEX ru� D ADD S P AC E
0 0552 * I NPUT : X-> BYTE O R WORD TO DECODE
0 0553 * OUTPUT : CHARACT E RS S E NT TO OUTPUT HAN DLER
0 0554 * X - > NEXT BYTE OR WORD
00555 **************************************************
0 0557A F9D9 A6 80 A ZOUT 2 H LOA ,X+ LOAD NEXT BYTE

0 0 5 5 8A F 9 DB 34 06 A PSHS o SAVE - DO NOT REREAD
0 0 5 59A F9DD C6 10 A LOB #16 SH I FT BY 4 B I TS
0 0 5 6 0A F 9 DF 3D MUL WITH MULT I P LY
0 0 5 6 1A F9EO 80 04 F9E6 BS R ZOUTIiX S E N D OUT AS HEX
0 0 5 6 2A F9E2 35 06 A PULS o RE STORE BYT E S
Ot0 5 6 3A F9E4 84 OF A ANDA #$OF I SOLATE R I G H T HEX
0 0 5 6 4A F9E6 8B 90 A ZOUTHX ADDA #$90 PRE PARE A-F ADJ UST
0 0 5 6 5A F9E8 19 OM ADJ UST
0 0 5 6 6A F9E9 89 40 -A ADCA # $40 PRE PARE CHARACTE R B I TS
0 0567A F9EB 19 OM ADJ UST
0 0568A F9EC 6E 90 E5EE SEND JMP [ VECTAB+ . CODTA , PC R ) S E N D T O OUT HAN D LE R -
0 0 5 7 0A F 9 F O 8 0 E7 F 9 D9 Z OT4 H S BSR ZOUT 2 H CONVERT F I RS T BYTE

0 0 5 7 1A F 9 F 2 8 0 E5 F 9 D9 ZOT2HS B S H. ZOUT 2 H CONVE RT BYTE T O HEX
0 0 5 7 2A F 9 F 4 AF 64 A STX 4,S UPDATE USERS X REG I �TER
0 0573 * F ALL I NTO SPACE ROUT I N E
00575 *************************************************
0 0576 * [ SW I F U NC T I ON 7 )
0 0577 * S PAC E - S E N D BLANK TO OUTPUT HANDLER
00578 * I NPUT : NONE
0 0 57 9 * OUT P UT : BLANK SE N D '::0 CONSOLt� lIAN DLER
00580 ***************** ********************************
0 0 5 8 1A F 9 F 6 8 6 20 A Z S PACE LOA #' LOAD BLANK
0 0 5 8 2A F 9 F 8 2 0 3D FA3 7 BRA ZOTC H 2 S E N D AN D RETU RN
0 0584 ***********************************************
0 0585 * [ Sri I FUNCT ION 9 )
00586 * SWAP VECTOR TABLE ENTRY
0 0587 * I NPUT : A-VECTOR TABLE CODE ( OF F S ET )
00588 * X=O OR REP LACEMENT VALUE
0 0589 * OUTPUT : X = P REVIOUS VALUE
00590 ***********************************************
0 0 5 9 1A F 9 FA A6 61 A ZVS WTH LOA 1,S LOAD REQUESTERS A
0 0 5 9 2A F 9 FC 81 34 A CMPA # H IVTR ? S U B-CODE TOO H IGH
0 0 5 9 3A F9FE 22 39 FA3 9 BH I ZOTCH3 IGNORE CALL I F SO
0 0 5 9 4A FAO O 10 9 E C2 A LDY VECTAB+ . AVTBL LOAD VECTOR TABLE ADDRE S S
0 0 5 9 5A FA0 3 EE A6 A LOU A,Y U=OLD ENTRY
0 05 9 6A FA0 5 EF 64 A STU 4 ,S RETU RN OLD VALUE TO CALLERS X
0 05 9 7 A FA0 7 AF 7E A STX -2 , S ? X= O
0 05 9 8A FA0 9 27 2E FA3 9 BEQ ZOTCH3 YES , DO NOT CHANGE ENTRY
0 0599A FAO B AF A6 A STX A, Y RE PLAC E ENTRY
0 0 6 0 0A FAO D 20 2A FA3 9 BRA ZOTCH 3 RETURN FROM SW I
00601 *0
8-47
PAG E 012 AS S I ST 0 9 . SA : 0 ASS I ST 0 9 - M C 6 8 0 9 MON I TOR
0 06 0 3 ************************************************
00604 * [ SW I FUNCT ION 0 ]
00605 * INCHNP - OBTA I N I N P UT CHAR I N A ( NO PARI TY )
00606 * NULLS AN D RU BOUTS ARE IGNORE D .
0 0607 * AUTOMAT I C L I N E F E E D I S S E N T U PON HEC I EV I NG A
00608 * CARRI AG E RE'l'URN .
0 06 0 9 * UNLESS �E ARE LOAD I NG F ROM TAPE .
0 06 1 0 ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
0 0 6 1 1A FAO F 80 50 FA6 E Z I NCHP BSR XQPAUS HE LEAS E PROC E S S O R
0 0 6 1 2A FAl l 80 SF FAn Z I NCH aSR XQC I DT CALL I N PUT DATA APP E N DAGE
0 06 1 3A FA1 3 24 FA FAO F BCC Z I NCHP LOOP I F NONE AVA I LABLE
0 0 6 1 4A FA1 5 40 TSTA ? T E ST FOR NU L L
0 0 6 1 5A FA1 6 27 F9 FAl l BEQ Z I NCH IGNORE NULL
0 0 6 1 6A FA1 8 81 7F A CMPA # $7F ? RU BOUT
0 0 6 1 7A FA1A 27 F5 FAl l BEQ Z I NCH BRANCH YES TO I G NORE
0 0 6 1 8A FA1 C A7 61 A STA 1,S STORE I NTO CALL E RS A
0 0 6 1 9A FA1 E 00 8F A TST M I S F LG ? LOAD IN PROG RE S S
0 0620A FA2 0 26 17 FA3 9 BNE ZOTCH3 BRANCH I F SO TO NOT ECHO
0 0 6 2 1A FA2 2 81 00 A CMPA #CR ? CARR I AG E RETURN
0 0 6 2 2A FA2 4 26 04 FA2A BNE Z I N2 NO , TES'l' ECHO BYTE
0 0 623A FA2 6 86 OA A LOA # LF LOAD L I NE F E E D
0 06 24A FA2 8 80 C2 F9EC BSR SEND ALWAYS ECHO L I N E F E E D
0 0 6 2 5A FA2A 00 F4 A Z IN 2 TST VEC'l'AB+ . E CHO ? ECHO DES I RE D
00626A FA2C 26 OB FA3 9 BNE Z OTC H 3 NO , RETURN
0 0 6 27 * F AL L TH ROUGH T O OUTCH
00629 ************************************************
00630 * [ S W I FUNCTION 1 ]
00631 * OUTCH - OUTPUT CHARACT ER F ROM A
00632 * I N PUT : NONE
00633 * OUTPUT : I F L I N E F E E D I S TH E OUTPUT CHARACTE R TH E N
0 06 3 4 * C = O NO CTL-X REC I EVED , C= l CTL- X REC I EVED
00635 *************** *********************************
00636A FA2E A6 61 A ZOTCH 1 LOA 1,S LOAD CHARACTE R TO S E N D
0 0 6 3 7A FA3 0 30 8C 09 LEAX < Z PCRLS , PC R DEFAU LT FOR L I NE F E E D
0 06 3 8 A FA3 3 81 OA A CMPA #LF ? L I NE FEED
0 0639A FA3 5 27 OF FA4 6 BEQ Z P DTLP B RANCH TO CHECK PAU S E IF SO
0 0 640A FA3 7 80 B3 F9EC ZOTCH 2 BS R SEND S E N D TO OUTPUT ROUT I N E
0 0 6 4 1A FA3 9 OC 90 A ZOTCH3 I N C SWICNT BUMP UP A SWI n T RACE NEST LEVEL
0 0 6 4 2A FA3B 3B RT I RETURN F ROM n SW I n F UNCT I O N
00644 **************************************************
00645 * [ SW I FUNCTION 6 ]
0 0646 * PCRLF - S E N D CR/LF TO CONSOLE HANDLER
00647 * INPUT : NONE
00648 * OUT PUT : C N. AN D LF S E NT TO HANDLER
00649 * C = O NO CTL- X , C= l CT L-X REC I EV E D
00650 **************************************************
0 0 6 5 2 A FA3C 04 A Z P C RLS F C B EOT NU L L STRING
0 0 6 5 4 A FA3 D 3 0 8C FC Z PCRLF LEAX Z PC RL S , PC R READY C R , L F ST R I NG

00655 * FALL I NTO CR/LF COD E
8-48
PAG E 013 ASS I �T0 9 . S A : 0 ASS I � T0 9 - M C 6 8 0 9 MON I T O R
0 0657 ** * * * * * * * *** *** * * * * * ** * * * * * ** * * * ** * ** * * * ** * * ******

0 0658 * [ S W I F U N C T I ON 3 J
0 06 59 *
PDATA - OUT P U 'f CR/I. F AND S T � I NG
00660 * I N P UT : X- > S T � I � G
00661 * OUT P U 'l' : C R/ LF AN D ST R I NG � E N 'l' 're O UT P U T CO NSOLE
0 0662 * liAlW L E H .
00663 * C - O NO CT L -X , C - l CT L - X Hi:: C n: V Ell
0 0664 * NOT E : LINe 1�' E t: D M U S T r'O L f.OW CA!{IU l\G F.: HE T U RN F O R
0 0665 * P RO p e l{ P U NCH l)ATA .
00666 *** * * * * * * * * ** * *** *** * * ******** * ** * * * *** * * * ********
0 0 6 6 7 A r�A 4 0 8 6 on A Z P DA'rA LDA #CR LOA D CAR R I AG E R E 'l' U RN
0 0 6 6 8 A FA4 2 8 0 A8 F9EC BS H SEND �END IT
0 0 6 6 9 A FA4 4 8 6 OA l\ I. nil # LF LO A n L I N E �' E i': J)
0 0670 * F A L r. L N'l'O P D AT A l
00672 ** ** * *** * ** * * * * * * * * ** * *** * * * * * * * ** * * * ** * * * ** * * * * *

00673 * [ S W I F U N CT I O N 2 J
00674 * PDATAl - OUTPUT �T R I NG T I L L EOT ( $ 0 4 )
00675 * TK I S ROUT I NE PAUSES IF AN I N PUT BYTE BECOM E S
00676 * AVA I LABLE DURI NG OUTPUT TRANSM I S S ION U N T I L A
0 0677 * SECOND IS REC I EVED .
00678 * I N PUT : X- ) ST R I NG
0 0679 * OUTPUT : S T R I N G S E NT 're OUTPUT CONSOLE DRI V E R
00680 * C - O NO CTL- X , C- l CTL- X RE C I EVED
00681 ******************* ***************** ******** * * * * *
0 0 6 8 2A FA 4 6 8 0 A4 F9EC Z P DTLP S S R SEND S E N D CHARACTE R T O DRI V E R
0 0 6 8 3 A FA 4 8 A6 80 A Z P DTAl LOA , X+ LOAD NEXT CHA RA C T E R
0 0 6 8 4 A FA4A 8 1 04 A C MP A # EOT ? EOT
0 0 6 8 5 A FA 4 C 2 6 F8 FA4 6 BNE Z P DTLP LOOP I F NOT
00686 * FALL I NTO PAU S E CHECK FUNCT ION
00688 ****************** ******** ******************

0 06 8 9 * [ SW I F UN C T I O N 1 2 J
00690 * PAUSE - RETU RN TO TAS K D I S PATCH I NG AN D CHECK
0 06 9 1 * FO R F RE E Z E CON D I T ION OR CTL-X BREAK
0 0692 * TH I � FUNCT I ON ENT E RS TH E TAS K PAUSE HANDLER SO
0 0693 * OPT I O NALLY OTH E R 6 8 0 9 PROCE S S E S MAY GA I N CONTROL .
00694 * U PON RETURN , CHECK FOR A ' F REE Z E ' CON D I T I ON
0 0695 * W I TH A RE S U LT I NG WA IT LOOP , DR CON D I T I ON CODE
0 06 9 6 * RETU RN IF A CONTROL-X IS ENTERED F ROM THE I NPUT
0 06 9 7 * HAN D L E R .
0 06 9 8 * OUTPUT : C= 1 IF CTL-X HAS ENTERE D , C= O OT H E RW I S E
00699 *****•••••••••••••••••••••*•••••••* .**•••*
0 0 7 0 0A FA4 E 80 lE FA6 E ZPAUSE BSR XQPAUS RE LEASE CONTROL AT EVERY L I N E
0 0 7 0 IA FA50 80 06 FAS 8 BSR CHKABT CKECK F O R FRE E Z E OR ABORT
0 0 7 0 2A FA 5 2 IF A9 A TF R CC , B PRE PARE TO REPLACE CC
0 07 0 3A FA54 E7 E4 A STB ,5 OVE RLAY OLD ONE O N ST ACK
007 04A FAS6 20 E1 FA3 9 B RA ZOTCH3 RETU RN F ROM " SW I "
0 07 0 6 • CHKABT - SCAN FOR INPUT PAU S E/ A B O RT DU RI NG OUTPUT

0 0707 * OUTPUT : C= O OK , C= 1 ABORT ( CTL-X I S S U E D )
0 07 0 8 • VOLAT I L E : U , X , D
0 0 7 0 9 A FA S a 8 0 18 FA7 2 CHKABT BSR XQC I DT ATT EMPT I N PUT
0 0 7 1 0 A FA 5A 2 4 05 FA6 1 BCC CHKRTN BRAN CH NO TO RETU RN
8-49
PAG E 014 AS S I ST 0 9 . SA : 0 AS S I ST0 9 - MC 6 8 0 9 MON ITOR
0 0 7 11A FASC 81 18 A CMPA # CAN ? C T L - X F O R ABORT

0 0 7 l 2A FA S E 26 02 FA6 2 BNE CHKWT BRANCH NO TO PAU S E
0 0 7 l 3A FA 6 0 53 C H K S EC COMB S E'f CARRY
0 0 7 l4A FA6 1 39 CHKRTN RTS RETURN TO CALLER WI TH CC SET
0 0 7 l SA FA6 2 80 OA FA6 E CH KWT BSR XQPAUS PAUS E FOR A MOMENT
0 0 7 l 6A FA6 4 80 OC FA7 2 BSR XQC I DT ? K EY FOR START
007 l7A FA6 6 24 FA FA6 2 BCC CH KWT LOOP UNT I L REC I EVEO
0 0 7 l 8A FA6 8 81 18 A CMPA # CAN ? ABORT S I GNALE D F ROM WA I T
0 0 7 l 9A FA6A 27 F4 FA6 0 BEQ CHK S E C BRANCH YES
0 0 7 20A FA6C 4F CLRA SET C = O FOR NO ABORT
0 07 21A FA6 D 39 RTS AN D RETURN
0 07 23 * SAVE ME MORY WITH JUMP S

0 0 7 2 4A FA6E 6E 90 E S 7 8 XQPAUS JMP [ VE CTAB+ . PAUS E , PC R ) TO PAU S E ROU T I N E
0 072SA FA7 2 AD 90 ES62 XQC I DT J S R [ V.ECTAB+ . C I DTA , PC R ) T O I NPUT ROUT I NE
0 07 26A FA7 6 84 7F A AN DA #$7F STR I P PAR ITY
"
0 0 7 27A FA78 39 RTS RETURN TO CALL E R
00729 ********************************************
00730 * NM I DE FAULT IN'fE RRUPT HANDLER
00731 * THE NMI HAN DLER I S US E D FOR TRAC I NG I N STRUCT IONS .
00732 * TRAC E PRI NTOUTS OCCUR ONLY AS LONG AS THE STACK
0 07 3 3 * THACE LEV E L I� NOT B R E AC H E D BY FALL I NG BE LOW IT .
00734 * TRAC I NG CONT I NU E S UNT I L TH E COUNT TU RNS Z E RO O R
0 07 3 5 * A CTL-X I S E NTERED F ROM THE I N PUT CONSOLE DEV I C E .
00736 *********************************************
0 0 7 3 8 A FA7 9 4F A MSHOWP F C B ' O , ' P , ' - , EOT OPCODE PREP
0 07 4 0A FA 7 D 80 42 FAC 1 NM I R BSR LOOP LOAD PAGE AND VERI F Y STACK

0 0 7 4 1A FA7 F 00 8F A TST M I S F LG ? T H RU A B R E AK PO I NT
0 0 7 4 2A FA 8 1 26 34 FAB7 BNE N M I CON B RANCH I F S O TO CONT I NUE
0 0 7 4 3A FA8 3 00 90 A TST SW I CNT ? I N H I B I T " SW I " DU R I NG TRAC E
0 0 7 4 4A FA 8 S 2B 29 FABO BM I NM I T RC BRANC H Y E S
0 074SA FA87 30 6C A LEAX 12 , S OBTA I N US E RS STACK PO I NT E R
0 0 7 4 6A FA8 9 9C F8 A CMPX SLEVEL ? T O TRAC E H E RE
00747A FA 8 B 25 23 FABO B LO N M I T RC BRAN CH I F 'roo LOW TO D I S PLAY
0 0 7 4 8A FA8D 30 8C £9 LEAX MSUOWP , PCR LOAD OP PRE P
0 0 7 4 9A FA9 0 3F SWI S E N D TO CON SO L E
007 50A FA9 1 02 A FCB P DAT AI FUNCTION
0 0 7 S 1A FA9 2 09 8E A ROL DE L I M SAV E CA R RY I H 'r
007 S2A FA 9 4 30 80 ESOI LEAX LASTOP , PC R PO I NT TO LAST OP
007 S3A �'A 9 8 3F SW I S E N D OUT AS H E X
0 07 S4A FA99 05 A FC B OUT 4 H S FUNCTION
0 0 7 S SA FA9A 80 17 FAB 3 BSR REG P RS FOLLOW ME MORY W I T H REG I ST E RS
0 07S6A FA9C 25 37 FADS BCS Z BKCMD BRAN C H I F " CANC E L "
00757A FA 9 E 06 8E A ROR DE L I M RE STORE CARRY B I T
0 0 7 S8A FAAO 25 33 FAD S BCS Z BKCMD BRANCH I F " CANCE L "
0 0 7 S9A FAA 2 9E 91 A LDX TRACEC LOAD TRAC E COUNT
00760A FAM 27 2F FADS BEQ ZBKCMD IF Z E RO TO COMMAN D HAN D L E R
0 0 7 6 1A FAA 6 30 IF A LEAX -1 , X M I N U S ON E
0 0 7 6 2A FAA 8 9F 91 A STX TRAC EC RE I-' RESH
0 07 6 3A FAAA 27 29 FADS BEQ ZBKCMD STOP TRAC E WH EN Z E RO
0 0 7 6 4A FAAC 80 AA FAS 8 BSR CH KABT ? A BORT THE TRACE
0 07 6 SA FAAE 25 25 FAD S BCS Z B KCMD BRANCH YES TO COMMAND HAN DLER
B·50
PAG E 015 AS S I ST0 9 . SA : 0 AS S I ST0 9 - M C 6 8 0 9 MON I TOR
0 0 7 6 6 A FAB O 1 6 0 3 F 7 F EAA NMI TRC LBRA CTRC E 3 NO , TRAC E ANOTH E R I N ST RUCT ION
0 0 7 6 8 A FAB 3 1 7 0 1 B 9 FC6F HEGPRS LBSR REG P RT PRI NT REG I S T E RS AS F ROM COMMAN D

0 0 7 6 9 A FAB 6 3 9 RTS RET U RN TO CAL L E R
00771 * J U ST E X E C UTE D 'fH RU A BRKPNT . NOW CONT I NU E NO RMALLY

0 0 7 7 2A FAB 7 O F 8F A NMI CON CLR M I S F LG C LEAR THHU F LAG
0 0 7 7 3 A FAB 9 1 7 0 2 E B F DA7 LBSR A RM B K 2 ARM BREAK PO I NTS
0 0 7 7 4 A FABC 3B RT I RT I AND CONT I NU E U S E RS P ROGRAM
00776 * LDDP - SETUP D I RECT PAGE REG I STE R , V E R I FY STACK .

0 0777 * AN I NVAI. I D STACK CAU S E S A RETURN TO T H E COMMAN D
0 0778 * HAN D LE R .
00779 * I NPUT : FU LLY STAC K E D REG I ST E RS FROM AN I NTE RRU PT
0 0780 * OUTPUT : DPR LOADED TO WORK PAGE
0 0 7 8 2A PAB D 3F A ERRM SG F C B ' ? , B E LL , $ 2 0 , EOT ERROR RE S PONSE
0 07 8 4A FAC I E6 8 D E 4 D8 LOOP LOB BAS E PG , PCR LOAD D I RECT PAGE H I GH BYTE

0 0 7 8 5A FAC 5 IF 9B A TFR B , DP S ETU P DI RECT PAGE REG I ST E R
0 07 8 6A FAC 7 Al 63 A CMPA 3,S ? I S STACK VAL I D
0 07 8 7A FAC 9 27 25 FAF O BEQ RTS YES , RETU RN
0 0788A FACB l O DE 97 A LDS RSTACK RESET TO I N I T I AL STACK PO I N T E R
0 0789A FACE 30 SC EC E RRORLEAX ERRMSG , PC R LOAD ERROR RE PORT
0 0 7 9 0A FADI 3F SWI S E N D OUT BEFORE REG I STERS
0 0 7 9 1A FAD2 03 A FCB PDATA ON NEXT L I N E
00792 * FALL I N T O BREAK PO I NT HAN DLER
00794 ********** ************* ************* *** *** * ***

0 07 9 5 * [ SW I FUNCT I ON 1 0 ]
00796 * BREAK PO I N T PROGRAM FUNCT ION
0 0797 * PRI NT REG I ST ERS AN D GO TO COMMAND HAN L E R
0 0798 ******************* ******************** ******t*
0 07 9 9 A FAD3 8D DE FAS 3 Z B K PNT BSR REG PRS PRI NT OUT REG I ST E RS
0 0 8 0 0 A FADS 1 6 F E 2 1 F8F9 Z SKCMD LBRA CMDN E P NOW ENTER COM M AND HAN D L E R
00802 **** **************** **************** *** **** *

0 08 0 3 * I RQ , RE S E RVED , SW I 2 AN D SWI 3 INTE RRU PT HANDLERS
00804 * THE DEF AULT HAN DL I NG I S TO CAUS E A B REAK PO I NT .
0 0805 ******* * * * * * * ** ** * * ** * * * * * * ****** ** ** * ** ** * *
0 0806 FADS A SWI 2 R EQU * SWI 2 ENTRY
0 0807 FAD8 A SW I J R EQU * SWI J ENTRY
00808 FADS A I RQR EQU * I RQ ENTRY
0 0 8 0 9 A FADS 8 D E7 FAC I RSRVDR B S R LDDP SET BASE PAGE , VAL I DATE STACK
0 0 8 l 0 A FADA 2 0 F7 FAD3 BRA Z B K PNT FORCE A BREAK PO I NT
00812 * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * *
0 08 1 3 * F I RQ HAN DLER
00814 * JUST RETU RN FOR TH E F I RQ INTE RRU PT
00815 ********* * **************************** * * **
0 08 1 6 FABC A F I RQR EQU RT I I MME D I ATE RETURN
8·51
PAGE 016 AS S I S T0 9 S A : 0
. ASS I ST0 9 - MC 6 8 0 9 MON ITOR
00818 **************************************************
00819 * DEF AUL'r I /O DRIVERS
0 0 8 20 **************************************************
0 08 2 2 * C I DTA - RETURN CONSOLE I NPUT CHARACT ER

00823 * OUTPUT : C=O I F NO DATA READY , C = l A=CH ARACTER
0 0 8 24 * U VOLAT I LE
0 0 8 25A F A DC DE FO A C I D rA LDU
' VECTAB+ . A C I A LOAD AC I A ADDRE S S
0 08 26A FA DE A6 C4 A L OA ,U LOAD STATUS REG I S T E R
0 0 8 27A FAEO 44 LS RA TEST REC I EVER REG I STER F LAG
0 08 28A FAE1 24 02 FAE 5 BCC C I RT N RE T U RN I F NOTH I NG
0 0 8 29A FAE 3 A6 41 A L OA 1 ,U LOAD DATA BYTE
0 08 30A FAE 5 39 C I RTN RTS RET U RN TO CALLER
00832 * C ION - INPUT C O N SO LE I N I T I AL I Z AT ION

00833 * COON - OUTPUT CONSOLE I N I T I A L I ZAT ION
0 08 3 4 * A ,X VOLAT I LE
00835 FAE 6 A C I ON EOU *
0 0 8 3 6A FAE 6 86 03 A COON LOA #3 RES E T AC I A CODE
00837A FAE8 9E FO A LOX VECTAB+ . A C I A LOAD AC I A ADDRES S
0 08 38A FAEA A7 84 A STA ,X STORE INTO STATUS REG I S T E R
0 08 3 9A FAEC 86 51 A LDA #$51 SET CONTROL
0 0840A FAE E A7 84 A STA ,X REG I STER UP
0 08 4 1A FAF O 39 RTS RTS RETURN TO CALLER
00843 * THE FOLLOW I NG HAVE NO DUT I ES TO P E RFORM

00844 FAF O A C IOF F E OU RTS CONSOLE I N PUT OF F
00845 F AF O A CO O F F E OU RTS CO N SO L E OUTPUT OF F
0 08 4 7 * CODTA - OUTPUT CHARACTE R TO CONSOLE DEV I C E

0 08 4 8 * I NPUT : A-CHARACT E R TO S E N D
00849 * O UTPUT : CHAR S E N T TO TERM I NAL ri I T H PROPER PADD I NG
0 0850 * A LL REG I ST E RS TRAN S PARENT
0 0 8 S 2A FAF 1 34 47 A C O DT A PSH S U , D , CC SAVE REG I S 'rERS , WORl( BYTE

0 08 S 3A FAF 3 DE FO A LDU VECTAB+ . AC I A ADDRES S AC I A
0 0 8 S 4A FAF S 8D IB Fa1 2 BSR CO DTAO CALL OUTPUT CHAR SUBROT I N E
0 0 8 S SA FAF 7 81 10 A CMPA tDLE ? DATA L I N E ESCAP E
0 0 8 S6A FAF 9 27 12 FBO D BEO CODTRT YES , RETU RN
0 08 S7A FAF B 06 F2 A LDB VECTAB+ . PAD DE FAULT TO CHAR PAD COUNT
0 0 8 S8A FAF D 81 00 A CMPA #CR ? CR
0 0S S 9A FAF F 26 02 FB0 3 BNE CO DTP D BRANCH NO
0 0 8 60A FB O l 06 F3 A LOB VECTAB+ . P AD+ 1 LOAD NEW L I N E PAD CO UNT
0 0 8 61A FB0 3 4F C O DTP D CLM CREAT E NULL
0 0 8 6 2A FB04 E7 E4 A STB ,S SAVE COUNT
0 0 8 6 3A FB06 8C A FCB SKIP2 ENT E R LOOP
0 08 6 4A FB07 80 09 F B 1 2 CODTLP BSH CO DTAO S E N D NU LL
0 0 8 6 SA FB09 6A E4 A DEC ,S ? F I N I S ti E D
0 08 6 6A FaOB 2A FA FB0 7 BPL CO DTLP NO , CONT I NU E WITH MORE
0 0867A FBOD 35 C7 A COD'rRT PULS PC , U , D , CC RE STORE REG I ST E RS AN D RET U RN
0 0869A FBOF 17 F F S C FA6 E CODTAD LBS R XQPAUS TEMPORARY G I V E UP CONTRO L

0 0 8 7 0 A F B 1 2 £6 C4 A CO DTAO L O B ,U LOAD AC I A CONTROL REG I ST E R
0 08 7 1A FBl4 CS 02 A B IT B 1$02 ? TX REG I ST E R CLEAR
8·52
PAG E 017 ASS I ST0 9 . SA : 0 AS S I ST 0 9 - MC 6 8 0 9 MON I TOR
0 0 8 7 2 A F B 1 6 27 F7 FBO F BEQ CO DTAD RE LE AS E CONTROL IF NOT

0 0 8 7 3 A FB 1 8 A7 41 A STA 1 ,U STORE I NTO DATA REG I S T E R
0 0 8 7 4A FBIA 39 RTS RETU RN T O CALLE R
00875 *E
00877 * BSON - TURN ON RE AD/VE R I FY/PUNCH MECHAN I S M

00878 * A IS VOLAT I LE
0 08 8 0A FB I B 86 11 A BSON LD A #$11 SET RE A D CO DE

0 0 8 8 1A FB I D 6D 66 A TST 6,S ? READ OR VE R I F Y
0 0 8 8 2A FBIF 26 01 FB22 BNE BSON 2 BRAN CH YES
0 0 8 8 3A FB21 4C I NCA SET TO WRITE
0 08 8 4A FB22 3F B S ON 2 SWI PERFORM OUT PUT
0 0 8 8 sA FB 2 3 01 A FCB OUTC H F UNCT ION
0 0 8 8 6A FB 2 4 OC 8F A INC M I S F LG SET LOAD IN PROG RE S S F L A G
0 0887A FB 2 6 39 RTS RETU RN TO CALLE R
00889 *
B S OF F - T U RN OF F READ/VERI FY/PUNCH ME CHAN I SM
00890 * A , X VOLAT I LE
0 0 8 9 1A FB27 86 14 A BSO F F LDA # $ 14 TO DC4 - ST OP
0 0 8 9 2A FB29 3F SW I S E N D OUT
0 0 8 9 3A F B 2A 01 A FC B OUTCH F U NC T I O N
0 0 8 9 4A FB2B 4A DECA CHANGE TO DC 3 ( X-OF F )
Q 0 8 9 sA FB 2C 3F SW I S E N D OUT
0 0 8 9 6A FB2 D 01 A FCB OUTCH F U N CT I ON
0 08 9 7A FB2E OA 8F A DEC M I S F LG C L E AR LOAD I N PROGRE SS F LAG
0 0 89 8A FB 3 0 8E 61A8 A LDX #25000 DE LAY 1 SECOND ( 2 M H Z C LOC K )
0 0899A FB 3 3 30 IF A BSO F LP LE AX -l , X COUNT DOWN
00900A FB 3 s 26 FC FB3 3 B NE B SO F LP LOOP T I LL DONE
0 0901A FB 37 39 RTS RETURN TO CALLE R
00903 *
B S DT A - READ/VER I FY/PUNCH HAN DLER
0 0904 * I N PUT : S + 6 =CODE BYTE , VERI F Y ( - l ) , PUNCH ( O ) , LOAD ( l )
00905 *
S + 4 = START ADDRE S S
0 0906 *
S+ 2 = STOP ADDRE S S
*
00907 S+O - RETURN ADDRE S S
0090B *
OUTPUT : Z - 1 NORMAL COMP LET I ON , Z - O I NVAL I D LOAD/VE R
*
00909 REG I �T E RS A R E VOLAT I L E
0 0 9 1 1A FB 3 8 B E 62 A BS DTA LDU 2,S U-TO ADDRE S S OR OF F S ET

0 0 9 1 2A FB3A 6 0 66 A TST 6 ,S ? PUNCH
0 0 9 1 3 1\ F B 3 C 2 7 54 FB9 2 BEQ BS D P U N B RAN CH Y E S
*
00914 DU R I NG READ/VER I F Y I S + 2 -Msn ADDRE S S SAVE BYTE
* S + l - SYTE COU NT E R
00915
*
OO!H6 S+O -CHECKSUM
* U HOLDS O F F S ET
00917
009 1BA PB3E 32 70 A LEAS -3 , S ROOM FOR WORK /COU NTER/C H E C K SUM
0 0 9 l 9A PB4 0 3F IJ� DLL')l SW I GET NEXT CH ARACT E R
0 0 9 20 A P B 4 l 00 A FCU INCHNP FUNCT I O N
0 0 9 2 1A FB4 2 81 53 A aSDLD2 CMPA tIS ? START OF S l / S 9
0 0 9 2 2 A E' B 4 4 26 FA F B4 0 8NE BS DLOl DRAN CH NOT
0 0 9 2 3 ,\ E' B 4 & 3F SWI GE'r N E X T CH ARACT E K
8-53
P AG E 018 ASS I ST0 9 . S A : 0 AS S I ST0 9 - M C 6 8 0 9 MON ITOR
0 09 24A FB47 00 A FCB INCHNP F UNCT I ON

0 09 25A FB48 81 39 A CMPA i' 9 ? HAVE S9
0 0 9 26A FB4A 27 22 FB6E BEQ BSDSRT YES , RETURN GOOD CODE
0 0 9 27A FB4C 81 31 A CMPA i'l ? HAVE NEW RE CORD
009 28A FB4E 26 F2 FB42 BNE BSDLD2 BRANCH IF NOT
0 0 9 29A FBSO 6F E4 A CLR ,S C LEAR CH E C K S UM
009 30A FBS2 80 21 FB7S BS R BYTE OBTA I N BY TE COU NT
0 0 9 31A FBS4 E7 61 A STB 1 ,S SAVE FOR DECRE M E N T
00932 * READ ADDRE S S
0 0 9 33A FBS6 80 10 FB7 S BS R BYTE OBTA I N H I G H VA LUE
0 0 9 34A FBS8 E7 62 A STB 2,S SAVE IT
0 0 9 3 5A F B SA 80 19 FB7 S BS R BYTE OBTA I N LOW VA LUE
0 0 9 36A FB SC A6 62 A LOA 2,S MAK E D=VALUE
009 37A FBSE 31 CB A LEAY D,U Y=ADDRES S+OF F S E'!,
00938 * STORE TEXT
0 0 9 39A FB60 80 13 F87 S BS DNXT B S R BYTE NEXT BYTE
00940A FB62 27 OC FB70 BEQ BSDEOL BRANC H IF CHECKSUM
0 0 9 4 1A FB64 60 69 A TST 9,S ? VE R I F Y ON LY
0 0 9 4 2A 1o� B 6 6 2B 02 FB6A BM I BS DCMP Y E S , ONLY COMPARE
0 0 9 43A FB6S E7 A4 A STB ,Y STORE I NTO ME MORY
0 0 9 4 4A Fa6A El AO A BSDCMP CMPB , Y+ ? VAL I D RAM
0 0 9 4 5A FB6C 27 F2 FB60 BEQ BS DNXT Y E S , CONT I NU E RE A D I NG
0 09 4 6A FB6E 35 92 A BS DSRT P U LS PC , X , A RETURN W I T H Z SET PRO P E R
0 0 9 4 8 A FB70 4C BS DEOL INCA ? VA L I D C H E C K S U M

0 0 9 4 9 A FB7l 27 CD FB4 0 BEQ BSDLDI BRANCH Y E S
0 09 S 0 A FB73 20 F9 FB6E BRA BS DSRT RETURN Z = O I NVAL I D
00952 * BYTE BU I LDS 8 B IT VALUE F ROM TWO HEX D I G ITS IN

0 09 S 3A FB 7 S 80 12 F B 8 9 BYTE BSR BYTH E X OBTA I N F I RST H E X
009S4A FB77 C6 10 A LOB #16 PRE P ARE S H I FT
0 09 S SA FB79 3D MU L OVE R TO A
00956A FB7A 80 00 FB89 BS R BYTHEX OBTA I N S E CO N D HEX
0 0 9 5 7A FB7C 34 04 A PSHS B SAVE H I GH HEX
009 S8A FB7E AS EO A ADDA , S+ COMB I N E BOTH S I DE S
0 09 59A FB80 IF 89 A TFR A,B S E N D BACK I N B
0 0960A FB82 AB 62 A ADDA 2,S COMP UTE N E W CH E C K S U M
0 0 961A FB84 A7 62 A STA 2 ,S STORE BACK
0 0 9 6 2A FB86 6A 63 A DEC 3 ,S DECREMENT BYTE COUNT
0 0 9 6 3A FB88 39 BYTRTS RTS RET URN TO CALLER
0 0 9 6 5A FB89 3F BYTH EX SW I GET NEXT HEX

0 09 6 6A FB8A 00 A FCB I N CH N P CHARACT E R
0 09 6 7 A FB8B 17 0 1 04 F D 6 2 LBSR CNVHEX CONVERT TO HEX
0 0968A FB 8 E 27 F8 FBS8 BEQ BYTRTS RETURN IF VAL I D H E X
00969A FB90 35 F2 A PULS PC , U , Y , X , A RET U RN TO CAL L E R WITH Z = O
00971 * PUNCH STACK US E : S + 8 =TO ADDRE S S

0 09 7 2 * S+ 6 = RE T U RN ADDRE SS
00973 * S + 4 = S AV E D PAD D I NG VAL U E S
00974 * S + 2 F RO M ADDRE S S
00975 *
S+ I = F RAME COU NT / C H E C K S U M
00976 *
S + O = BYTE COUNT
0 0977A F B 9 2 DE F2 A BS D P U N LOU VECTAB+ . PAD LOAD PAD D I NG VAL U E S
0 0978A F B 9 4 AE 64 A LOX 4,S X= F ROM ADDRE S S
0 0979A FB96 34 56 A PSUS U,X,D CREATE STAC K WORK AREA
00980A FB98 CC 0018 A LDD i24 SET A= O , B = 2 4
8-54
PAGE 019 AS S I ST0 9 . SA : 0 AS S I ST 0 9 - M C 6 8 0 9 MON I TOR
0 0 9 8 1A FB 9 B 07 F2 A ST8 VECTAB+ . PAD SETUP 24 CH ARACTER PADS

0 0 9 8 2A FB 9 D 3F SWI S E N D NU LLS OUT
0 0 9 8 3A FB9E 01 A FCB OUTC H FUNCT ION
0 0 9 8 4A FB9F C6 04 A LDB t4 SETU P NEW L I N E PAD TO 4
0 0 9 8 5A FBAl DD F2 A STD VECTAB+ . P AD SETUP PUNCH PADD I NG
0 0986 * CALCULAT E S I Z E
0 0 9 8 7A FBA3 EC 68 A BS PGO LDD 8 ,S LOAD TO
0 0988A F BA 5 A3 62 A SUBD 2 ,s M I N U S F ROM= LENGTH
0 0 9 8 9A FBA7 1083 0018 A CMP D # 24 ? MORE TH AN 2 3
0 0 9 9 0A FBAB 25 02 FBAF B LO BS POK NO , OK
0 0 9 9 1A FBAD C6 17 A LDB #23 FORCE TO 2 3 MAX
0 0 9 9 2A FBAF 5C BS POK I NC B P RE PARE CO U NT E R
0 0 9 9 3A FBB O E7 E4 A STB ,S STORE BYTE COU NT
0 0 9 9 4A FBB2 CB 03 A ADDB #3 ADJ UST TO F RAME CO U NT
0 0 9 9 5A FBB 4 E7 61 A STB l ,s SAVE
0 0996 * PUNCH C R , L F , NU LS , S , l
0 0997A FBB 6 3 0 8C 33 LEAX < B S PSTR , PCR LOAD START RE CORD HEADER
0 0998A FBB 9 3 F SWI SEND OUT
0 0999A FBBA 03 A FCB PDATA F UN C T I O N
01000 * S E N D F RAME COUNT
O lO O lA FBBB S F C LRB I N I T I AL I Z E C H E C K S U M
0 1 0 0 2A FBBC 30 61 A LEAX l,s PO I NT TO F R�E COUNT AN D ADDR
0 10 0 3A FBBE 80 27 FBE7 BSR BS P U N 2 S E N D F RA M E CO U NT
01004 * DATA ADDRE S S
0 1 0 0 5A FBC O 8 0 25 FBE 7 BSR BS PU N 2 S E N D ADDRE S S H I
0 1006A FBC 2 8 0 23 FBE7 BS R BS P U N 2 S E N D ADDRE S S LOW
0 10 0 7 * PUNCH DATA
0 10 0 8A FBC 4 AE 62 A LDX 2,s LOAD START DATA ADDRE S S
0 10 0 9 A FBC 6 80 lF FBE 7 BS PMRE B S R BS P U N 2 S E N D OUT N E X T BYTE
O lO l OA FBC 8 6A E4 A DE C ,s ? F I NAL BYTE
O lO l lA FBCA 26 FA FBC6 BNE BS PMRE LOOP I F NO'l' DONE
0 10 1 2A F acc AF 62 A STX 2,s U P DATE F ROM ADDRE S S VALU E
0 10 1 3 * PUNCH CH E C K S U M
01014A FBCE 53 COMB COMPLEMENT
0 1 0 1 5A FBCF E7 61 A STB l ,s STORE FOR S E N DOUT
0 10 1 6A FBDl 30 61 A LEAX l ,s PO I NT TO I T
0 1 0 1 7A FBD3 8D 14 FBE9 BS R BSPUNC S E N D OUT AS H E X
0 1 0 1 8A FBD5 AE 68 A LDX 8,s LOAD TO P ADDRES S
0 10 1 9A F B D7 AC 62 A CMPX 2,s ? DON E
0 1020A F B D9 24 C8 F BA3 BH S BS PGO BRANCH NOT
0 1 0 21A F B DB 30 BC 1 1 LEAX < B S PEO F , PCR PRE PARE E N D OF F I LE
O l0 22A F B DE 3F SW I S E N D OUT STR I NG
0 10 2 3A F B DF 03 A FCB P DATA FUNCT ION
0 1024A FBEO EC 64 A LDD 4,s RE COVER PAD COUNTS
0 10 2 5A FBE2 DD F2 A STD VECTAB+ . P AD RESTORE
0 10 26 A FBE4 4F CLRA SET Z = l FOR OK RET U RN
0 10 27A FBE 5 35 06 A PULS PC , U , X , O RETU RN W I T H OK CO DE
0 1 0 2 9 A F B E 7 EB 84 A BS PUN 2 ADDB ,X ADD TO C H E C K S U M

0 1 0 30A FBE9 16 F D E D F 9 D9 BSPUNC LBRA ZOUT 2 H S E N D OUT A S H E X AN D RETU RN
0 1 0 3 2A FBEC 53 A BS PSTR FCB ' S , ' l , EOT CR , LF , N U L L S , S , l

0 10 3 3A FBEF 53 A BS PEOF FCC /S 9.0 3 0 0 0 0 FC/EOF STRI N G
0 10 3 4 A FBF 9 00 A FC B C R , L F , EOT
01036 * H S DTA - H I G H S P E E D P R I NT ME MORY
8-55
P AG E 020 AS S I ST 0 9 . SA : 0 ASS I S T0 9 - M C 6 8 0 9 MON I TOR
*
0 10 37 I N PUT : S + 4 = START ADDRE SS
*
0 10 3 8 S + 2 = STOP ADDRE S S
*
01039 S+O = RE T U RN ADDRE S S
0 10 4 0 *
X , D V<? L AT I LE
*
01042 S E N D T I T LE
0 10 4 3A FBFC 3F H S DT A SW I SEND NEW L I N E
0 10 4 4 A FBF D 06 A FCB PCRLF FUN C T I ON
0 1 0 4 SA FBF E C6 06 A LOB #6 PRE PARE 6 SPAC E S
0 10 4 6A FC O O 3F H S B LN K SW I S E N D BLAN K
0 10 4 7 A FC O l 07 A FCB S PAC E FUNCT ION
0 10 48A FC 0 2 SA DE C B COUNT DOWN
0 1 0 49A FC 0 3 26 FB FCO O BNE HS B LNK LOOP IF MO RE
O lO SOA FC O S SF C LR B SETU P BYTE COUNT
O l O S lA FC 0 6 lF 98 A HSHTTL TFR B ,A PRE PARE FOR CONVERT
0 1 0 S 2A FC 0 8 17 F DDB F 9 E 6 LBS R ZOUTHX CONVE RT TO A HEX DIG IT
0 10 S 3A FCO B 3F SW I SEND BLANK
0 1 0 S4A FC O C 07 A FCB S PAC E FUNCT ION
O lO S SA FC O D 3F SWI SEND ANOT H E R
0 10 S6A FCOE 07 A FCB S PACE B LANK
0 10 S7A FC O F SC INCB UP ANOTH E R
0 10 S8 A FC 1 0 Cl 10 A CMPB # $10 ? PAST 'F'
0 10 S9A FC1 2 25 F2 FC0 6 B LO HS HTTL LOOP U NT I L SO
0 10 6 0 A FC 1 4 IF H S U L N E SW I TO NEXT L I N E
0 10 6 1A FC 1 5 06 A FCB PCRLF F UNCT ION
0 1 0 6 2A FC 1 6 25 2F FC47 BC S H S D RTN RE'rURN I F U S E R ENTERED CTL- X
0 10 6 3A FC 1 8 30 64 A LEAX 4 ,S PO I NT AT ADDRESS TO CONVERT
0 10 6 4A FC1A 3F SW I PRI NT OUT ADDRE S S
0 10 6 SA FC I B 05 A FeB OUT 4 H S F UNCT ION
0 10 6 6A FCIC AE 64 A LDX 4,S LOAD ADDRE S S P RO P E R
0 10 6 7A FC I E C6 10 A LDB #16 NEXT S I XT E E N
0 10 6 8A FC 2 0 3F H S H NXT SWI CONVERT BYTE TO HEX AN D S E N D
0 1069A FC 2 1 04 A FCB OUT 2 H S F U N CT I ON
0 1 0 7 0A FC 2 2 SA DE C B COUNT DOWN
O l O 7 lA FC 2 3 26 FB FC20 BNE H S H NXT LOOP I F NOT S I XTEENTH
O l o nA FC 2 S IF SW I SEND BLANK
0 10 7 3A FC 2 6 07 A FCB S PACE F UNCT ION
0 1 0 7 4A FC 2 7 AE 64 A LOX 4 ,S RE LO AD F RO M ADDRE S S
0 1 0 7 SA FC29 C6 10 A LOB #16 COU NT
0 10 7 6A FC2B A6 80 A H S H C H R LDA , X+ NEXT BYTE
O l 0 77A FC 2 D 2B 04 FCl l BM I HSH DOT TOO LARG E , TO A DOT
0 1078A FC 2 F 81 20 A CMPA #' ? LOWER TH AN A BLANK
0 10 7 9 A FC 3 l 24 02 FC3 S BH S HSHCOK NO , BRANCH OK
0 10 8 0A FC l 3 86 2E A H S H DOT L DA #' • CONVERT I NVAL I D TO A BLANK
0 1 0 8 1A FC 3 S 3F HSUCOK SWI S E N D CHARACT E R
0 1 0 8 2A FC 3 6 01 A FCB OUTC H FUNCT ION
0 10 8 3A FC 3 7 SA DE C B ? DON E
0 10 84A FC 3 8 26 Fl FC2 B BNE HSHCHR BRANC H NO
0 1 0 8 SA FC3A AC 62 A C PX 2,S ? PAST LAST ADDRE S S
0. 1 0 8 6 A FClC 24 09 FC4 7 BHS H S DRTN QU I T IF SO
0 1087A FC 3 E AF 64 A STX 4 ,S U P DAT E F ROM AD DRE S S
0 10 8 8 A FC40 A6 65 A LOA 5,S LOAD LOW BYTE ADD RE S S
0 1089A FC4 2 48 AS LA ? TO SECT I O N BOU N DRY
0 1 0 9 0A FC 4 3 26 CF FC 1 4 8NE HSHLNE BRANCH I F NOT
0 1 0 9 1A FC 4 5 20 B5 FBFC BRA H S DTA BRAN CH IF SO
0 1 0 9 2A FC 4 7 IF H S DRT N SW I S E N D NEW L I N E
0 10 9 lA FC 4 8 06 A FCB PCRLF FUNCT ION
0 1 0 9 4A FC49 19 RTS RETURN TO CALLER
8-56
PAG E 021 ASS I ST0 9 . S A : 0 AS S I ST0 9 - MC 6 8 0 9 MON I TOR
01095 *F
01097 ***********************************************
0 10 9 8 * A S S I S T 0 9 C O M M A N D S
0 10 9 9 ***********************************************
0 1101 * * * * * * * * * * * * * REG I ST E RS - D I S PLAY AN D CHANGE REG I ST E RS

0 1 1 0 2 A FC 4 A 8 D 23 FC 6 F CREG BSR REG P RT PRINT REG I STERS
0 1 1 0 3 A FC 4 C 4 C I NCA S E T FO R CHANGE FUNCT ION
0 1 1 0 4A FC 4 D 8 D 21 FC7 0 BSR REGCHG GO CHANGE , D I S P LAY REG I S'r E RS
0 1 1 0 5 A FC 4 F 3 9 RTS RETURN TO COMMAND PROCESSOR
0 1107 ********************************************
0 1 10 8 * REG PRT - PRI NT/CHANGE REG I S T E RS SUBROUT I N E
0 1109 * WI L L ABORT TO ' C MDBAD ' I F OVERF LOW DETECT E D DUR I NG
0 11 1 0 * A CHANGE OPERAT I O N . CHANGE D I S P LAYS REG I STERS WHE N
0 1111 * DONE .
01112 * REG I ST E R MASK L I ST CON S I STS OF :
0 1113 * A ) C HARACTE RS DENOT I NG REG ISTER
0 1114 * B ) Z E RO FOR ONE BYTE , - 1 FOR TWO
01115 * C ) O F F S ET ON STACK TO REG I S'r E R POS I T I ON
0 1116 * I N P UT : S P + 4 = STACK E D REG I STERS
0 1117 * A= O PRI NT , At O PRI NT AND CHANGE
0 1118 * OUT PUT : ( ON LY POR REG I STER D I S P LAY )
0 1119 * C = l CONTROL-X EN'rERE D , C = O OTH E RW I S E
01120 * VOLAT I LE : D , X ( CHANGE )
0 1121 * B , X ( D I S P LAY )
0 1122 *******************************************
0 1 1 2 3A FC 5 0 50 A REGMS K F C B ' P , ' C , - 1 , 1 9 PC REG
0 11 24A FC 5 4 41 A FCB ' A , 0 , 10 A REG
0 1 1 2 5A FC57 42 A FCB ' B,0 ,11 B REG
0 1126A FC5A 58 A FCB ' X , - 1 , 1 3 X REG
0 1127A FC S D 59 A FCB ' Y , - 1 , 1 5 Y R� G
0 1128A FC6 0 55 A FCB ' U , - 1 , 1 7 U RE G
0 1129A FC 6 3 53 A FC B ' 5 , -1 , 1 S REG
0 1130A FC 6 6 43 A FCB ' c , ' C , 0 , 9 C C RE G
0 1 1 3 1A FC6A 44 A FC B ' D , ' P , 0 , 1 2 DP REG
0 1 1 3 2A FC 6 E 00 A FC B 0 E N D OF L I ST
0 1 1 3 4A FC 6 F 4 F REG P RT CLRA SETUP P R I NT ONLY F LAG

0 1 1 3 SA FC 7 0 30 E8 10 A RE G C HG L EAX 4+12 , S READY STACK VALUE
0 1 l 3 6A FC 7 3 34 32 A PSHS y , X ,A SAV E ON STACK WITH OPT I O N
01l37A FC 7 S 31 8C 08 LEAY REGM S K , PC R LOAD REG I S T E R MAS K
01l38A FC 7 8 EC AO A REG P 1 LD D , Y+ LOAD NEXT CHAR OR < - 0
0 1 1 3 9A FC7A 40 TSTA ? END OF CH ARACTE RS
O 1l40A FC 7 B 2F 04 FC 8 1 BLE RE G P 2 BRANCH NOT CH ARAC T E R
0 11 4 1A FC 7 D 3F SW I S E N D TO CONSOLE
0 1 l 4 2A FC 7 E 01 A FC B OUTCH F U N C T I O N B Y TE
O 1 l 4 3A FC 7 F 20 F7 FC 7 S B RA RE G P 1 C H E C K NEXT
O 1 l 4 4A FC 8 1 86 20 A RE G P 2 LOA #'- READY ' - '
O 1 l4 SA FC 8 3 3F SW I S E N D OUT
O 1l46A FC 8 4 01 A FCB OUTCH W I T H OUTCH
0 1l47A FC 8 S 30 E5 A LEAX B,S X- > REG I ST E R TO P R I NT
01l48A FC 8 7 60 E4 A TST ,S ? C H ANGE OPT I O N
8·57
PAG E 022 AS S l I:iT0 9 . SA : 0 ASS I ST0 9 - M C 6 8 0 9 MON I TOR
0 1 l 4 9A FC S 9 26 12 FC 9 0 BU E REGC NG BRANCH YE S
0 1 l 50A FC S B 60 3F A TST -l , Y ? O N E OR TWO BYT E S
0 1 l 5 1A FC S O 27 03 FC 9 2 BEQ REG P 3 BRAN C H Z E RO M E A N S ON E
0 1 l 5 2A FC S F 3F SWI P E RF O RM WORD HEX
O 1 l 5 3A FC90 05 A FCB OUT4 H S FU N CT I O N
0 1 l 54A FC 9 l SC A FCB SKI P2 SK I P BYTl-� P R I NT
O 1 l55A FC 9 2 3F REGP 3 SW I P E RFORM BYTE HEX
0 1 l 56A FC 9 3 04 A FCB OUT2ffS FUNCT ION
0 1l 5 7A FC 9 4 EC AO A REG 4 LOO , Y+ TO FRONT OF N E X T ENTRY
0 1 l 5SA FC 9 6 SO TSTB ? E N D OF ENT R I E S
0 1 l 59A FC 9 7 26 OF FC7S BNE RE G P l LOO P I F MORE
O 1 l 60A FC 9 9 3F SW I FORC E NEW L I N E
O l l 6 lA FC 9 A 06 A FCB PCRLF F UNCT ION
O 1 l 6 2A FC 9 B 35 B2 A REGRTN P U LS PC , y , X , A RESTORE STACK AN D RE TU RN
O 1 l 64A FC 9 0 SO 40 FCOF REGCNG BS R BLDNNB I N PUT B I NARY NUMBER

0 1 l65A FC 9 F 27 10 FCBl BEQ REGNXC I F CHANGE TH E N JUMP
O1l66A FCAl Sl 00 A C M PA t CR ? NO MORE DE S I RE D
O 1l67A FCA3 27 lE FCC 3 BEQ RE GAG N BRANCH NOP E
O1l6SA FCA 5 E6 3F A L OB -l , Y LOAD S I Z E F LAG
0 1l69A FCA7 SA OE CB M I N U S ONE
0 1l 70A FCAS 50 NEGB MA K E PO S I T I V E
O l l 7 1A FCA 9 5S AS L B T I ME S TWO ( = 2 OR = 4 )
O l l 7 2A FCAA 3F R E G S K P SWI PERFORM S PAC E S
O 1 l 73A FCAB 07 A FCB S PAC E F U NCT I O N
0 1l 7 4A FCAC SA DECB
0 1 l 7 5A FCAD 26 FB F C AA BN E REG S K P LOOP I F MO R E
0 1 l 76A FCAF 20 E3 FC9 4 B RA REG 4 CONT I NUE W I T H NEXT REG I ST E R
O ll 77A FCBl A7 E4 A RE G N XC ST A ,S SAV E DE L I M IT E R I N OPT I O N
01178 * ( ALWAYS > 0)
0 1 l79A FC B 3
DC 9B A LDD N UMB E R OBTA I N B I NARY RE S U LT
O l l SOA FC B S
60 3F A TST -l , Y ? TWO BYT E S WORTH
O ll SlA F CB 7
26 02 FCBB B NE RE G TWO BRAN CH YES
0 1 l 8 2A F CB 9
A6 82 A L OA , -X SETUP FOR TWO
0 1 l 8 3A FCB B
ED 84 A REGTWO STD ,X STORE I N NEW VALUE
0 1 1 S 4A FCB D
A6 E4 A LOA ,S RECOV E R D E L I M IT E R
0 11 8SA FCBF81 00 A CM PA tCR ? E N D O F CHANGES
0 1 1 8 6 A FCC l 26 01 FC 9 4 BNE RE G 4 NO , K E E P O N TRUCK ' N
0 1187 * MOVE STAC K E D DATA TO NEW STACK I N CASE STACK
0 1188 * PO I NTER HAS CHAN G E D
0 11 89A FC C 3 30 80 E28A REGAGN LEAX TSTAC K , PCR LOA D TEMP AREA
0 11 90A FCC 7 C6 15 A LOB # 21 LOAD COU NT
0 1 1 9 lA FCC 9 35 02 A REGTF l PULS A NEXT B Y TE
0 1 l 9 2A FCCB A7 80 A STA , X+ STORE I NT O T E M P
0 1 1 93A FCC D SA DECB COU NT DOWN
0 11 94A FCCE 26 F9 FCC9 BNE RE GT F l LOO P I F MORE
0 1 l 9SA F C DO 10EE 8 8 EC A LOS ... 2 0 , X LOAD NEW STACK PO I NTER
0 11 96A F C D4 C6 15 A LOB #21 LOAD COUNT AG A I N
0 1 1 97A F C D6 A6 82 A REGT F 2 LOA , -X NEXT T O STO RE
0 1 1 98A FC D8 34 02 A PSRS A BACK ONTO N E W S T A C K
0 1 1 99A FC DA SA DECB COUNT DOWN
0 1 200A F C DB 26 F9 FCD6 BNE RE G T F 2 LOO P IF MORE
0 1 2 0 1A FC DD 20 BC FC9 B BRA RE G RTN GO RE START COMMA N D
0 1203 *********************************************
0 1204 * BLDNUM - B U I LDS B I NARY VAL U E F RO M I N P UT H E X
01205 * TH E ACT IVE E X P RE S S ION HAN DLER I S U S E D .
B·58
PAGE 023 AS S I ST 0 9 . S A : 0 AS S I ST0 9 - M C 6 8 0 9 MON ITOR
0 1206 * I NPUT : S=RE T U RN ADDRES S

0 1207 * OUTPUT : A= DE L I M IT E R WH I CH TE RM I NAT E D VALUE
01208 * ( I F DELM NOT Z E RO )
0 1209 * n NU MB E R " =WORD B INARY RE S U LT
0 1210 * Z = 1 I F I N P UT RE C I EVED , Z = O I F NO HEX REC I E VED
01211 * REG I STERS ARE TRAN S PARENT
0 1212 **********************************************
01214 * EXE CUTE S I NGLE O R EXTEN D E D ROM EXPRE S S I O N HAN DLER

0 1215 *
01216 * THE F LAG " DE L I M n I S US E D AS FOLLOWS :
0 1217 * DE L I M = O N O LEAD I N G B LANK S , N O F O RC E D 'rE RM I N A'rOR
0 1218 * DE L I M =CHR ACC EPT LEAD I NG ' CH R ' S , FORC E D TERM I NATOR
0 12 1 9A FC DF 4 F BLDNNB CLRA NO DYNAM I C DE L I M I T E R
0 1220A FCEO 8C A FCB SKIP2 S K I P NEXT I NSTRUC'r r ClII
Q 1221 * B U I L D WITH LEAD I NG B LANK S
0 1 2 2 2A FCE1 8 6 20 A BLDNUM LDA #' ALLOW LEAD I N G B LANK S
0 1223A FCE 3 9 7 8E A STA DE L I M STORE A S DEL I M IT E R
0 1224A FCE 5 6 E 9D E3 0 3 JMP [ V ECTAB+ . E XPAN , PC R ] TO EXP ANALY Z E R
0 12 2 6 * TH I S I S 'rH E DEFAU L'f S I NG L E ROM ANALY Z E R . WE ACC E PT :

0 1227 * 1 ) HEX I NP UT
01228 * 2 ) ' M ' F O R LAS 'r MEMORY EXAM I N E ADDRE S S
0 1229 * 3 ) ' P ' F O R PROG RAM COU NTER ADDRE S S
0 1230 * 4 ) ' w ' F O R W I N DOW VAL U E
0 1231 * 5 ) ' @ ' FOR I N D I RECT VALU E
0 1 2 3 2A FC E 9 3 4 14 A EXPl PSHS X,B S AVE REG I STERS
0 12 3 3A FCEB 8 0 5C FD49 EXPDLM B S R BLDHX I C L E AR NUMBE R , CHECK F I RST CHAR
0 1234A FCED 2 7 18 F D0 7 BEQ EX P2 IF HEX DIG IT CONT I NU E BU I L D I NG
01235 * SK I P B LANK S I F DE S I KE D
0 1236A FCEF 9 1 8E A CMPA DE L I M ? C ORRECT DE L I M IT E R
0 1237A FCF 1 2 7 F8 FCEB BEQ EXP DLM Y E S , I GNORE rr
0 12 3 8 * TEST FOR M OR P
01239A FCF 3 9E 9E A LOX ADDR DEF AU LT FOR ' M '
01240A FCF 5 81 40 A CMPA #'M ? r-I E MO RY EXAM I N E ADDR WANTE D
0 1 2 4 1A FCF 7 27 16 FDOF BEQ EXPTDL BRANCH I F SO
0 1 2 4 2A FC F 9 9E 93 A LOX PCNT E R DE F AU LT F O R ' P '
0 1 2 4 3A FC F B 81 50 A CMPA #'P ? LAST PROGRAM COUNT E R WAN T E D
0 1244A FCF D 27 10 FDOF BEQ EXPTDL BRANCH I F SO
0 1245A FCFF 9E AO A LOX W I N DOW D E F AU LT TO W I N DOW
0 1246A F OO l 81 57 A CMPA #'W ? W I N DOW WANTEU
0 1247A F D0 3 27 OA FDOF BEQ EXPTDL
0 1248A F D0 5 35 94 A EXPRTN P U LS PC , X , B RETU RN AN D RESTORE REG I ST E RS
0 1249 * GOT HEX , NOW CONT I N U E BU I L D I NG
0 1250A FD07 8D 44 FD4 D EXP2 BSR BLDHEX COMPUTE NEXT D I G I T
0 1 2 5 1A FD09 27 FC FD07 BEQ EXP2 CONT I NU E I F MORE
0 1 2 5 2A F DO B 2 0 OA F D1 7 BRA E X P C DL S EARCH FOR +/-
01253 * STORE VALUE AN D CHECK I F N E E D DEL I M I T E R
0 12 5 4A FDO D AE 84 A EXPT D I LDX ,X IN D I RECT ION DE S I RE D
0 1 2 5 5A F DO F 9F 9B A EXPTDL STX NUMBER STORE RE S U LT
0 1 2 5 .6 A FDll OD 8E A TST DE L I M ? T O FORC E A DE L I M IT E R
0 1257A FD13 27 FO F D0 5 BEQ E X P RTN RETU RN I F NOT WITH VALUE
0 1258A FD15 8D 62 F D7 9 BS R READ OBTA I N NEXT CHARACTE R
01259 * TEST FOR + OR -
0 1 2 6 0A FD17 9E 9B A EX PCDL LOX NUM B E R LOAD LAST VALUE
0 1 2 6 1A F D1 9 81 2B A CMPA #'+ ? ADD OPERATOR
0 1 2 6 2A F OIB 26 OE FD2B BNE EX PCHM B RANC H NOT
0 1 2 6 3A F D1 D 8D 23 F 04 2 BSR EXPTRM COMPUTE NEXT T E RM
8-59
PAGE 024 ASS I ST0 9 . SA : 0 AS S I ST0 9 - M C 6 8 0 9 MON I TOR
0 1 2 6 4A F DI F 34 02 A PSHS A SAVE DE L I M I T E R
0 1 2 6 5A FD21 DC 9B A LDD NUMBE R LOAD N E W T E RM
0 1 2 6 6A FD23 30 8B A EX PADD LEAX D,X ADD TO X
0 1 267A FD25 9F 9B A STX NUMB E R STORE AS NEW RE S U LT
0 1268A F D2 7 35 02 A PULS A RE STO RE DE L I M I 'r E R
0 1269A F D29 20 EC F01 7 BRA E X P C DL NOW T E S T IT
0 1 2 7 0A FD2B 81 20 A EXPCHM C M PA #'- ? S U BTRACT O P E RATOR
0 1 2 7 1A FD2 D 27 07 FD36 BEQ EXPSUB BRANC H I F SO
0 1 2 7 2A FD2F 81 40 A CMPA #'@ ? I N D I RE C T I O N DE S I RE D
0 1 2 7 3A FD31 27 DA FOO D BEQ E X PT D I BRANC H I F SO
0 1 2 7 4A FD33 SF C LRB SET DE L I M IT E R RETURN
0 1 2 7 5A FD34 20 CF F DO S BRA EXPRTN AN D RET U RN TO CALLE R
01276A F D3 6 80 OA F D4 2 EXPSUB BSR EXPTRM OBTA I N NEXT T E RM
0 1277A FD38 34 02 A PSHS A SAV E DE L I M I T E R
0 1278A F D3A DC 9B A LDD NUMB E R LOAD UP NEXT TERM
0 1279A F D3 C 40 NEGA NEGATE A
0 1 2 80A FD3D 50 NEGB NEGATE B
0 1 2 8 1A F D 3E 82 00 A SBCA #0 CORRECT FO R A
0 1 2 8 2A FD40 20 El FD23 B RA EX PADD GO ADD TO E X P RE S ION
0 1283 * COMPUTE NEXT EX PRES S I ON T E RM
0 1284 * OUTPUT : X=OLD VALU E
01285 * ' N UMB E R ' =NEXT TE RM
0 12 86A F D4 2 8 0 90 FCEl EX PTRM a S R B LDNUM OBTAI N N E X T VAL U E
0 1 2 87A F D 4 4 27 32 F D7 8 BEQ CNVRTS RETU RN I F VAL I D NUMBER
0 1 288A F D4 6 1 6 FC1 3 F 9 5 C BLDBAD LBRA CMD�AD ABO RT COMMAN D I F I NVAL I D
0 1290 *********************************************
0 1291 * BU I L D B I NARY VALU E U S I NG I N PUT CHARACT E RS .
0 1292 * I N PUT : A=AS C I I HEX VALUE OR DE L I M IT E R
0 12 9 3 * S P + O = RETURN ADDRES S
0 1 2 94 * S P+ 2 = 1 6 B I T RE S U LT AREA
0 1295 * OUTPUT : Z = l A= B I NARY VALUE
0 1296 * Z = O I F I NVAL I D H E X CHARAC T E R ( A UNCHANG ED )
01297 * VOLAT I LE : 0
0 1298 ****************************************
0 1 2 99A FD49 OF 9B A B L DH X I C LR NUI-t B E R CLEAR NUMB E R
0 1300A F D4 B OF 9C A CLR NUMBER+ ! CLEAR NU M B E R
0 13 0 1A F D4 D 80 2A FD7 9 B LDHEX BSR RE AD GE'l' I l� P UT CHARACT E R
0 1 3 0 2A F D4 F 80 11 F D6 2 B L DHXC B S R CNVHEX CO NVERT AN D T E S T CHARACTER
0 1 3 0 3A FD51 26 25 FD7 8 BNE CNVRTS RE T U RN IF NOT A NUMBER
0 1 3 0 4A F D5 3 C6 10 A LOB #16 PRE PARE S H I F'!,
0 13 0 5A FOSS 3D MUL BY FOUR P LAC E S
0 1 3 0 6A F DS 6 86 04 A LOA #4 ROTATE B I NARY I NTO VALU E
0 1307A F D5 8 58 BLDS H F AS L B OBTAI N N E X T � I T
0 1 3 0 8A FDS9 09 9C A ROL NUM B E R+ l I NTO LOW BYTE
0 1309A F DS B 09 9B A ROL NUMBER I NTO H I BYTE
0 1 3 10A FDSD 4A DECA COUNT DOW�
0 1 3 1 1A F DS E 26 F8 FD58 BNE BLDSHF BRANC H I F MORE TO DO
0 1 3 1 2A F D6 0 20 14 F D7 6 B RA CNVOK SET GOOD RET U RN CO DE
01314 ****************************************
0 13 1 5 * CONVERT ASC I I CHARACT ER TO B I NARY BYTE
01316 * I NP UT : A=AS C I I
0 1317 * O UTPUT : Z = l A=B I NARY VALUE
01318 * Z = O I F I NVAL I D
0 1319 * ALL REG I ST E RS TRAN S PARENT
8-60
PAG E 025 AS S I ST0 9 . SA : 0 AS S I ST0 9 - M C 6 8 0 9 MON I TOR
0 1320 * ( A UNALTERED I F I NVA L I D HEX )

0 1321 * * * * * * * * * * * * * * * * * * * * * * *- * * * * * * * * * * * * * *
0 1 3 2 2A F D6 2 81 30 A CNVHE X CMPA 1'0 ? LOW E R THAN A Z E RO
0 1323A FD64 25 12 FD78 BLO CNVRT S BRANCH NOT VALUE
0 1 3 2 4A F D6 6 81 39 A CMPA #'9 ? POS S I B LE A-F
0 1 3 2 5A F D6 8 2F OA F D7 4 BLE CNVGOT BRANCH NO TO ACCEPT
0 1 3 2 6A F D 6A 81 41 A CMPA # 'A ? LESS TH EN TEN
01327A FD6C 25 OA FD7 8 BLO CNVRTS RETURN I F . M I NUS ( I NVAL I D )
01328A FD6E 81 46 A CM P A I'F ? NOT TOO LARGE
0 1 3 2 9A F D7 0 22 06 FD7 8 BH I CNVRTS NO , RETURN TOO LARG E
0 1 3 3 0A F D7 2 80 07 A S U BA #7 DOWN TO B I NARY
0 1 3 3 1A F D7 4 84 OF A CN VGOT AN DA I$OF C LEAR H IGH H E X
0 1 3 3 2A F 07 6 lA 04 A CNVOK ORCC 14 FORC E Z E RO ON FOR VAL I D H E X
0 13 3 3A F D7 8 39 CNVRTS RTS RETURN TO CALLER
01335 * GET I N P U T CHAR , ABORT COMMAN D I F CONTROL-X ( C AN C E L )

0 1 3 3 6A F D7 9 3F READ SW I GET NEXT CHARAC TER
0 1337A F D7 A 00 A FCB I NCH N P F U NCT I O N
0 1 3 3 8A F 07 B 81 18 A CM PA I C AN ? ABORT CO M M A N D
0 1 3 3 9A F D7 D 27 C7 F046 BEQ B LDBAD BRANCH TO AB O RT I F SO
01340A F D7 F 39 RTS RETURN TO CALLER
01341 *0
01343 * * * * * * * * * * * * * * * GO - START PROGRAM EXECUTION

0 1 3 4 4 A F D8 0 8 0 01 F D8 3 CGO BSR GOADDR BU I L D ADDRE S S IF NEEDED
0 1 3 4 5 A F 08 2 3 8 R',I' I START EX E C UT I N G
01347 * F I N D OPT I ONAL N E W PROGRAM COUNTE R . ALSO A�� TH E

0 13 4 8 * B REAKPO I NTS .
01349A F D8 3 3 5 30 A GOA D DR PULS Y,X RECOVER RET U RN ADDRE S S
0 13 5 0A F 08 5 3 4 10 A PSHS X STORE RETURN BAC K
0 1 3 5 1A F D8 7 2 6 19 F DA2 BNE GON DF T I F N O CA RR I AG E RETURN TH E N NEW P C
01352 * DEFAULT PROGRAM COUNTE R , SO FALL T H RO UG H I F
0 13 5 3 * I MM E D I ATE BREAKPO I NT .
0 1 3 5 4A F 08 9 17 0186 FF42 L BS H C B K L DR SEARC H B RE AK PO I N T S
0 1 3 5 5A F D8 C AE 6C A LOX 12 , S LOAD PROGRAM COUNTER
0 13 5 6 A F D8 E SA ARMBLP D E C a COUNT DOWN
01357A F D8 F 2B 16 F DA 7 BMI ARM B K 2 DON E , NON E T O S I NGLE TRACE
01358A F D9 1 A6 30 A L DA - NU M BK P * 2 , Y P RE - F E T C H OPCODE
0 13 5 9A F D9 3 AC Al A CMPX , Y+ + ? I S TH I S A BREAK PO I NT
0 1360A F 09 5 26 F7 F 08 E BN E AR.'1BLP LOOP I F NOT
0 1 3 6 1A F 09 7 81 3F A CM P A t $ 3F ? SWI 8REAKPO I NT E O
0 1 3 6 2A F 09 9 26 02 F D9 0 BNE ARMN SW NO , S K I P SETT I NG OF PAS S F LAG
0 1 3 6 3A F D9 B 97 FB A S TA SW I BF L SHOW UP C OMM I NG SWI NOT BRKPNT
0 1 3 6 4A F D9 D O C 8F A ARMNSW INC M I S F LG F LAG TH RU A BREAK PO I NT
0 1 3 6 5A F D9 F 1 6 0 1 0 6 F EA 8 LBRA C DOT DO S I NGL E TRAC E WIO BREAK P O I NTS
01366 * O BT A I N NEW PROG RAM COUNT E R
013 6 7A F DA2 1 7 O O BB FE60 GO N D F T LBS R C D NU M OBTA I N NEW PROGRAM CO U NT E R
0 1368A F OA5 E D 6C A STO 12 ,S STORE I NTO STACK
01369A F OA7 1 7 019 8 FF4 2 A RM B K 2 LB S R C8K LDR OBTA I N TAB LE
0 1 3 7 0A F OAA 0 0 FA A NEG BK P',I'CT COMPLEMENT TO SHOW ARM E D
O 1 3 7 1A F OAC SA ARM LOP DE C B ? DON E
0 1 3 7 2A F OAD 2B C9 F 07 8 BM I CN V RT S RE'rU RN WH E N DONE
0 1 3 7 3 A F OAF A6 84 A LDA [ ,Y] LOAD OPCOOE
0 1 3 7 4 A F DB l A7 30 A STA -NUMBK P * 2 , Y STORE I NTO OPCODE TA B LE
8·61
PAGE 026 AS S I ST0 9 . SA : 0 · AS S I ST0 9 - MC 6 8 0 9 MON I TOR
0 1 3 7 5A F DB3 8 6 3F A LDA #$ 3F READY " SW I " O PCODE

0 1 3 7 6 A F D B 5 A7 Bl A STA [ , Y++ ) STORE AN D MOVE UP TAB LE
0 1 3 7 7 A F DB 7 2 0 F3 F DAC BRA ARMLOI? AN D CONT I NU E
0 1379 * * * * * * * * * * * * * * * * * * * CALL - CALL ADDRE S S AS SU B ROUT I N E

0 1 3 8 0A F D8 9 8D C8 F D8 3 CCALL BS R GOADDR FETCH ADDRE S S IF N E E D E D
0 1 3 8 1A F DB B 35 7F A P U LS U , Y , X , DP , D , CC RE S TORE U S E RS REG I ST E RS
0 1 3 8 2A F DB D AD Fl A JS R [ , S++ ) CALL US E R S U BROUT I N E
0 1 3 8 3A F DB F 3F CGOBRK SWI PE RFORM BREAK PO I NT
0 1 3 8 4A F OC O OA A FCB BRKPT FUNCT ION
0 1 3 8 5A FOCl 20 FC F DB F BRA CGOB RK LOOP UNT I L U S E R CHANGES PC
0 1387 * * * * * * * * * * * * * * * *MEMORY - D I S PLAY/CHANGE MEMORY

0 1388 * CMEMN AND CMPADP ARE D I RECT ENTRY PO I NTS F ROM
0 1389 * THE COMMAN D HAN D L ER FOR QU I C K COMMAN DS
0 1 3 9 0A F DC 3 17 0 0 9A F E 6 0 CMEM LBSR C DN U M OBTA I N ADDRE S S
0 1 3 9 1A F DC 6 DO 9E A CMEMN STD ADDR STORE DE FAULT
0 1 3 9 2A F DC 8 9E 9E A CM EM2 LOX AD DR LOAD PO I NT E R
0 1 3 9 3A F DCA 17 F C O C F 9 D9 LBS R ZOUT 2 H S E N D OUT H E X VALUE OF BYTE
0 1 3 9 4A FDCD 86 20 A LDA #'- LOAD DE L I M I T E R
0 1 3 9 5A F DCF 3F SW I S E N D OUT
0 1 3 9 6A F ODO 01 A FCB OUTC H FUNCT I O N
0 13 97A F DDl 17 F F O B F C DF CMEM4 LBS R BLDNNB OBTAI N NEW BYTE VALUE
0 1 3 9 8A F DD4 27 OA F DE O BEQ CME N U M BRANCH I F NUMBE R
0 1399 * COMA - S K I P BYTE
0 1400A F DD6 81 2C A ClI'lPA ii , ? COMMA
0 1 4 0 1A F DD 8 26 OE FDE8 BNE CMNOTC BRANCH NOT
0 1 4 0 2 A F DDA 9F 9E A STX AD D R U P DATE PO I NTER
0 1 4 0 3A F DDC 30 01 A L E AX 1 ,X TO NEXT BYT E
0 1 4 0 4 A F DOE 20 Fl F OOl B RA CMEM 4 AND IUPUT I T
0 1 4 0 5 A F OE O D6 9C A CMENUM L O B NUMBE R+ l LOAD LOW BYTE VALUE
0 1 4 0 6 A F DE 2 80 47 F E 2B BSR MUP DAT GO OVERLAY MEMORY B YT E
0 1 4 0 7 A F DE 4 81 2C A CMPA ii , ? CONT I NU E W I T H NO D I S P LAY
0 1 4 0 8 A F DE 6 27 E9 F OO l BEQ CM E M 4 BRANCH Y E S
0 14 0 9 * Q UOT E D ST R I NG
0 1 4 1 0 A F DE 8 8 1 27 A CMNOTC C(l:i PA I" ? QUOT E D ST R I N G
0 1 4 1 1 A F DEA 2 6 OC FDF8 BN E CMNO T Q BRANC H NO
0 1 4 1 2 A F DE C 8 0 8B FD79 C M E S T R BS R RE A D OBT A I N N E X T CHARACT E R
0 1 4 1 3 A F OE E 8 1 27 A ClI'l PA II I ? END OF QUOT E D STRING
0 1 4 1 4A F DF O 27 OC F DF E BEQ CM S P C E YES , QU I T S T R I NG MODE
0 14 1 5A F DF 2 1 F 89 A TF R A,B TO B FOR SU B ROUT I N E
0 1416A F DF 4 80 35 FE2 B BS R MUP DAT GO UPDAT E BYTE
0 1 4 1 7A FDF6 20 F4 F DEC BRA CM E S T R G E T N E X T CH ARACT E R
01418 * B L AN K - NEXT BYTE
0 1 4 1 9A FOF8 8 1 20 A CMNOTQ CMPA # $ 20 ? B LANK FOR NEX T BYTE
0 14 20A F D FA 2 6 06 FE0 2 BNE C M NO T B B RANCH NOT
0 1 4 2 1A F UFC 9 10" 9E A ST X AD D R U P DAT E PO I NT E R
0 1 4 2 2A F OF E 3F CMS P C E SW l G I VE S P AC E
0 1 4 2 3A F UF F 07 A FC B S P AC E F U N CT I O N
0 1 4 2 4A FEOO 20 C6 F OC S B RA CM E M 2 NOW PROMPT FOR NEXT
0 1425 * L I N E F E E D - NEXT BYTE W I T H ADDRE S S
0 1 4 2 6A FE0 2 81 01\ A CMNOT B CMPA I LF ? L I N E F E E D FOR NEXT BYTE
0 1 4 2 7 1\ F E 0 4 26 08 FEO t BNE CMNOTL BRANCH NO
0 1 4 2 8 1\ F E 0 6 86 00 A LDA tCR G I V E CARR I AG E RETU RN
8·62
PAGE 027 AS S I ST0 9 . SA : 0 ASS I ST0 9 - M C 6 8 0 9 MON I TOR
0 1 4 2 9A FE0 8 3 F SWI TO CONSOLE

0 14 3 0A FE0 9 01 A FCB OUTCH HANDLER
0 1 4 3 1A FEOA 9 F 9E A STX ADDR STORE NEXT ADDRESS
0 1 4 3 2A FEO C 2 0 OA FE18 B RA CMPADP BRAN CH TO SHOW
0 14 3 3 * U P ARROW - PREVIOUS BYTE AN D ADDRE S S
0 1 4 34A FE O E 81 5E A CMNOT L CMPA # '@ ? U P ARROW FOR PREV IOUS B YT E
0 14 3 5A FEI O 26 OA FEIC BNE CMNOTU BRAN CH NOT
0 1 4 3 6A FE1 2 30 lE A LEAX -2 , X DOWN TO PRE V I O U S BYTE
0 1437A FEl 4 9F 9E A STX ADDR STO RE NEW PO I NT E R
0 14 3 8A FE1 6 3F CMPADS SW I FORCE NEW L I N E
0 14 3 9A FE1 7 06 A FCB PCRLF FUNCT ION
0 1440A FE1 8 80 07 FE21 CMPP. DP BSR PRTADR GO P R I NT I 1'S VALUE
0 1 4 4 lA FE1A 20 AC F DC 8 BRA CMEM2 THEN PROMPT FOR I N PUT
0 14 4 2 * S LASH - NEXT BYTE W I TH ADDRE S S
0 1443A FEIC 8 1 2F A CMNOTU CMPA i'/ ? S LAS H FOR CURRENT D I S PLAY
0 1 4 4 4A FEIE 27 F6 FE1 6 BEQ CMPADS Y E S , S E N D ADDRE S S
0 1 4 4 5A FE2 0 3 9 RTS RE'rURN FROM COMfotAN D
0 1447 * P R I NT CURRENT ADDRE S S

0 14 4 8A FE 2 1 9E 9E A PRTADR LOX ADDR LOAD PO I NT E R VALU E
0 14 4 9A FE2 3 34 10 A PSHS X SAVE X · ON STACK
0 1 4 5 0A FE2 5 30 E4 A LEAX ,S PO I NT TO I T FOR D I S PLAY
0 1451A FE 2 7 3F SWI D I S PLAY PO I NTER I N HEX
0 1 4 5 2A FE2 8 05 A FCB OUT 4 H S F UNCT ION
0 1453A FE29 35 90 A PU LS Pc , x RECOVER PO I NT E R AN D RET U RN
01455 * U P DAT E BYTe

01456A FE2 B 9E 9E A MU P DAT LOX ADDR LOAD NEXT BYTE PO mTER
0 1457A FE 2 D E7 80 A STB , X+ STO RE AN D I NCRE M E N T X
0 1458A FE2 F El IF A CMPB -l , X ? S U C C E S F UL L STORE
0 1 4 59A FE 3 1 26 03 FE36 BNE MUPBA O BRAN C H FOR I ? ' I F NOT
01460A FE 3 3 9F 9E A STX ADDR STORE NEW PO I NT E R VALUE
0 1 4 6 1A FE 3 5 39 RTS BACK TO CALLE R
0 1 4 6 2A FE3 6 34 02 A MU P BAD PSHS A SAVE A REG I STER
0 1 4 6 3A FE38 86 3F A LOA Ii? SHOW I NVAL I D
0 1 4 6 4A FE3A 3F SWI S E N D OUT
0 1 4 6 SA FE 3 B 01 A FCB OUTCH F UNCT ION
0 14 6 6A FE3C 35 82 A PULS PC , A RETURN TO CALLER
0 1468 * * * * * * * * * * * * * * * * * * * * W I N DOW - SET W I N DOW VALUE

0 1 4 6 9 A FE 3 E 8 0 20 FE 6 0 CW I N DO BSR C DN U M OBTA I N w I N DOW VALUE
0 1 4 7 0 A FE4 0 DO AO A STD W I N DOW STORE IT I N
0 1 4 7 1A FE4 2 3 9 RTS END COMMAND
01473 * * * * * * * * * * * * * * * * * * D I S P LAY - H I GH S P E E D D I S P LAY ME M ORY

0 14 7 4A FE4 3 80 IB F E 6 0 CDI S P BS H CDNUM F E'rC H ADDRES S
0 1 4 7 SA FE 4 5 C4 FO A AN DB #$FO FORC E '1'0 1 6 BOUN DRY
0 1476A FE4 7 IF 02 A TF R D,Y SAVE I N Y
0 1477A FE 4 9 30 2F A LE AX 15 ,y DE FAULT LENGTH
0 1478A FE4 B 25 04 FE51 BCS C D I S PS BRANC H I F E N D OF I NPUT
0 14 7 9A FE4 D 80 11 FE60 BSR C DNU M OBTA I N COUNT
0 1480A FE4F 30 AB A LEAX D,Y AS S U M E COUNT , COMPUTE E N D ADDR
0 1 4 8 1A FE S 1 34 30 A C D I S PS PSHS Y,X SETUP PARAME T E RS FOR H S DATA
0 1 4 8 2A FE 5 3 l0A3 62 A CMPD 2,s ? WAS IT COU NT
B-63
PAGE 028 AS S I ST0 9 . SA : 0 AS S I ST0 9 - MC 6 8 0 9 MON ITOR
0 1 4 8 3A FES6 23 02 FESA B LS C DCNT BRAN CH Y E S

0 14 8 4A FES8 ED E4 A STD ,S STORE H I G H ADDRE S S
0 14 8 SA FESA AD 90 E184 CDCNT JSR [ VECTAB+ . H S DTA , PC R ] CALL PRI NT RO UT I NE
0 1486A FESE 35 EO A PULS PC , U , Y CLEAN STACK AN D E N D COMMAND
0 1488 * OBTA I N NUMBER - ABORT I F NON E

0 1489 * O N LY DEL I M I T E RS OF C R , BLANK , OR ' I ' ARE AC C E PT E D
0 1490 * OUTPUT : D=VALU E , C=l IF CARRIAGE RETURN DE LM I T E R ,
01491 * E L S E C= O
0 1 4 9 2A FE60 17 F E 7 E FC E I CDNUM LBS R BLDNUM OBT A I N NUM B E R
0 1 4 9 3A FE6 3 26 09 FE6E BNi:'! C DBADN BRANCH I F I NVAL I D
0 1 4 9 4A FE 6 S 81 2F A CMPA i'l ? VAL l O DE L I M I T E R
0 14 9 SA FE 6 7 22 05 FE6 E BHI C DBADN BRANCH I F NOT F O R ERROR
0 14 9 6A FE69 81 OE A CMPA # C R+ l LEAVE COMPARE FOR CARR I AGE RET
0 1 4 9 7A FE6B DC 9B A LDD NUM B E R LOAD NUM B E R
0 1498A FE6D 39 RTS RETURN W I T H COMPARE
0 1499A FE6E 16 FAE B F 9 S C C D BADN LBRA CMDBAD RETURN TO E RROR MECHAN I SM
0 1501 * * * * * * * * * * * * * * * * * P U NCH - PUNCH MEMORY I N S 1 - S 9 FORMAT

0 1 S 0 2A FEn 80 ED F E 6 0 C PUNCH BSR CDNUM OBTA I N START ADDRE S S
0 1 S 0 3A FE73 IF 02 A TFR D,Y SAVE I N Y
0 1 S 0 4A FE7 S 80 E9 FE60 BSH CDNU M OBTA I N E N D ADDRES S
0 1 S 0 SA FEn 6F E2 A CLR , -S SETU P PU N C H F UNCT ION CO DE
0 1S06A FE 7 9 34 26 A PSHS Y,D STORE VAL U E S ON STACK
0 1 S 0 7A FE7B AD 9 0 E1 6 5 CCALBS J S R [ VE CTAB+ . B SON , PC R ] I N I T I AL I Z E HANDLER
0 1S08A FE7F AD 90 E163 JSR [ VECTAB+ . BS DTA , PC R ] P E RFORM FUNCT I ON
0 1S 0 9A FE83 34 01 A PSIIS CC SAVE RETURN CODE
0 1S10A FE 8 S AD 9D E15F JSR [ VECTAB+ . B SOFF , PC R ] T U RN O F F HANDLER
0 1SHA FE89 35 01 A P U LS CC OBTA I N CON D I T ION CODE SAVED
0 1 S 1 2A FE8B 26 El FE6E BNE C D BADN BRANCH IF ERROR
0 I S 1 3A FE80 35 B2 A P U LS PC , y , X , A RETURN F ROM COMMAND
0 1515 * * * * * * * * * * * * * * * * * LOAD - LOAD MEMORY F ROM S 1 - S 9 FORMAT

0 1 S16A FE8F 80 01 F E 9 2 C LOAD BS R C LVOF S CALL SET U P AN D PAS S CO DE
0 1 S 17A FE91 01 A FCB 1 LOAD FUNCT I ON CO DE FOR PAC K ET
0 1 S 1 9A FE 9 2 33 Fl A CLVO F S LEAU [ , S++ ] LOAD CO D E IN HIGH BYTE OF U

0 1 S20A FE94 33 04 A LEAU [ ,U] NOT CHAN G I NG CC AND RESTORE S
0 1 S 2 1A FE9 6 27 03 FE 9 B BEQ C LVDFT BRANCH I F CARR I AG E RETURN N E XT
0 1 S 2 2A FE9S 80 C6 FE60 BSR CDNUM OBTA I N OF F S ET
0 1S 23A FE9A 8C A FCB SKIP2 S K I P DE FAULT OF F S ET
0 1S24A FE 9 B 4F C LVDFT CLRA CREATE Z E RO OF F S ET
0 1S 2 SA FE9C SF CLRB AS DEFAUL'f
0 1 S26A FE9D 34 4E A PSHS U , DP , D S E'fUP COD E , N U L L ·wORD , OF F S ET
0 1.S 2 7 A FE9F 20 DA FE7B BRA CCALBS ENTER CALL TO BS ROUT I NES
0 1529 * * * * * * * * * * * * * * * * * * V ER I F Y - COMPARE MEMORY WITH F I LE S

0 1 S 3 0 A FEAl 8 0 EF FE9 2 CVER BSR C LVO F S COMPUTE O F F S ET IF ANY
0 1 S 3 1 A FEA3 FF A FCB -1 VERI F Y FNCTN CO DE FOR PACK ET
8-64
PAGE 029 AS S I ST0 9 . SA : 0 AS S I ST0 9 - M C 6 8 0 9 MON I TOR
0 1533 * * * * * * * * * * * * * * * * * * * TRAC E - TRAC E I NSTRU CT IONS

0 1534 ******************* •
- S I NGLE ST E P TRAC E
0 1 5 3 5A FEA4 80 BA FE60 CTRAC E BSR CDNUM OBTA I N TRACE COU NT
0 1536A FEA6 DO 91 A STD TRAC EC STORE CO UNT
0 1537A FEA8 32 62 A COOT LEAS 2,S RI D COMMAN D RET U �� FROM STACK
0 1 5 3 8A FEAA EE Fa OA A CT RC E 3 LOU [lO ,S) LOAD OPCODE TO EX E C UTE
0 1 539A FEAD OF 99 A STU LASTOP STORE FOR TRAC E INTE RRU PT
0 1 540A FEAF DE F6 A LDU VECTAB+ . PTM LOAD PTM ADDRE S S
0 1 541A FEBl CC 0701 A LDD #7 ! <8+1 CYCLES ooWN + C Y C L E S U P
0 1 54 2A FEB4 ED 42 A STD PTMTMI - PTM , U START NM I T I MEOUT
0 1 5 4 3A FEB6 3B RT I RETURN FOR ONE I N S T RU CT ION
0 1545 * * * * * * * * * * * * * N U L LS SET NEW L I N E AN D CHAR PADD I NG

0 1 5 4 6 A FEB7 8 0 A7 F E 6 0 CNU LLS BSR CDN U M OBTA I N NEW L I N E PAD
0 1 5 4 7 A F E B 9 DO F2 A STD VECTAB+ . PAO RE SET VAL U E S
0 1 5 4 8 A FEBB 3 9 RTS END COMMAND
01550 * * * * * * * * * * * * * * * * * * STLEVEL - SET STACK TRAC E LEVEL

0 1 5 5 1A F E BC 27 OS FEC3 CST LEV BEQ STLDFT TAK E DE F AULT
0 1 5 5 2A FEBE 80 AO FE6 0 BSR CDN U M OBTA I N NEW STACK LEVEL
0 1 5 5 3A FECO DO Fa A STD SLEVEL STORE NEW E NT RY
0 15 54A FEC2 39 RTS TO COMMAND HAN D L E R
0 1555A FEC 3 30 6E A STLOFT LEAX 14 , S COMPUTE NMI COMPARE
0 1556A FEC 5 9F F8 A STX SLEVEL AN D STORE I T
0 1557A FEC7 39 RTS END COMMAN D
0 1559 * * * * * * * * * * * * * * * * * * OF F S ET - COMPUTE SHORT AND LONG

0 15 6 0 ** **************** B RANC H O F F S ETS
0 1 5 6 1A FEC S 8 0 96 FE60 COF F S BSR CDNUM OBTA I N I NSTRUCT I O N ADDRE SS
0 1 5 6 2A FECA I F 01 A TF R D,X U S E AS F ROM ADDRE S S
0 1 5 6 3A FECC 8 0 92 FE60 BS R CDNUM OBTA I N TO ADDRE S S
0 1564 * D=TO I N STRUCT I O N , X = F RO M I NSTRU CT I O N OF F SET BYT E ( S )
0 1565A FECE 30 01 A LEAX 1,X ADJ U S T FOR * + 2 SHORT BRANCH
0 1566A F E DO 34 30 A PSHS Y,X STORE WORK WORD AN D VALUE ON S
0 1567A FED2 A3 E4 A SUBD ,S F I N D OF F S ET
0 1568A F E D4 ED E4 A STD ,S SAVE O V ER STACK
0 1 569A F E D6 30 61 A LEAX 1 ,5 PO I NT FOR ONE BYTE D I S P LAY
0 1570A F E DS 10 SEX S I G N EXT E N D LOW BYTE
0 1 5 7 1A F E D9 Al E4 A CMPA ,S ? VAL I D ONE BYTE OF F S E T
0 1 5 7 2A FE DB 26 02 FEOF BNE COFNOl BRANCH I F NOT
0 1 s 7 3A FEDD 3F SW I SHOW ONE BYTE O P F S ET
0 1 s7 4A F E DE 04 A FCB OUT 2 HS F U NCT ION
0 1 s 7 sA F E DF EE E4 A COF NO l LOU ,S RE LOAD OF F S E T
01576A FEEl 33 SF A LEAU -l , U CONVERor TO LONG B RANCH OF F S E T
0 1577A FEE3 EF 84 A STU ,x STORE BACK WHE RE X PO I NTS NOW
0 1 s7 8 A FEES 3F SW I SHOW T'1l0 BYTE OF F S ET
0 1 s7 9 A FEE6 OS A FCB OUT 4 H S FUNCT ION
0 1s80A FEE7 3F SWI FORCE NEW L I N E
0 1 s8 1A FEES 06 A FCB PCRLF FUNCT ION
0 1 s 8 2A FEE9 35 96 A PULS PC , X , D RE STORE STACK AN D E N D COMMAN D
0 1583 *H
8-65
PAGE 030 AS S I ST0 9 . SA : 0 AS S I ST0 9 - M C 6 8 0 9 MON I TOR
01585 * * * * * * * * * * * * * BREAKPO I NT - D I S PLAY/E N T E �/DE LETE/CLEAR

01586 ************* BREAKPO I NTS
0 1 5 8 7A FEEB 27 23 F F 1 0 C B K PT BEQ CBK DS P BRANCH D I S P LAY OF J UST ' s '
0 1 5 8 8 A FEE D 17 FDFl F C E l LBS R BLDNUM ATT EMPT VALUE ENTRY
0 1 5 8 9A FEFO 27 2C FF1 E BEQ CBKADD BRANCH TO ADD I F SO
0 1 5 9 0A F E F 2 81 2D A CMPA #'- ? CORRECT DE L I M ITER
0 1 5 9 1A FEN 26 3F FF3 5 BNE CBKERR NO , BRANCH FOR ERROR
0 1 5 9 2A FEF 6 17 FDE8 FCE l LB S R BLDNUM ATTEMPT DE LETE VALUE
0 1 5 9 3A FEF 9 27 03 FEFE BEQ CBK OLE GOT ONE , GO DELETE IT
0 1 5 9 4A FEFB OF FA A CLR BK PTCT WAS ' B - ' , SO Z E RO COUNT
0 1 5 9 5A F E F O 39 CBKRTS RTS E N D COMMAN D
01596 * DELETE THE ENTRY
0 1 59 7 A FEFE 80 40 F F 4 0 CBK OLE BSR CBKSE'r SETU P REG I S 'r E �S AN D VAL U E
0 1 5 9 8A F F O O SA CBKOLP DECB ? ANY ENTR I E S I N TAB LE
0 1 59 9 A FFOl 2B 32 FF 3 5 BM I C B K E RR BRAN CH NO , E RROR
0 1 6 0 0 A FF 0 3 AC Al A CMPX , Y++ ? I S TH I S TH E ENTRY
0 1 6 0 1A F F 0 5 26 F9 FFO O BNE CBK DLP NO , TRY NEXT
01602 * F OU N D , NOW MOVE OTH E RS UP IN ITS PLACE
0 16 0 3A F F 0 7 AE Al A C B K DLM LOX , Y++ LOAD NEXT ONE U P
0 1 6 0 4 A FF 0 9 AF 3C A STX -4 , Y MOVE DOWN B Y ONE
0 1 6 0 5A FFOB SA DE C B ? DONE
0 1 6 0 6 A FF O C 2A F9 FF07 BPL CBKDLM NO , CONT I NU E MOVE
0 16 0 7 A F F O E OA FA A DEC BK PTC'l' DE CREMENT B REAK PO I NT COUNT
0 1 608A FF10 8D 2E FNO CBK OS P B S R CBKSET SETUP REG I S T E �S AN D LOAD VALUE
0 16 0 9 A FF 1 2 27 E9 FEFD BEQ CBKRT S RETURN IF NONE T O D I S PLY
0 1 6 1 0 A FF1 4 30 Al A C B K DSL LEAX , Y++ PO I NT TO N E XT ENTRY
0 1 6 1 1A F F 1 6 3F SW I D I S PLAY I N HEX
0 1 6 1 2A FF 1 7 05 A FCB OUT4 H S F U NCT ION
0 1 6 1 3A FF1 8 SA DEC B COUNT DOWN
0 1 6 1 4A FF 1 9 26 F9 FF14 BNE CBKDSL LOOP I F MORE TO DO
0 1 6 1 5 A FF 1 B 3F SW I SK I P TO NEW L I N E
0 16 1 6 A FF1C 06 A FCB PCRLF FUNCT ION
0 1 6 1 7 A FF 1 D 39 RT S RETU RN TO END COMMAN D
01618 * ADD NEW ENTRY
0 1 6 1 9A F F 1 E 80 20 F F 4 0 CBKADD BSR CBKSET SETUP REG I ST E RS
0 1 620A FF20 Cl 08 A CMPB #NUMBKP ? A LREADY FULL
0 1 6 2 1 A FF 2 2 27 11 FF3 5 BEQ C B K E RR BRAN CH ERRO R I F SO
0 1 6 2 2 A FF 2 4 A6 84 A LDA ,X LOAD BYTE TO TRAP
0 1 6 2 3 A FF 2 6 E7 84 A ST B ,X TRY TO CHANGE
0 1 6 2 4 A FF 2 8 El 84 A CMPB ,X ? C HANGAB LE RAM
0 1 6 2 5 A F F 2A 26 09 FF 3 5 BNE CBK ERR BRANCH EORROR IF NOT
0 1 6 26A FF2C A7 84 A STA ,X RE STORE BYTE
0 1 6 27A FF 2E SA CBKADL DE C B COUNT DOWN
0 1 6 2 8A FF 2 F 2B 07 FF38 BM I CBKADT BRANCH IF DON E 'ra ADD IT
0 1 6 2 9A FF 3 1 AC Al A CMPX , Y+ + ? ENTRY ALREADY HERE
0 1 6 3 0A FF 3 3 26 F9 FF2E BNE C BKADL LOOP I F NOT
0 1 6 3 1 A FF 3 5 16 F A 2 4 F 9 5 C CBKERR LBRA CM OBAD RETURN TO ERROR PRODUCE
0 1 6 32A FF 3 8 AF A4 A CBKADT STX ,Y ADD TH I S ENTRY
0 1 6 33A FF3A 6F 31 A C LR -NUMBK P * 2 + 1 , Y C LEAR OPT I ONAL BYTE
0 1 6 3 4A F F 3 C OC FA A INC BK PTCT ADD ONE TO COU NT
0 1 6 3 5 A FF 3 E 20 DO FF10 BRA CBKDSP AND NOW D i S PL�Y ALL OF ' EM
01636 * SETUP REG I ST E RS FOR SCAN
0 1 6 37A FF40 9E 9B A CBKSET LDX NU M B E R LOA D VALUE DE S I �E D
0 1 6 3 8A FF 4 2 31 8 D E0 6 C C B K LDR LEAY BK PTBL , PCR LOAD START OF TAB LE
0 1 6 3 9A F F 4 6 D6 FA A LDB BK PTCT LOAD ENTRY COUNT
0 1 6 4 0 A FF 4 8 39 RTS RETURN
8-66
PAGE 031 AS S I ST 0 9 . SA : 0 ASS I ST0 9 - MC 6 8 0 9 MON I 'fOR
01642 · · · · · · · · · · · · · · · · · ENCODE ENCODE A POSTBYTE

0 16 4 3A FF49 6F E2 A CENCDE CLR , -5 DE FAULT TO NOT I N D I RECT
0 1 6 4 4A FF4B SF CLRB Z E RO PO STBYTE VA L U E
0 16 4 SA FF4C 30 8C 3 F LE AX < C O N V1 , P C R START TAB L E S E ARC H
0 1646A FF 4 F 3F SW I OBTA I N F I RS T C H ARACT E R
0 1 6 4 7A FFSO 00 A FC B I NCHNP FUNCT ION
0 1 6 48A FF S l 81 SB A CM P A #' I ? I N D I RE C 'r H E HE
0 1 6 4 9A FF S 3 26 06 FFSB BNE CEN2 BRANCH I F" No'r
0 1 6 S0A FF S S 86 10 A LOA #$10 SET I N D I R E C T B I T ON
0 16S1A FF S7 A7 E4 A STA ,s SAVE FOR LAT F H
0 1 6 S2A FF S !:! 3F C E NG E T SW I O BTA I N N E X T C H A RA C T E R
016S3A FF SA 00 A FC B I N CH N P F U N CT I O N
0 1 6 S4A FFSB 81 00 A CEN 2 C M PA #CR ? END O F E N T RY
0 1 6 S SA FF S D 27 OC FF6B BEQ C E N Dl BRANCH YES
0 1 6 S6A FFSF 60 84 A C E N L P l TS'f ,X ? E N D OF TAB LE
0 1 6 S7A FF61 2B 02 FF 3 S BM I C B K E RR BRANCH ERROR I F SO
0 1 6 S8 A FF63 Al 81 A CMPA , X ++ ? TH I S TH E CH ARACT E H
0 16 S9A FF6S 26 F8 FFSF BNE CE N L P l BRANCH I F NOT
0 1 6 60A FF67 EB IF A ADDB -l , X ADD 'flU S VALUE
0 1 6 6 1A FF 6 9 20 EE F F S !:! BRA C E N GE 'f GET N E XT I N P U T
0 1 6 6 2A �' F 6 B 30 8C 4 9 CE N Dl LEAX < CONV2 , PC R PO I NT AT T AB L E 2
0 1663A FF6E IF 98 A TFH B ,A SAVE COpy I N A
0 1 6 6 4A FF70 84 60 A ANDA #$60 I SO LATE HEG I ST E R MAS K
0 1 6 6 SA FF72 AA E4 A ORA ,S ADD I N I N D I RE CT ION B IT
0 1 6 6 6A FF74 A7 E4 A STA ,S SAVE BACK AS POSTBYTE SKELETON
0 1667A FF 7 6 C4 9F A AN DB #$9F CLEAR REG I ST E R B ITS
0 1668A FF 7 8 60 84 A CENLP2 TST ,X ? E N D OF TAB LE
0 1669A FF 7A 27 B9 FF 3 5 BEQ CBKERR BHANCH E RROR I F SO
0 1 670A FF7C El 81 A CM P B , X ++ ? S AME VALUE
0 1 6 7 1A FF7E 26 F8 FF78 BNE CENLP2 LOOP I F NOT
0 1 6 7 2A FF80 E6 IF A LOB -l , X LOAD RE S U LT VAL U E
0 1 6 7 3A FF 8 2 EA E4 A ORB ,S ADD TO BAS E S K E L ETON
0 1 674A FF84 E7 E4 A STB ,S SAVE POSTBYT E O N STACK
0 1 675A FF86 30 E4 A LEAX ,S PO I NT TO I T
0 1 67 6A FF 8 8 3F SW I S E N D OUT AS HEX
0 1677A FF89 04 A FCB OUT 2HS F U N C T I ON
0 1678A FF8A 3F SW I TO NEXT L I NE
0 1679A FF8B 06 A FC B PC R L F F UNCT ION
0 1680A FF8C 35 84 A PULS PC , B END OF COMMAN D
01682 * TABLE ONE DE F I N E S VAL I D I N PUT I N SEQUENCE

0 1683A FF8E 41 A CONVl FCB ' A, $04 , ' B , $05 , ' D, $ 06 , ' H , $01
0 1 6 8 4A FF 9 6 48 A FCB ' H , $Ol , ' H , $Ol , ' H , $OO , ' , , $OO
0 1 685A FF 9 E 20 A FCB ' - , $0 9 , ' - , $01 , ' 5 , $7 0 , ' Y , $ 30
0 1686A FFA6 55 A FCB ' U , $ 50 , ' X , $10 , ' + , $0 7 , ' + , $01
0 1687A FFAE 50 A FCB ' P , $8 0 , ' C , $OO , ' R , $DO , ' ) , $0 0
0 1 6 8 8A FFB6 FF A FCB $FF E N D O F TABLE
0 1689 *CO N V2 U S E S ABOVE CO NVERS ION TO SET POSTBYTE
0 1690 * B I T S K E L ETON .
0 1 6 9 1A FFB 7 1084 A CONV 2 F OB $1084 , $1100 R, H ,R
0 1 6 9 2A FFBB 1288 A F OB $ 1 2 8 8 , $ 1 3 8 9 HH , R HHHH , R
0 1 6 9 3A FFBF 1486 A F DB $1486 , $1585 A,R B,R
0 1694A FFC 3 168B A F OB $1688 , $ 17 80 O, R , R+
0 1 6 9 5A FFC? 1881 A F OB $ 1 8 8 1 , $ 1 9 8 2 , R++ , -R
0 1696A FFCB lAS 3 A F OB $ 1A 8 3 , $ 8 2 8 C , --R HH , P C R
0 1697A FFCF 8380 A F OB $ 8 3 8 D , $ 0 3 9 F HHHH , PCR [ H HH H )
0 1698A FFD3 00 A FCB 0 E N D OF TABLE
B-67
PAGE 032 AS S I ST 0 9 . SA : 0 AS S I ST0 9 - MC 6 8 0 9 MON I TOR
0 1700 ****************************************************
0 1701 * DE FAULT I NTERRUPT TRANS F E RS *
0 1702 ****************************************************
0 1 703A F F D4 6E 90 DF EE RSRVD JMP [VECTAB+ . RSVD , PC R ) RE S E RVED VECTOR
0 1704A F F D8 6E 90 DFEC SW I 3 JMP [ VECTAB+ . SW I 3 , PC R ) SWI 3 VECTOR
0 1 705A F F DC 6E 90 DFEA SW I 2 JMP [ VECTAB+ . SW I 2 , PCR) SWI 2 VECTOR
0 1706A FFEO 6E 90 DF E S F I RQ JMP [ V ECTAB+ . F I RQ , PCR) F I RQ VECTOR
0 1 7 0 7A FFE4 6E 90 DF E 6 I RQ JMP [ V ECTAB+ . I RQ , PCR) I RQ VECTOR
0 1708A FFE8 6E 90 DF E4 Sill I JMP [ VECTAB+ . SW I , PCR] S W I VECTOR
0 1 7 0 9A FFEC 6E 90 DFE2 NMI JMP [ VECTAB+ . NM I , PCR ] NM I VECTOR
01711 * * * ***************************************************
0 1712 * ASS I S'f0 9 HA�DWARE VECTOR TABLE
0 1713 * TH I S TABLE I S U S E D IF TH E AS S I ST 0 9 ROM ADDRE S S E S
01714 * T H E MC 6 S 0 9 HARDWARE VECTORS .
0 1715 *** ***************************************************
0 1 7 1 6A FFF O ORG ROMBEG+ROMS I Z - 1 6 SETU P HARDWARE VECTORS
0 1 7 1 7A FFF O F F D4 A F OB RS RVD RES E RVED S LOT
0 1 7 1 8A FFF 2 F F DS A F OB SW I 3 SOFTWARE I NT E RRUPT 3
0 1 7 1 9A FFF 4 F F DC A F OB SWI 2 SOFTWARE I NT E RRUPT 2
0 17 20A FFF 6 FFEO A F OB F I RQ FAST I NT E RRU PT REQUEST
0 1 7 2 1A FF F 8 FFE4 A F OB I RQ INTE RRUPT REQUEST
0 1 7 2 2A FFFA FFES A F OB Sill I SOFTWARE I NT E RRU PT
0 1 7 23A FFFC FFEC A FOB NMI NON-MAS KAB LE I NTERRUPT
0 1 7 2 4A FFFE FS37 A F OB RESET RE START
01726 FS37 A END RE SET

TOTAL ERRORS 0 0 0 0 0 - - 0 0 0 0 0
TOTAL WARN I N G S 0 0 0 0 0 --0 0 0 0 0
002E . AC I A 00095*00S25 00837 00S53

0 000 • AVTBL 00072*00594
0024 • BS DTA 00090*01508
0 0 26 . BSO F F 00091*01510
0022 . S SON 000S9*01507
0016 . C I l)'f1\ 00083*00725
001S . C IOFF 00084*
0014 . C ION 00082*00348
0002 . CM D L 1 00073*00429
0 0 2C . CMDL2 000 9 4 * 0 0 4 3 2
001C . C O DTA 0 0 0 S G * 0 0 5 6 t1
0 0 lE: . COO F F 00087*
001A . COOt� 000S5*00349
0032 . EC H O 00097*00625
002A . E X P AN 00093*01224
0 0 0 1\ . F l �o. 00077*01706
0020 . lt S DTA 0 00 8 8 * 0 1 4 8 5
O OOC . UQ 0 0 0 7 1:1 * 0 1 7 0 7
0010 .NMI 000SO*01709
0 030 . P AD 00096* 00S57 00860 00977 00981 009a5 01025 01547
002S . P AU S E 000 9 2* 0 0 7 2 4
0034 • P'l'M 00098*00353 01540
B·68
PAGE 033 AS S I ST 0 9 . SA : 0 ASS I ST0 9 - MC 6 8 0 9 MON ITOR
0 0 1 2 . RESET 00081*
0 0 0 4 . RSVD 00074*01703
O O O E . SW I 00079*01708
0 0 0 8 . SW I 2 00076*01705
0 0 0 6 . SW I 3 00075*01704
E 0 0 8 AC IA 00024*00256
DF9E ADDR 00133*01239 01391 01392 01402 01421 01431 01437 01448 01456 01460
F DA7 ARMBK 2 00773 01357 01369*
F D8 E ARM B L P 01356*01360
F OAC ARM LOP 01371 *01 377
F 09 0 ARMNSW 01362 01364*
OF90 BAS E PG 00 1 3 5 * 0 0 1 8 6 0 0 7 8 4
0007 BELL 00 0 3 6 * 0 0 7 8 2
OFB2 BK PTBL 00127*01638
OFFA BK PTCT 00121*00386 01370 01594 01607 01634 01639
O FA 2 BK P'rO p 00129*
F81s BL02 001 9 2 * 0 0 1 9 6
F821 BL03 00198*00201
F 04 6 B LOBAD 012 8 8 * 0 1 3 3 9
F 04 D B LOH E X 01250 01301*
F D4 F BLOHXC 00421 0 1 3 0 2*
F 04 9 B LOH X I 01233 01299*
F C Olo' BLON N B 01164 01219*01397
F C E I BLONUM 01222*01286 01492 01588 01 592
F83s BLORTN 00205 00207*
F Os 8 BLDSHF 01307*01311
F800 BLDVTR 00183*00 218
O OOA BRKPT 00066*0 1384
FB6A BS OCMP 00942 00944*
FB70 BS OEOL 00940 00948*
FB40 BS DLD I 00919*00922 00949
FB42 BS DLD 2 00921*00928
FB60 BS DNXT 00939*00945
FB92 BSDPUN 00913 00977*
FB6E BSDSRT 00926 00946*00950
FB38 B S DTA 00250 00911*
FB27 B SO F F 00251 00891*
FB33 BSO F LP 00899 *00900
FBIB BSON 00249 00880*
FB22 BSON 2 00882 00884*
F BE F BS PEOF 01021 01033*
F BA 3 BS PGO 00987*01020
F BC 6 BS PMRE 01009*01011
F BAF BS POK 00990 00992*
F BE C BS PSTR 0 0 9 9 7 0 1 0 3 2*
FBE7 BS PUN 2 01003 01005 01006 01009 0 1 0 29 *
FBE9 BS PUN C 01017 01030*
FB75 BYTE 00930 00933 00935 00939 00953*
FB89 BYTH E X 00953 00956 00965*
F B8 8 BYTRT S 009 6 3 * 0 0 9 6 8
0018 CAN 00040 * 0 0 7 1 1 0 0 7 1 8 01338
FFlE CBKADD 01589 01619*
FF2E CBKA.DL 01627*01630
FF38 CBK A DT 01628 01632*
F E F !:: CBKDLE 01593 01597*
FF07 CBK DLM 01603*01606
FFOO CBKDLP 01598*01601
F Fl 4 CBKDSL 01610*01614
8-69
PAGE 034 ASS I ST0 9 . SA : 0 ASS I ST0 9 - M C 6 8 0 9 MON I TOR
FFI0 CBKDSP 01587 01608*01635

FF35 CBK E RR 01591 01599 01621 01625 01631*01657 01669
FF42 CBKLDR 00303 00383 01354 01369 01638*
F EEB CBKPT 0 0 50 3 0 1 5 8 7 *
F EF D CBK RTS 01595*01609
FF40 CBK S ET 01597 01608 0 1 6 19 01637*
FE7B CCA LBS 01507*01527
F DB 9 CCALL 00506 01380*
F E6 E C DBADN 01493 01495 01499*01512
F E5A C DCNT 01483 01485*
FE4 3 C DI S P 00509 01474*
FE51 C OI S PS 01478 01481*
FE60 C DN U M 01367 01390 01469 01474 01479 01492*01502 01504 01522 01535 01546
01552 01561 01563
F EA8 C OOT 00408 0136 5 01537*
F F 5B CEN 2 01649 01654*
FF49 C E N C DE 00512 016 4 3 *
F F 6B CEN D l 0 1 6 5 5 016 6 2*
F F 59 e ENG ET 01652*01661
FF5F CEN L P l 01656*01659
FF78 CENLP2 01668*01671
F D8 0 CGO 00515 01344*
F DBF CGO BRK 01383*01385
FA58 CHKABT 007 0 1 0070 9 * 0 0 7 6 4
FA61 CHKRTN 00710 00714*
FA60 CHKSEC 00713*00719
FA62 CH KWT 007 1 2 00715*00717
F A De C I DTA 00243 00825*
F AF O C IO F F 00244 00844*
F AE 6 C ION 0024 2 00835*
F AE 5 C I RTN 00828 00830*
FE8F C LOAD 00518 01516*
F E9 B C LVDFT 01 5 2 1 0 1 5 2 4 *
FE92 C LVOF S 01516 01519*01530
F8F7 CMD 00 3 5 4 0 0 3 8 0 * 0 0 4 39
F935 CM D 2 00415*00425
F948 CMD3 00422 00424*
F 95C CMOBAD 0 0 4 3 5 * 0 0 4 6 4 0 1 28 8 0 1 4 9 9 0 1 6 3 1
F 977 CMDCMP 00450 * 0 0 4 5 5
F901 CMDDDL 00387*00391
F 96C CMD F LS 00444*00453
F94D CMDGOT 00416 00427*
F 990 CMDMEM 00420 00463*
F8F9 CMDN E P 00383*00800
F 9 0A CM DNOL 00384 00388 00392*00462
F953 CM DSC H 00430*00434 00445
F96F CM DS I Z 00443 00446*
F 96 7 CMOSME 00431 00441*
F99B CMDT B 2 00254 00 4 9 6 *
F 99C CMOT B L 00233 00500*
F987 CMDXQT 00410 00413 00459*00467
F DC3 CMEM 00521 01390*
F DC 8 CMEM2 01392*01424 01441
F DO l CMEM4 0139 7 * 0 1 4 0 4 0 1 4 0 8
F DC6 CMEMN 00465 01391*
F DEO CMENUM 01398 01405*
F DEC CM E ST R 014 1 2 * 0 1 4 1 7
FE02 CMNOTB 01420 01426*
B·70
PAGE 035 ASS I ST 0 9 . SA : 0 ASS I ST0 9 - M C 6 8 0 9 MON I TOR
F OE 8 CMNOTC 0 1 4 0 1 0 1 4 1 0 *
FEOE CMNOTL 0 1 4 2 7 0 1 4 3 4 *
F OF 8 CMNOTQ 0 1 4 1 1 0 1 4 1 9 *
FE1C CMNOTU 0 1 4 3 5 0 1 4 4 3 *
F E1 8 CMPAOP 0 0 4 1 1 0 0 4 6 5 0 1 4 3 2 0 1 4 4 0 *
F E1 6 CMPADS 0 1 4 3 8 * 0 1 4 4 4
F OFE CM SPCE 0 1 4 1 4 0 1 4 2 2 *
F EB 7 CNULLS 0 0 5 2 4 0 1 5 4 6 *
F 07 4 CNVGOT 0 1 3 2 5 0 1 3 3 1 *
F 06 2 CNVHEX 0 0 9 6 7 0 1 3 0 2 0 1 3 2 2 *
F 07 6 C NVOK 0 1 3 1 2 0 1 3 3 2*
F 07 8 C NVRTS 0 1 2 8 7 0 1 3 0 3 0 1 3 2 3 0 1 3 2 7 0 1 3 2 9 01333*01372
F AF I COOTA 0 0 2 4 6 0 0 8 5 2 *
FBOF COOTAO 0 0 8 6 9 * 0 0 8 7 2
F B1 2 COOTAO 0 0 8 5 4 0 0 8 6 4 0 0 8 7 0 *
F B07 COOTLP 0 0 8 6 4 * 0 0 8 6 6
FB03 COOT P O 0 0 8 5 9 0 0 8 6 1 *
FBOO COOTRT 0 0 8 5 6 0 0 8 6 7 *
F EC 8 COFFS 00527 01561*
F E OF COFNOI 0 1 5 7 2 0 1 5 7 5 *
FF8E CONVI 01645 01683*
FFB7 CONV2 01662 01691*
F AF O COO F F 00247 008 45*
F AE 6 COON 00 2 4 5 0 0 8 3 6 *
FE71 CPUNCH 0 0 5 3 0 0 1 5 0 2 *
0000 CR 00038*00427 00621 00667 00858 01034 01166 01185 01428 01496 01654
F C 4A CRE G 00533 01102*
F EBC CSTLEV 0 0 5 3 6 0 1 5 5 1 *
F EA4 CTRACE 0 0 5 3 9 0 1 5 3 5 *
F EAA CTRC E 3 0 0 7 6 6 0 1 5 3 8 *
F EAl CVE R 00 5 4 2 0 1 5 3 0 *
FE3E CWI N OO 0 0 5 4 5 0 1 4 6 9 *
DF8E DE L I M 00153*00751 00757 01223 01236 01256
0 00 0 DFTCH P 0 0 0 2 6 * 0 0 2 5 7
0005 OFTNLP 0 0 0 2 7 * 0 0 2 5 7
0010 OLE 00039*00855
0004 EOT 000 3 5 * 0 0 3 4 3 00652 00684 00738 00782 01032 01034
F AB D ERRMSG 0 0 4 3 6 0 0 7 8 2 * 0 0 7 8 9
F AC E ERROR 0 0 3 1 4 0 0 7 8 9 *
F CE 9 EXPI 00253 01232*
F D0 7 EX P 2 01234 01250*01251
FD23 EX PADO 0 1 2 6 6 * 0 1 2 8 2
F 01 7 EX P C DL 0 1 2 5 2 0 1 2 6 0 * 0 1 2 6 9
F D2 B EXPCHM 0 1 2 6 2 0 1 2 7 0 *
F CE S EXPDL� 0 1 2 3 3 * 0 1 2 3 7
F D0 5 EXP RTN 0 1 2 4 8 * 0 1 2 5 7 0 1 2 7 5
F 03 6 EXPSUS 0 1 2 7 1 0 1 2 7 6 *
F OO D EXPTOI 0 1 2 5 4 * 0 1 2 7 3
F OO F EXPTDL 0 1 2 4 1 0 1 2 4 4 0 1 2 4 7 0 1 2 5 5 *
F D4 2 EXPTRM 0 1 2 6 3 0 1 2 7 6 0 1 2 8 6 *
FFEO F I RQ 01706 *01720
F ABC F I RQR 0 0 2 3 7 0 0 8 1 6 *
F 08 3 GOADDR 0 1 3 4 4 0 1 3 4 9 * 0 1 3 8 0
F DA2 GONDFT 0 1 3 5 1 0 1 3 6 7 *
0034 H I VT R 0 0 1 0 0 * 0 0 5 9 2
FCOO HSSLN K 0 1 0 4 6 * 0 1 0 4 9
FC47 HSDRTN 0 1 0 6 2 0 1 0 8 6 0 1 0 9 2 *
F BFC HS OTA 0 0 2 4 8 0 1 0 4 3 * 0 1 0 9 1
8-71
PAGE 036 AS S I S T 0 9 . S A a O AS S I ST0 9 - M C 6 8 0 9 MON ITUR
PC2 a HS H C H R
01076*01084
FC3 5 HSH COK 01079 0108 1 *
FC3 3 HSU ooT 01077 Ol0 8 0 *
rC1 4 HSH �NE 01060*01090
tC20 HSH NXT 0 1 0 6 8 * 0 1 0 7 1
FC0 6 HS HTT� 0 1 0 5 1 * 0 1 0 5 9
0000 INCHN P 0 0 0 5 6 * 0 0 9 2 0 0 0 9 2 4 00966 Ol 337 01647 01653
r844 I N ITVT 0 0 1 8 8 0 0 2 3 3 *
r870 INTVE 00197 00264*
F870 I NTVS 0 0 1 9 7 0 0 2 5 6 *
FFE4 I RQ 01707*0172l
F A D8 I RQR 00238 00808*
OF99 �ASTOP 001 39*00752 0 1 5 39
FAC 1 �OOP 00297 00740 00784*00809
O OOA �F 000 3 7 * 0 0 6 2 3 00638 00669 0 1 0 3 4 01426
OF8F MISF� 00151 * 0 0 4 0 2 0 0 6 1 9 0074l 00 7 7 2 00886 00897 01364
0 00 8 000 6 4 * 0 0 2 2 2
MON I T R
FA79 M S HOWP
007 3 8 * 0 0 7 4 8
F E3 6 MUPBAO 01459 014 6 2*
FE2B MU P DAT 0 1 4 0 6 0 1 4 1 6 0 1 4 5 6 *
F F EC NM I 01709*01723
FAB 7 NM I CON 0 0 7 4 2 0 0 7 7 2 *
F A7 0 NM I R 00240 00740*
F AB O NM I 'rRC 0 0 7 4 4 0 0 7 4 7 0 0 7 6 6 *
DF 9 B NUMB E R 0 0 1 3 7 * 0 0 4 0 1 0 0 4 6 6 0 1 1 7 9 01255 01260 01265 01267 01278 01299 01300
01308 01309 01405 01497 01637
0 0 0 8 NUMBKP 0 0 0 2 9 * 0 0 1 2 6 0 0 1 2 8 0 0 3 8 9 01358 01374 01620 01633
O O O B NUMF UN 0 0 0 6 8 * 0 0 3 1 3
0 0 1 B NUMVTR 0 0 0 9 9 * 0 0 1 2 4 0 0 1 9 0
0 0 0 4 OUT2 HS 0 0 0 6 0 * 0 1 0 6 9 0 1 1 5 6 0 1 5 7 4 01677
0 0 0 5 OUT 4 H S 0 0 0 6 1 * 0 0 7 5 4 0 1 0 6 5 0 1 1 5 3 01452 01579 01612
0 0 0 1 OUTCH 00057* 0 0 3 9 6 00885 00893 00896 00983 01082 01142 01146 01396 01430
01465
O O O B PAU S E 00 0 6 7 *
OFFC PAU S E R 00 1 1 7 * 0 0 2 5 2
O F 9 3 PCNTER 0 0 1 4 5 * 0 0 3 9 3 0 1 2 4 2
0 0 0 6 PCRLF 00062*00381 01044 01061 01093 01161 01439 01581 01616 01679
0 0 0 3 POATA 00 0 5 9 * 0 0 3 5 2 0 0 7 9 1 0 0 9 9 9 01023
0 0 0 2 POATA1 0 0 0 5 8 * 0 0 4 3 8 0 0 7 5 0
0 0 3 E PROMPT 00 0 2 8 * 0 0 3 9 4
F E 2 1 P RTA DR 0 1 4 4 0 0 1 4 4 8 *
OF 9 5 PSTACK 0 0 1 4 3 * 0 0 3 9 8 0 0 4 3 5
E O O O PTM 000 2 5 * 0 0 0 4 2 0 0 0 4 3 0 0 0 4 4 00045 00046 00047 00259 00355 00356 00358
00359 00 3 6 1 0 1 5 4 2
E O O O PTMC 1 3 0 0 0 4 3 * 0 0 3 5 9
E 0 0 1 PTMC2 00044 * 0 0 3 5 8 00361
E 0 0 1 PTMSTA 0 0 0 4 2 *
E 0 0 2 PTMTM l 0 0 0 4 5 * 0 0 3 5 5 0 0 3 5 6 0 1 5 4 2
E 0 0 4 PTMTM 2 0 0 0 4 6 *
E 0 0 6 PTMTM 3 0 0 0 4 7 *
E 7 0 0 RAMOFS 0 0 0 2 1 * 0 0 1 1 1
F 07 9 REA D 0 0 4 0 7 004 2 4 01258 0 1 3 0 1 01336*01412
F C 9 4 RE G 4 01157 *01176 01186
F CC 3 REGAGN 0 1 1 6 7 0 1 1 8 9 *
F C 7 0 RE(:C H 3 01 1 0 4 0 1 1 3 5 *
F C 9 0 REGCNG 0 1 1 4 9 0 1 1 6 4 *
F C 5 0 RE GMSK 0 1 1 2 3 * 0 1 1 3 7
F C B l REGNXC 0 1 1 6 5 0 1 1 7 7 *
8-72
PAG E 037 ASS I ST 0 9 . SA : 0 ASS I ST0 9 - MC 6 8 0 9 �1ON ITOR
FC78 REGP l 01138*01143 01159

FC81 REGP2 01140 01144*
FC92 REGP3 01151 01155*
FAS 3 REGPRS 00755 007 6 8 * 0 0 7 9 9
FC6F REGPRT 00768 01102 01134*
FC9S REGRTN 01162*01201
F CAA REGSKP 01172*01175
F CC 9 REGTF l 01191*01194
F C D6 REGTF 2 01197*01200
F CS B REGTWO 01181 01183 *
F837 RESET 00 2 1 7 * 0 0 2 4 1 0 1 7 2 4 0 1 7 2 6
F83D RESET2 00219*00223
FOOO ROM20F 00023*00202
DF6 6 ROM2WK 00155*
F800 ROMBEG 0 0 0 2 0 * 0 0 0 2 3 0 0 1 1 1 00 1 6 7 0 1 7 1 6
0 80 0 ROMS I Z 00022*00023 01716
F F D4 RSRVD 01703*01717
F A DS RSRVDR 00234 00809*
DF 9 7 RSTACK 00141*00345 00788
FABC RT I 00774*00816
FAF O RTS 00787 00841*00844 00845
F 9EC SEND 0056 8 * 0 0 6 2 4 00640 00668 00682
F8C9 S I GNON 00342*00350
008C SKIP2 00049*00863 01154 01220 01523
DFF 8 SLEVE L 00123*00746 01553 01556
0007 S PACE 00063*01047 01054 01056 01073 01173 01423
DF 5 1 STAC K 00158*00217
FEC3 STLDFT 01551 01555*
FFE8 SWI 01708*01722
F F DC SWI 2 01705*01719
F AD8 SWI 2 R 00236 00806*
F F D8 SWI 3 01704*01718
F AD8 SW I 3 R 00235 00807*
DFFB SWI BF L 00119*00301 00311 01363
DF90 SWI CNT 0 0 1 4 9 * 0 0 296 0 0 6 4 1 00743
F8B5 SWI DN E 00302 00306 00311*
F 8A 8 SWI LP 00305*00308
F895 SWI R 0 0 2 3 9 0 0 29 6 *
F87D SWI VTB 00283*00283 00284 00285 00286 00287 00288 00289 00290 00291 00292
0 0 29 3 0 0 2 9 4 0 0 3 17
DF 9 1 TRACE C 0 0 1 4 7 * 0 0 4 0 3 0 0 7 59 0 0 7 6 2 0 1 5 3 6
DF51 TSTACK 00157*01189
0009 VCTRSW 00065*
DFC 2 VECTAB 00125*00183 00348 00349 00353 00429 00432 00568 00594 00625 00724
00725 00825 00837 00853 00857 00860 00977 00981 00985 01025 01224
01485 01507 01508 01510 01540 01547 017 0 3 01704 01705 01706 01707
01708 017 0 9
DFAO WI N DOW 00131*01245 01470
DF O O WORKPG 00111*00112 00113
FA7 2 XQC I D'r 00612 00709 00716 00725*
FA6E XQPA U S 00611 00700 00715 00724*00869
F ADS Z B KCMD 00756 00758 00760 0076 3 00765 00800*
F AD 3 ZBK PNT 00293 00310 00799*00810
F A2 A Z I N2 00622 00625*
FAll Z I NCH 00283 00612*00615 00617
FAOF Z I N CH P 00611*00613
F8E6 Z MONT 2 00347 0 0 3 5 3*
F 8 D2 Z MONTR 0029 1 00345*
8-73
P AG E 038 ASS I ST0 9 . SA : 0 ASS I ST0 9 - M C 6 8 0 9 MON I TO R
F 9F2 Z OT2HS 00287 00571*

F9FO ZOT 4 H S 00288 00570*
FA2E Z OTCH1 00284 00636*
F A3 7 Z OTCH 2 00582 00640*
FA3 9 Z OTCH 3 00593 00598 00600 00620 00626 00641*00 7 0 4
F 9 D9 Z OUT2H 00 557*00570 0 0 5 7 1 0 1 0 3 0 01393
F 9 E6 Z OUTHX 00561 00564*01052
FA4E Z PAUSE 00294 00700*
FA3 D Z PCRLF 00289 00654*
FA3C Z PCRLS 00637 00652*00654
F A4 0 Z P DATA 00286 00667*
FA48 Z PDTA1 00285 00683*
FA4 6 Z P DTLP 006 39 00682*00685
F 9F6 Z S PACE 00290 00581*
F 9 FA ZVSWTH 00292 00591*
8-74
AP PEN DIX C
MAC H I N E CODE TO INSTRUCTION C ROSS REFEREN C E
C.1 I NTRO D U CT I O N
Thi s appendix contai ns a cross reference between the mach i ne code, represented i n hex
adeci mal and the i n struction and addressing mode that it represents. The n u m ber of
M PU cycles and the n u m ber of program bytes is a l so g iven . Refer to Table C-1 .
C-1
'o
Table C·1. M achine Code to Instruction Cross Reference
OP Mnem Mode I OP Mnem Mode # OP Mnem Mode I
r
00 N EG Dir ct 6 2 30 LEAX 4+ 2+ 60 N EG Indexed 6+ 2+
01 31 LEAY 4+ 2+ 61
02 32 LEAS 4+ 2+ 62
03 COM 6 2 33 LEAU Ind xed 4 + 2+ 63 COM 6+ 2+
04 LSR 6 2 34 PSHS I mmed 5 + 2 64 LS R 6+ 2+
�
05 35 PULS 5+ 2 65
06 ROR 6 . 2 36 PSHU 5+ 2 66 ROR 6+ 2+
07 ASR 6 2 37 PULU I mmed 5+ 2 67 ASR 6+ 2+
08 A S L, LSL 6 2 38 I nherent 68 ASL, LS L 6+ 2+
39 6+ 2+
I
09 ROL 6 2 RTS 5 69 ROL
OA DEC 6 2 3A ABX 3 6A DEC 6+ 2+
OB 3B RTI 6/ 1 5 1 6B
OC INC 6 2 3C CWAI 20 2 6C INC 6+ 2+
00 TST 6 2 3D MUL 11 1 60 TST 6+ 2+
OE JMP 3 2 3E 6E JM P 3+ 2+
OF CLR Direct 6 2 3F SWI Inherent 19 6F CLR Indexed 6+ 2+
10 Page 2 40 NEGA I nherent 2 70 N EG Extended 7 3

11 Page 3 41 71
12 NOP I nherent 2 42 72
13 SYNC Inherent 4 43 COMA 2 73 COM 7 3
14 44 LSRA 2 74 LS R 7 3
15 45 75
16 LBRA Relative 5 3 46 RORA 2 76 ROR 7 3
17 LBSR Relative 9 3 47 ASRA 2 n ASR 7 3
18 48 AS LA, LSLA 2 78 AS L, L S L 7 3
19 DAA I nherent 2 1 49 R O LA 2 79 ROL 7 3
lA ORCC Immed 3 2 4A DECA 2 7A DEC 7 3
lB 4B 7B
lC ANDCC Immed 3 2 4C I N CA 2 7C INC 7 3
10 S EX I nherent 2 1 40 TSTA 2 70 TST 7 3
lE EXG Immed 8 2 4E 7E JMP 4 3
lF TFR Immed 6 2 4F CLRA Inherent 2 7F CLR Extended 7 3
20 BRA Relative 3 2 50 NEGB Inherent 2 80 S U BA Immed 2 2

21 BRN 3 2 51 81 C M PA 2 2
22 BHI 3 2 52 82 S B CA 2 2
23 BLS 3 2 53 COMB 2 83 SUBD 4 3
24 B H S , BCC 3 2 54 LSRB 2 84 ANDA 2 2
25 B LO, BC5 3 2 55 85 BITA 2 2
26 BNE 3 2 56 RORB 2 86 LOA 2 2
27 B EQ 3 2 57 A5RB 2 87
28 BVC 3 2 58 A S L B , LSLB 2 sa EO R A 2 2
29 BVS 3 2 59 R O LB 2 89 ADCA 2 2
2A BPL 3 2 5A DECB 2 8A ORA 2 2
2B BMI 3 2 5B 8B ADDA 2 2
2C BGE 3 2 5C INCB 2 8C CMPX Immed 4 3
20 B LT 3 2 50 T5TB 2 80 B5R Relative 7 2
2E BGT 3 2 5E 8E LOX Immed 3 3
2F B LE Relative 3 2 5F CLRB I nherent 2 8F
LEG E N D :
- N umber o f M P U cycles ( less possible push pull or indexed-mode cycles)
I Number of program bytes
• Denotes unused opcode
C-2
Table C·1 . M achine Code to Instruction Cross Reference (Continued)
OP Mnem Mode # OP Mnem Mode # OP Mnem Mode #
90 S U BA Direct 4 2 CO SUBB I mmed 2 2
91 C M PA 4 2
r
Cl CMPB 2 2 Page 2 and 3 Machine
92 S B CA 4 2 C2 S B CB 2 2 Codes
93 S U BD 6 2 C3 ADDD 4 3
94 ANDA 4 2 C4 ANDB 2 2 1 021 LBRN R elative 5 4
95 BITA 4 2 C5 BITB I m med 2 2 1 022 LBHI 5(6) 4
96 LOA 4 2 C6 LOB 2 2
Immed 1 023 LBLS 5(6) 4
97 STA 4 2 C7 1 024 LBHS, LBCC 5(6) 4
98 EO R A 4 2 C8 EOR B 2 2 1 025 LBCS , L B LO 5(6) 4
99 ADCA 4 2 C9 ADCB 2 2 1 026 LBNE 5(6) 4
9A ORA 4 2 CA ORB 2 2 1 027 LBEQ 5(6) 4
9B ADDA 4 2 C t3 ADr 3 2 2 1 028 LBVC 5(6) 4
9C C M PX 6 2 CC LDD 3 3 1 029 LBVS 5(6) 4
90 JSR 7 2 CD 1 02A LBPL 5(6) 4
9E LOX 5 2 CE LOU 3
I mmed 3 1 02B LBMI 5(6) 4
9F STX D irect 5 2 CF 1 02C LBGE 5(6) 4
1 020 L B LT 5(6) 4
AO S U BA I n dexed 4+ 2+ DO SUBB Direct 4 2
1 02E LBGT 5(6) 4
Al
A2
C M PA
S B CA
4+
4+
2+
2+
01
02
CMPB
SBCB t 4
4
2
2
1 02F
l 03F
LBLE
SWI2
Relative
I n herent
5(6)
20
4
2
A3 S U BD 6+ 2+ 03 ADDD 6 2
1 083 CMPD I m med 5 4
A4 A N DA 4+ 2+ 04 ANDB 4 2
AS B ITA 4+ 2+ 05 BITB 4 2
l OSC CMPY I 5 4
l OSE LOY I m med 4 4
A6 LOA 4+ 2+ 06 LOB 4 2
1 093 C M P. D Direct 7 3
A7 STA 4+ 2+ 07 STB 4 2
i
1 09C CMPY 7 3
AS EO R A 4+ 2+ 08 EO R B 4 2
l09E LOY 6 3
A9 ADCA 4+ 2+ 09 ADCB 4 2
l 09 F STY Di ct 6 3
AA ORA 4+ 2+ DA ORB 4 2
1 0A3 CMPD I ndexed 7+ 3+
AB ADDA 4+ 2+ DB ADDB 4 2
�
1 0AC C M P Y 7+ 3+
AC C M PX 6+ 2+ DC LDD 5 2
2 1 0AE LOY 6+ 3+
AD JSR 7+ 2+ DO STD 5
l OAF STY I ndexed 6+ 3+
AE LOX 2+ DE LOU 5 2
5+
1 0B3 CMPD Extended 8 4
AF STX I ndexed 5+ 2+ OF STU Direct 5 2
: �
10BC C M P Y 4
EO SUBB Indexed 4+ 2+ l OB E LOY 4
BO S U BA Extended 5 3 El CMPB 4+ 2+ 10BF STY ExtenQed 7 4
Bl CMPA 5 3 E2 S B CB 4+ 2+ 1 0C E LOS I m med 4 4
B2 S B CA 5 3 E3 ADDD 6+ 2+ l OD E LOS Direct 6 3
B3 S U BO 7 3 E4 ANOB 4+ 2+ 1 0D F S T S Direct 6 3
B4 ANOA 5 3 E5 BITB 4+ 2+ 1 0EE LOS I n dexed 6+ 3+
B5 B ITA 5 3 E6 LOB 4+ 2+ 1 0EF STS I n dexed 6+ 3+
B6 LOA 5 3 E7 STB 4+ 2+ 1 0FE LOS Extended 7 4
B7 STA 5 3 E8 EO R B 4+ 2+ 1 0FF STS Extended 7 4
B8 EORA 5 3 E9 AOCB 4+ 2+ 1 1 3F SWI3 I n herent 20 2
B9 AOCA 5 3 EA ORB 4+ 2+ 1 1 83 CMPU I mmed 5 4
BA ORA 5 3 EB AOOB 4+ 2+ 1 1 8C CMPS I m med 5 4
BB ADOA 5 3 EC LDD 5+ 2+ 1 1 93 CMPU Direct 7 3
BC CMPX 7 3 ED STO 5+ 2+ 1 1 9C CMPS Direct 7 3
BD JSR 8 3 EE LOU 5+ 2+ l 1 A3 CMPU I ndexed 7+ 3+
BE LOX 6 3 EF STU Indexed 5+ 2+ 1 1 AC C M P S I ndexed 7+ 3+
BF STX Extended 6 3 l l B3 CMPU Extended 8 4
FO SUBB Extended 5 3
l l BC CMPS Extended 8 4
Fl CMPB 5 3
F2 SBCB 5 3
F3 ADOO 7 3
F4 ANOB 5 3
F5 BITB 5 3
F6 LOB 5 3
F7 STB 5 3
NOTE: All u n used opcodes a re both u ndefined F8 EO R B 5 3

F9 AOCB 5 3
and i llegal
FA ORB 5 3
FB ADOB Extended 5 3
FC LDD Extended 6 3
t
FD STO 3
FE
FF
LOU
STU Extended 6
� 3
3
C-3/C-4
AP PEN DIX D
P ROG RAM M I N G AI D
D.1 I NTRO DUCTION
'
This appendix contains a com p i l ation of data th at w i l l assist you i n p rogramm i ng the
M6809 processor. Refer to Table 0-1 .
Table D·1 . Program ming Aid
Branch InsbUcdons
Addreaing Addressing
Mode Mode
Relative 5 3 2 1 0 aIati\ 5 3 2 1 0
IllSIrUction Forms OP - , Description H N Z V C Instruction Forms OP - , Description H N Z V C
BCC BCC 24 3" 2 Branch C - O • • • · • BLS BLS 23 3 2 Branch Lower • • • · •
lBCC 10 5(6) 4 Long B ranch • • • • · or Same

24 c=o L B LS 10 5(6) 4 Long B ranch Lower · • · · ·
BCS BCS 25 3 2 Branch C = 1 • · • • • 23 or Same

lBCS 10 5(6) 4 Long B ranch • • · • · BLT B LT 20 3 2 B ranch < Zero · · · · ·
25 C= 1 L B LT 10 5(6) 4 Long B ranch < Zero · · · • •
BEC BEC 27 3 2 B ranch Z = O • • · · • 20

LBEC 10 5(6) 4 Long B ranch • • · · • BMI BMI 2B 3 2 B ranch Minus · • · • ·
27 Z=O LBMI 10 5(6) 4 Long B ranch M inus · · · · ·
BGE BGE 2C 3 2 Branch � Zero · • • • · 2B

LBGE 10 5(6) 4 Long B ranch � Zero • · • · • BNE BNE 26 3 2 B ranch Z .. O · · • • ·
2C LBNE 10 5(6) 4 Long Branch · · • · ·
BGT BGT 2E 3 2 B ranch > Zero · • • • • 26 Z .. O

lBGT 10 5(6) 4 Long B ranch > Zero • · • • · BPL BPL 2A � '! B ranch Plus • • · • •
2E LBPL 10 5(6) 4 Long B ranch Plus · · · · ·
BHI BHI 22 3 2 B ranc�, nigher • • • · • 2A

LBHI 10 5(6) 4 Long B ranch H ig her • • • · • BRA BRA 20 3 2 B ranch Always • • • • •
22 lBRA 16 5 3 Long Branch Always • • · · ·
BHS BHS 24 3 2 Branch H igher • • • · • BRN BRN 21 3 2 B ranch Never · · · • ·
or Same LBRN 10 5 4 Long B ranch Never · • • • ·
lBHS 10 5(6) 4 Long B ranch Higher • • • · • 21

24 or Same BSR BSR 80 7 2 B ranch to S ubroutine • · · · •
BLE B lE 2F 3 2 B ranch s Zero • • • · • lBSR 17 9 3 Long Branch to · · · • ·
lBlE 10 5(6) 4 Long B ranch s Zero • • • • • S ubroutine

2F BVe BVe 28 3 2 Branch V = O · • • • ·
BlO B LO 25 3 2 B ranch lower • • • · • LBVC 10 5(6) 4 Long B ranch · · • • •
L B lO 10 5(6) 4 Long B ranch lower · • • · •

28 V=O
25 BVS BVS 29 3 2 B ranch V - I • · • • •
lBVS. 10 5(6) 4 Long B ranch • • · · •
29 V= I
0-1
Table D·1. Programming Aid (Continued)
SIMPLE BRANCHES
OP , SIMPLE CONDITIONAL BRANCHES ( Notes 1 -41
BRA 20 3 2 Test True OP False OP
lBRA 16 5 3 N=l BMI 2B BPl 2A
BRN 21 3 2 Z= l B EQ 27 BNE 26
lBRN 1 021 5 4 V= l BVS 29 BVC 28
BSR 80 7 2 C=l BCS 25 BCC 24
lB S R 17 9 3
SIGNED CONDITIONAL BRANCHES (Notes 1 -41 UNSIGNED CONDITIONAL BRANCHES ( Notes 1 -41
Test True OP False OP Test True OP False OP
r> m BGT 2E BlE 2F r> m BHI 22 BlS 23
r�m BGE 2C B lT 20 r� m BHS 24 B lO 25
r=m BEQ 27 BNE 26 r=m B EQ 27 BNE 26
rs m BlE 2F BGT 2E r :s m BlS 23 BHI 22
r< m B lT 20 BGE 2C r< m B lO 25 BHS 24
N otes:
1. All conditional branches have both short and long variations.
2. All short branches a re 2 bytes and require 3 cycles.
3. All conditional long branches are formed by prefixing the short branch opcode with $ 1 0 and uSing a 1 6-bit destination offset.
4. All conditional long branches require 4 bytes and 6 cycles if the branch is taken or 5 cycles if the branch is not taken .
0·2
Table D·1 . Programming Aid (Continued)
Addressi ng Modes
Immediate Direct Indexed Extended Inherent 5 3 2 1 0
Instruction Forms Op - # Op - # Op - I Op - I Op - I Description H N Z V C
ABX 3A 3 1 B + X - X ( U nSigned ) • • • • •
AD C ADCA B9 2 2 99 4 2 A9 4+ 2+ B9 5 3 A + M + C- A I I I I I
A DC B C9 2 2 D9 4 2 E9 4+ 2+ F9 5 3 B + M + C- B I I I I I
ADD ADDA 8B 2 2 9B 4 2 A8 4+ 2+ BB 5 3 A+ M-A I I I I I
ADDB CB 2 2 DB 4 2 EB 4+ 2+ FB 5 3 B + M- B I I I I I
ADD D C3 4 3 D3 6 2 E3 6+ 2+ F3 7 3 D + M:M + 1 - D • I I I I
AN D ANDA B4 2 2 94 4 2 A4 4+ 2+ B4 5 3 AA M-A • I I 0 •
ANDB C4 2 2 D4 4 2 E4 4+ 2+ F4 5 3 B A M-B • I I 0 •
ASL
A N D CC
A S LA
ASLB
1C 3 2
48
58
2
2
1
1
A
B
} [H 1 1 1 1 1 1 1 f.- o
CC A I M M - C C
+- 8
8
I
I
I
I
I
I
7
I
I
�
ASL 08 6 2 68 6+ 2+ 78 7 3 M c b7 bO 8 I I I I
ASR ASRB 47 2 1 •
�} I I I I I I I�
A ----. 8 I I I
ASR 57 2 1 8 I I • I
ASR 07 6 2 67 6+ 2+ 77 7 3 7 bo c 8 I I • I
BIT B I TA 85 2 2 95 4 2 A5 4+ 2+ B5 5 3 8 i t Test A ( M A A ) • I I 0 •
BITB C5 2 2 D!: 4 2 E5 4 + 2+ F5 5 3 B i t Te�t B 1 M A Bi • I I 0 •
CLR CLRA 4F 2 1 O- A • 0 1 0 0
C LR B 5F 2 1 O- B • 0 1 0 0
CLR OF 6 2 6F 6+ 2+ 7F 7 3 O- M • 0 1 0 0
CMP CMPA 81 2 2 91 4 2 A1 4+ 2+ B1 5 3 Compare M from A 8 I I I I
CMPB C1 2 2 D1 4 2 E1 4+ 2+ F1 5 3 Compare M from B 8 I I I I
CMPD 10 5 4 10 7 3 10 7+ 3+ 10 8 4 Compare M : M + 1 from D • I I I I
83 93 A3 B3
CMPS 11 5 4 11 7 3 11 7+ 3+ 11 8 4 Compare M : M + 1 from S • I I I I
8C 9C AC BC
CMPU 11 5 4 11 7 3 11 7+ 3+ 11 8 4 Compare M : M + 1 from U • I I I I
83 93 A3 B3
CMPX 8C 4 3 9C 6 2 AC 6+ 2+ BC 7 3 Compare M : M + 1 from X • I I I I
CMPY 10 5 4 10 7 3 10 7+ 3+ 10 8 4 Compare M : M + 1 from Y • I I I I
8C 9C AC BC
COM COMA 43 2 1 A- A • I I 0 1
COMB 53 2 1 B- B • I I 0 1
COM 03 6 2 63 6+ 2+ 73 7 3 M- M • I I 0 1
CW A I 3C � 2 CC A I M M - C C Wait for I n terrupt 7
DAA 19 2 1 Decimal Adjust A • I I 0 I
DEC DECA 4A 2 1 A- 1-A • I I I •
DECB 5A 2 1 B- 1-B • I I I •
DEC OA 6 2 6A 6+ 2+ 7 4. 7 3 . M- 1-M • I I I •
EOR EORA 88 2 2 98 4 2 A8 4+ 2+ B8 5 3 A ¥- M - A • I I 0 •
EO R B C8 2 2 DB 4 2 E8 4+ 2+ F8 5 3 B J,l- M - B • I I 0 •
EXG R 1 . R2 1E 8 2 R 1 - R 22 • • • • •
INC INCA 4C 2 1 A+ 1-A • I I I •

INCB 5C 2 1 B+ 1-B • I I I •
INC OC 6 2 6C 6+ 2+ 7C 7 3 M+ 1-M • I I I •
JMP OE 3 2 6E 3+ 2+ 7E 4 3 EA J - PC • • • • •
JSR 9D 7 2 AD 7+ 2+ BD 8 3 J u m p to S u broutine • • • • •
LD LDA 86 2 2 96 4 2 A6 4+ 2+ B6 5 3 M-A • I I 0 •
LDB C6 2 2 D6 4 2 E6 4+ 2+ F6 5 3 M- B • I I 0 •
LDD CC 3 3 DC 5 2 EC 5+ 2+ FC 6 3 M:M + 1 - D • I I 0 •
LDS 10 4 4 10 6 3 10 6+ 3+ 10 7 4 M:M + 1-S • I I 0 •
CE DE EE FE
LDU CE 3 3 DE 5 2 EE 5+ 2+ FE 6 3 M:M + 1 - U • I I 0 •
LDX BE 3 3 9E 5 2 AE 5+ 2+ BE 6 3 M:M + 1 - X • I I 0 •
LDY 10 4 4 10 6 3 10 6+ 3+ 10 7 4 M:M + 1 - Y • I I 0 •
8E 9E AE BE
LEA LEAS 32 4+ 2+ EA3 _ S • • • • •
LEAU 33 4+ 2+ EA 3 _ U • • • • •
LEAX 30 4+ 2+ EA3 _ X • • I • •
LEAY 31 4+ 2+ E A3 _ y • • I • •
Legend : M Complement of M Test and set if true, cleared otherwise

OP Operation Code ( H exadeci mal) Transfer I nto • Not Affected
N umber of MPU Cycles H Half-carry (from bit 3) CC Condition Code R egister
# N umber of Program Bytes N Negative (sign bit) Concatenation
+ Arithmetic Plus Z Zero ( R eset) V Logical or
Arithmetic Minus V Overflow, 2's complement A Log ical and
• M u ltiply C Garry from ALU ¥- Logical Exclusive or
0 ·3
Table D·1 . Programming Aid (Continued)
Addressing Modes
I mmediate Direct Indexed1 Extended Inherent 5 3 2 1 0
Instruction Forms Op -
, Op -
, Op -
, Op -
I Op -
, Description H N Z V C
�}[H I I I I I I I �
LSL LSLA 48 A ....---
2 1 • I I I I
LSLB 58 2 1 O • I I I I
LSL 08 6 2 68 6+ 2+ 78 7 3 c b7 b() • I I I I
LSR LSRA
LSRB
LS R 04 6 2 64 6+ 2+ 74 3
44
54
2
2
1
1 �} -+/ I I I I I I I f-t{]
0
b7 bO c
•
•
•
b
0
0
I
I
I
•
•
•
I
I
I
MUL 3D 11 1 A x B - D ( U nSigned) • • I • 9
NEG N EG A 40 2 1 A+ 1-A 8 I I I I
NEGB 50 2 1 B+ 1 - B 8 I I I I
NEG 00 6 2 60 6+ 2+ 70 7 3 M+ 1-M 8 I I I I
NOP 12 2 1 N o O pera t i o n • • • • •
OR ORA 8A 2 2 9A 4 2 AA 4 + 2+ BA 5 3 A V M-A • I I 0 •
ORB CA 2 2 DA 4 2 EA + l+ FA 5 3 B V M-B • I I 0 •
ORCC 1A 3 2 CC V I M M - CC 7
PSH PSHS 34 5 + 4 2 P ush Registers on S Stack • • • • •
PSHU 36 5 + 4 2 Push Registers on U S taCk • • • • •
PUL PULS 35 5 + 4 2 Pull Registers from S S tack • • • • •

P U LU 37 5 + 4 2 P u l l Registers from U S tack • • • • •
�}4HI I I I I I I P
ROL R O LA 49 2 1 • I I I I
ROLB 59 2 1 • I I I I
ROL 09 6 2 69 6+ 2+ 79 7 3 c b7 b() • I I I I
ROR RORA
RORB
ROR 06 6 2 66 6+ 2+ 76 7 3
46
56
2
2
1
1 �} 4}+j I I I I I I I P
c b7 b()
•
•
•
I
I
I
I
I
I
•
•
•
I
I
I
RTI 3B 6m 1 Return From I n terrupt 7
RTS 39 5 1 Return from S ubroutine • • • • •
SBC S B CA 82 2 2 92 4 2 A2 4+ 2+ B2 5 3 A - M - C- A 8 I I I I
SBCB C2 2 2 02 4 2 E2 4+ 2+ F2 5 3 B - M - C- B 8 I I I I
S EX 1D 2 1 Sig n Extend B into A • I I 0 •
ST STA 97 4 2 A7 4+ 2+ B7 5 3 A-M • I I 0 •
STB 07 4 2 E7 4+ 2+ F7 5 3 B-M • I I 0 •
STD DO 5 2 ED 5+ 2+ FD 6 3 0-M:M + 1 • I I 0 •
STS 10 6 3 10 6+ 3+ 10 7 4 S-M:M + 1 • I I 0 •
OF EF FF
STU OF 5 2 EF 5+ 2+ FF 6 3 U-M:M + 1 • I I 0 •
STX 9F 5 2 AF 5+ 2+ BF 6 3 X-M:M + 1 I . I I 0 •
STY 10 6 3 10 10 7 4 Y-M:M + 1 • I I 0 •
9F AF 6+ 3+ BF
SUB SUBA 80 2 2 90 4 2 AO 4+ 2+ SO 5 3 A- M-A 8 I I I I
SUBB CO 2 2 DO 4 2 EO 4 + 2+ FO 5 3 B - M- B 8 I I I I
SUBD 83 4 3 93 6 2 A3 6 + 2+ B3 7 3 0 - M:M + 1 - D • I I I I
SWI SWl o 3F 19 1 Software I n terrupt 1 • • • • •
SWI26 10 20 2 Software I nterrupt 2 • • • • •

3F
SWI36 11 20 1 SoftwC!re I nterrupt 3 • • • • •
3F
SYNC 13 �4 1 Syn c hronize to Interrupt • • • • •
T FR 1F 2 :.! • • • • •
R 1 , R2 6 R 1 - R2
TST T STA 40 2 1 Test A • I I 0 •
TSTB 5D 2 1 Test B • I I 0 •
T ST OD 6 2 6D 6+ 2+ 70 7 3 Test M • I I 0 •
Notes:
1. This column g ives a base cycle and byte count. To obtain total count, add the values obtained from the I N D EX E D A D D R E S S I N G M O D E table,
in Appendix F.
2. R 1 and R 2 may be any pair of 8 bit or any pair of 16 bit reg isters.
The 8 bit reg isters are: A, B, C C , D P
T h e 1 6 b i t reg isters are: X , Y , U , S , D ,P C
3. E A i s the effective address.
4. The P S H and P U L i nstructions req u i re 5 cycles plus 1 cycle for each byte pushed or pulled.
5. 5(6) means: 5 cycles if branch not taken , 6 cycles if taken ( B ranch instructions) .
6. SWI sets I and F bits. SWI2 and SWI3 do not affect I and F .
7. Conditions Codes set as a direct result o f t h e instruction .
8. Value of half-carry fla g is undefined .
9. S pecial Case - Carry set if b7 is S ET .
0·4
AP PEN DIX E
ASCII C H ARACTER SET
E.1 I NTRO D U CT I O N
Th is appendix contain s the standard 1 1 2 character ASCII character set (7-bit code).
E.2 CHARACTER REPRESENTAT I O N A N D CODE I DENTI FICATION
The ASC I I character set is g iven in F i g u re E-1 .
�
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
Sir. b6 b6 0 1 0 1 0 1 0 1
.b4 b3 b2 b1 ...... Column 0 1 2 3 4 5 6 7
I , , I RoW Hex 0 1 2 3 4 5 6 7
0 0 0 0 0 0 NUL OLE SP 0
.
@ P p
0 0 0 1 1 1 SOH DCl I 1 A 0 a q
1
..
0 0 0 2 2 S TX DC2 2 B R b r
0 0 1 1 3 3 ETX DC3 , 3 C S c s
0 1 0 0 4 4 EOT DC4 $ 4 0 T d t
0 1 0 1 5 5 ENO NAK % 5 E U e u
0 1 1 0 6 6 ACK SYN & 6 F V f v
1 1 7 7
·
0 1 BEL ETB 7 G W 9 w
1 0 0 0 8 8 BS CAN ( 8 H X h x
1 0 0 1 9 9 HT EM ) 9 I Y i y
1 0 1 0 10 A LF SUB J j
·
Z Z
1 U 1 1 11 Ii VT ESC + ; K [ Ie I
1 1 0 0 12 C FF FS · < L \ I I
1 1 0 1 13 0 CR GS - = M 1 m J
1 1 1 0 14 E SO RS .> N " n -
1 1 1 1 15 F SI US / ? 0 0 DEL
Figure E·1 . ASCI I Character Set
E-1
Each 7-bit character i s represented with bit seven as the h i gh-order bit and bit one as the
low-order bit as shown i n the fol low ing exam ple:
b7 b6 b5 b4 b3 b2 b1 bO
1 0 0 0 0 0 0 1
The bit representation for the character "A" is d eve loped f rom the bit pattern for bits
seven through five found above the col umn des i g n ated 4 and the bit pattern for bits fou r
through one found t o the l eft of t h e row des i g n ated 1 .
A hexadec i m a l notat ion is commonly used to i nd i cate the code for each character. Th i s
i s easily developed b y assu m i ng a log i c zero i n t h e non-exi stant bit eight position f o r t h e
col u m n n u m bers and u s i n g t h e hexadecimal n u m ber for the row n u m bers.
E.3 CONTROL C HARACTERS
The characters located in col umns zero and one of Fig ure E-1 are considered control
characters. By defi n i tion , these are characters whose occ u rrance i n a particular context
i n it i ates, mod i fies, or stops an action that affects the record i n g , processi n g , t ran s m i s
sion, or i nterpretation of data. Table E-1 provides the mean i ngs of the control characters.
Table E·1 . Control Characters
Mnemonic Meaning Mnemonic Meaning

NUL Null OLE Data Link Escape
SOH Start of Heading DC1 Device Control 1
STX Start of Text DC2 Device Control 2
ETX End of Text DC3 Device Control 3
EOT End of Transmission DC4 Device Control 4
ENO Enquiry NAK • Negative Acknowledge
ACK Acknowledge SYN Synchronous Idle
BEL Bell ETB End of TransmiSSion Block
BS Backspace CAN Cancel
HT Horizontal Tabulation EM End of Medium
LF Line Feed SUB S u bstitute
VT Vertical Tabulation ESC Escape
FF Form Feed FS File Separator
CR carriage Return GS G roup Separator
SO Shift Out RS Record Separator
SI Shift I n US U nit Separator
DEL Delete
E.4 G RA P H I C C H A RACTERS
The characters in co l u mns two through seven are considered graphic characters. These
characters have a visual representat ion which is normal ly d i s p l ayed or pri nted . These
characters and their names are g iven in Table E-2.
E-2
Table E·2. Graphic Characters
Symbol Name
SP S pace ( Normally Nonprinting)
Exclamation Point
Quotation Marks ( Diaeresis)
, N umber Sign
$ Dollar Sign
% Percent Sign
& Ampersand
Apostrophe ( Closing Single Quotation Mark; Acute Accent)
Opening Parenthesis
Closing Parenthesis
Asterisk
+ Plus
Comma ( Cedilla)
Hyphen ( Minus)
Period ( Decimal Point)
I Slant
0 . . .9 Digits 0 Through 9
Colon
S emicolon
< Less Than
Equals
> Greater Than
7 Question Mark
@ Commercial At
A . . .Z U ppercase Latin Letters A Through Z
[ Opening Bracket
\ Reverse Slant
1 Closing Bracket
1\ Circumflex
U nderline
Opening Single Quotation Mark ( G rave Accent!
a. . .z Lowerca� Latin Letters a Through z
Opening Brace
Vertical Line
Closing Brace
Tilde
E·3/E-4
APPENDIX F
OPCODE MAP
F.1 I NTRO D U CTION
Th is appendix contains the opcode map and add itional information for cal c u l at i n g re·
q u i red mch i n e cycles.
F . 2 OPCO D E MAP
Table F-1 is the opcode map for M6809 p rocessors. The number(s) by each i n struction in·
d icates the n u m ber of machine cycles req u i red to execute that i n struction. When the
n u m ber contai ns an " I " (e.g ., 4 + I), it indicates that the i ndexed addressing mode i s being
used and that an add itional n u mber of m ach i n e cycles may be requ i red. Refer to Tabl e
F-2 t o determ i ne t h e add itional machi n e cycles t o b e added .
Some i n struct ions i n the opcode map have two n u m bers, the second one i n parenthesis.
Th i s indicates that the i nstruction i nvolves a branch. The parenthet ical number appl ies if
the branch i s taken .
The "page 2, page 3" notation i n col u m n one means that al l page 2 instructions are
preceded by a hexadeci mal 1 0 opcode and al l page 3 instructions are preceded by a hex·
adec i m al 1 1 opcode .
F-1
Table F·1 . Opcode Map
Most-Significant Four Bits

OIR REL ACCA Acca INO EXT IMM OIR INO EXT IMM DIR IND EXT
0000 0001 0010 001 1 0100 0101 01 10 01 1 1 1000 1001 1010 101 1 1 100 1 101 1 1 10 1111
0 1 2 3 4 5 6 7 8 9 A B C D E F
6 3 BRA 4+ 1 2 2 6+ 1 7 2 4 4+ 1 5 2 4 4+ 1 5
0000 0 NEG PAGE2 LEAX NEG S U BA SUBB 0
-
3 BRNI 4+ 1 2 4 4+ 1 5 2 4 4+ 1 5
000 1 1 PAGE3 5 l B R N lEAY CMPA CMPB 1
2 3 BHII 4+ 1 2 4 4+ 1 5 2 4 4+ 1 5
/
-
0010 2 NOP 5(6) L B H I lEAS S B CA

/
SBCB 2
6 2 3 BlSI 4+ 1 2 2 6+ 1 7 4,6,6 + 1 ,7 5,7,7 + 1 ,8 5,7,7 + 1 ,8 4 6 6+ 1 7
001 1 3 COM SYNC 5(6) l B l S lEAU COM SUBD CMPD CMPU ADDD 3
6 3 BHS 5+ 11 by 2 2 6+ 1 7 2 4 4+ 1 5 2 4 4+ 1 5
-
0100 4 L S R 5(6) I B CC) PSHS lSR ANDA ANDB 4
3 B lO 5 + l l by 2 4 4+ 1 5 2 4 4+ 1 5
.f!
- -
." III
0101 5 5161 1 BCS) P U lS BITA BITB 5
N ...
:J
6 5 3 BNEI 5 + l l by 2 2 6+ 1 7 2 4 4+ 1 5 2 4 4+ 1 5
01 1 0 6 ROR lBRA 5(6) l B N E PSHU ROR lOA
If · lOB 6
1: 6 9 3 BEQI 5 + l l by 2 2 6+ 1 7 -
4 4+ 1 5 4 4+ 1 5
�
-
01 1 1 7 ASR lBSR 5(6) lBEQ P U LU ASR STA STB 7
6 ASl 3 BVCI 2 2 6+ 1 7 2 4 4+ 1 5 2 4 4+ 1 5
-
I 1 000 8 I lS LI 5(6) lBVC ASl l lS LI EORA EOR B 8
]
6 2 3 BVSI 5 2 2 6+ 1 7 2 4 4+ 1 5 2 4 4+ 1 5
1001 9 ROl OAA 5(6) lBVS RTS ROl ADCA ADCB 9
6 3 3 BPLI 3 2 2 6+ 1 7 2 4 4+ 1 5 2 4 4+ 1 5
1 010 A DEC ORCC 5(6) lBPl ABX DEC ORA ORB A
3 BMII 6/ 1 5 2 4 4+ 1 5 2 4 4+ 1 5
/ /
- -
101 1 B 5(6) l B M I RTI AOOA AODB B
6 3 3 BGEI 20 2 2 6+ 1 7 4,6,6 + 1 ,7 5,7,7 + 1 ,8 5,7.7 + 1 ,8 3 5 5+ 1 6
1 100 C I N C ANDCC � (6) L B G E CWAI I NC CMPX CMPY CMPS LDD C
6 2 � B lTI 11 2 2 6+ 1 7 7 7 7+1 8 5 5+ 1 6
1 1 01 0 TST SEX 5(6) lBlT MUL TST BSR JSR STD 0
� BGTI
/
3+ 1 4
/
3 8 3,5,5 + 1 ,6 4,6,6 + 1 ,7 3,5,5 + 1 ,6
I
4,6,6 + 1 ,7
1 /
-
1 1 10 E JMP EXG 5(6) lBGT JMP lOX lOY lOU lOS E

� BLEI
1
2 2 6+ 1 7 5,5 + 1 ,6 6,6 + 1 ,7
/
6 7 19120/20 _ 5,5 + 1 ,6 .,,6 + 1 ,7
1 1 1 1 F ClR TFR 5(6) lBlE SWII2/3 ClR STX STY STU STS F
'--- '--- --- '---- '- - - - ----- -- -- -
Table F·2. Indexed Addressing Mode Data
N o n I ndirect I n direct
Assem bler Postbyte x + Assem bler Postbyte + +
Type Forms Form OP Code -
# Form OP Code -
#
Constant O ffset F r o m R N o Offset ,R l R R 00 1 00 0 0 L RI l R R 1 0 l 00 3 0
(twos complement offsetl 5 Bit Offset n, R OR R n n n n n 1 0 defa u lt s to 8 - b i t
8 Bit Offset n, R l R R 0 1 000 1 1 (n, R ] l R R l l 000 4 1
1 6 B it Offset n, R 1 R R 0 1 00 l 4 2 (n, R ] l R R 1 1 00 1 7 2
Acc u m u lator O ffset From R A - R eg i ster O ffset A, R l R ROOl l 0 1 0 (A, R ] l RR 1 01 1 0 4 0
(twos complement offsetl B - R eg i ster Offset B, R l R R 00 1 0 1 1 0 (B , R ] l RR 1 0l 0l 4 0
o - R eg i ster Offset 0, R 1 RROl 01 1 4 0 (0, R ] 1 R R 1 1 01 1 7 0
Auto I n c r e m ent/Decrem ent R I n cre m e nt By 1 ,R+ l R R OOOOO 2 0 not a l l owed

I n crement By 2 , R ++ 1 R R OOOO l 3 0 ( . R ++ ] I l R R 1 000 1 6 0
Decrement Bv 1 ,-R l R R OO0 1 0 2 0 n ot a l l owed
Decrement By 2 ,--R l R R OOOl l 3 0 (, - - R ] l R R 1 00 1 1 6 0
Constant O ffset F r o m PC 8 Bit Offset n , PCR l XX01 1 00 1 1 ( n , PC R ] l XX l l 1 00 4 1

(twos complement offsetl 1 6 B it Offset n , PCR l XX01 1 0 1 5 2 (n, PCR] l XX 1 1 1 0 1 8 2
Extended I n d i rect 1 6 B it Address - - - -
(n] 1 00 1 1 1 1 1 5 2
R = x, Y, U or 5 x -- 00 Y -- 0 1
X = Don't Care U = 10 5 = 11
+ a n d + I n d i cate t h e n u m be r of addit i o n a l cycles a n d bytes for t h e p a r t i c u l a r v a r i at i o n .

-
#
F·3/F·4
APPENDIX G
PIN ASSIGNMENTS
G .1 I NTRO DUCTIO N
of the p i n assi gnm ents for the M C6S09

This appe ndix i s p rovid ed for a q u ick refer ence
. Desc riptio ns of thes e pin assi gnm ents are
and M C6S09E p roce ssor s. Refe r to Fig u re G·1
g iven i n Sect ion 1 .
M C6809 E
M C6809
HAi:T HAlT
TSC
NMi XTAL
LIC
IRa EXTAL
RffiT
4 RffiT
AVMA
5 M R OY
a
a
E
OMA/BREa BUSY
R/W R/W
DO
DO
01
A3 01
02
A4 02
03
AS 03
A6 D4
A6 D4
A7 05
A7 05
AS D6
AS D6
AS 07
AS 07
Al0 A15
Al0 A15
Al l A14
Al l A14
A12 20 21 A13
A12 A13
Figure G·1 . Pin Assignments
G·1 /G·2
AP PEN DIX H
CONVERSION TAB LES
H .1 I NTRO D U CTI O N
This appendix p rovides some conversion tables for you r convenience.
H .2 POWERS OF 2, POWERS O F 1 6
Refer t o Table H-1 .
Table H·1 . Powers of 2; Powers of 1 6
161Tl 2n 16fT1 2n
m= n= Value m= n= Value
0 0 1 4 16 65,536
-
1 2 -
17 1 3 1 ,072
-
2 4 -
18 262 , 1 44
-
3 8 -
19 524,288
1 4 16 5 20 1 ,048,576
-
5 32 -
21 2,097 , 1 52
-
6 64 -
22 4, 1 94,304
-
7 1 28 -
23 8,388 , 608
2 8 256 6 24 1 6,7n,21 6
-
9 512 -
25 33,554,432
-
10 1 ,024 -
26 67 , 1 08,864
-
11 2,048 -
27 1 34,21 7 ,728
3 12 4 , 096 7 28 268,435,456
-
13 8 , 1 92 -
29 536,870,91 2
-
14 1 6,384 -
30 1 ,073,741 ,824
-
15 32,768 -
31 2 , 1 47,483,648
H-1
H .3 H EXAD ECI M AL AN D D ECIMAL CONVERSI O N
Table H -2 i s a ch art that can be u sed for convert i n g n u m bers. fro m either hexadec imal to
decimal or dec i m a l to hexadec i m a l .
H .3.1 CONVERTI N G H EXAD ECI MAL TO DECIMAL. Find the decimal weights for cor
responding hexadec imal characters beg i n n i ng with the least-s i g n ificant character. The
s u m of the dec i m a l wei g hts is the deci mal val ue of the hexadecimal n u m ber.
H .3.2 CO NVERT I N G DECIMAL TO H EXADECI MAL. Find the h i ghest decimal value in the
table which is lower than or equal to the decimal n u m ber to be converted . The correspon
d i ng hexadec i mal character is the most-s i g n ificant d i g it of the f i n a l n u m ber. Subtract the
decimal val u e fo und from the decimal n u m ber to be converted . Repeat the above step to
determ ine the hexadec imal character. Repeat this process to f i n d the su bseq uent hex
adecimal n u m bers.
Table H -2. Hexadecimal and Decimal Conversion Chart
15 Byte 8 7 Byte 0
15 Char 12 11 Char 8 7 Char 4 3 Char 0
Hex Dec Hex Dec Hex Dec Hex Dec
0 0 0 0 0 0 0 0
1 4,096 1 256 1 16 1 1
2 8, 192 2 512 3 32 2 2
3 1 2 ,288 3 768 3 48 3 3
4 16,384 4 1 ,024 4 64 4 4
5 20,480 5 1 ,280 5 80 5 5
6 24,576 6 1 ,536 6 96 6 6
7 28,672 7 1 ,792 7 1 12 7 7
8 32,768 8 2,048 8 1 28 8 8
9 36,864 9 2,304 9 1 44 9 9
A 40,960 A 2,560 A 1 60 A 10
B 45,056 B 2,816 B 1 76 B 11
C 49, 1 52 C 3,072 C 1 92 C 12
0 53,248 0 3,328 0 2(S 0 13
E 57,344 E 3,584 E 224 E 14
F 61 ,440 F 3 .840 F 240 F 15
H -2
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applicalions intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees ariSing out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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Literature Distribution Centers:

USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan.
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PRINTED IN USA (1993) MPS/POD . M6809PM/AD
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M6809PM (AD)

Original Issue: March 1, 1981

©MOTOROLA INC., 1981

Paragraph No. Title Page No.

1.1 Introduction .............................................................................................................1-1

1.3 Software Features ..................................................................................................1-2

1.6 Stack Pointer Registers (U, S) ...............................................................................1.3

1.10.1.5 Carry (C), Bit 0 .................................................................................................1-5

Paragraph No. Title Page No.

1.11.8.4 Halt/Bus Grant ................................................................................................1·8

2.2 Addressing Modes ..................................................................................................2·1

2.2.4 Direct 2·2

2.2.5.1 Constant Offset from Register . ... . . .. . .. .. . .

2.2.5.2 Accumulator Offset from Register ...............................................................2·3

3.1 Introduction .............................................................................................................3·1

Paragraph No. Title Page No.

4.1 Introduction ............................................................................................................. 4-1

4.2.6 Stack Programming ...........................................................................................4-6

4.4 Instruction Set ........................................................................................................4-9

A.1 Introduction ............................................................................................................A-1

8.1 General Description ............................................................................................... 8-1

Paragraph No. Title Page No.

B.5 Input/Output Control ............................................................................................. B-4

Register ............................................................................................................. B-11

Paragraph No. Title Page No.

.COOFF ............................................................................................................. 8-29

.IRQ .................................................................................................................... 8-31

.PAD ........ ....................................... . ........ . ........................................... . .............. 8-32

.RESET ..... . ........ . ............... . ..

.RSVD ........... . .......... ..

C.1 Introduction . .. ........... . ..... .. .. ... .

0.1 Introduction ..... . . . .. .... ...

E.1 Introduction ............................................................................................................E·1

Paragraph No. Title Page No.

F.1 Introduction F-1

F.2 Opcode Map............................................................................................................ F-1

Figure No. Title Page No.

1-1 Programming Model ...............................................................................................1-3

2-1 Post byte Usage for EXGrrFR, PSH/PUllnstructions ........................................2-2

3-1 Interrupt Processing Flowchart ............................................................................3-5

4-1 Stacking Order ........................................................................................................4-7

8-1 Memory Map ........................................................................................................... 8-2

E-1 ASCII Character Set ...............................................................................................E-1

G-1 Pin Assignments .................................................................................................... G-1

Table No. Title Page No.

1 -1 BAlBS Signal Encoding ........................... . ................................... . . .. ............ . .

2-1 Postbyte Usage for Indexed Addressing Modes ................................................2-3

3-1 Interrupt Vector Locations .......................................... . ...... . ....... . .......................... 3-1

4-1 Instruction Set ........................................... . ....................... . .

A-1 Operation Notation ....................... . ... . .............................. . ......................... . .......... .A-1

B-1 Command List ........................................................................................................B-5

B-3 Vector Table Entries ............................................................................................B-22

C-1 Machine Code to Instruction Cross Reference .................................................. C-2

0-1 Programming Aid ................................................................................................... 0-1

E-1 Control Characters ................................................................................................ E-2

F-1 Opcode Map .

H-1 Powers of 2; Powers of 16 .....................................................................................H-1

Enhancements such as additional registers (a Y index register, a U stack pOinter, and a

Upward compatibility is guaranteed as MC6800 assembly language programs may be

A multiply instruction is included which multiplies unsigned binary numbers in ac

LoI DP 1

1.1 1 .1 0 INTERRUPT�The processor has three separate interrupt input�s: non

1.11 .1 2 ADVANCED VALID MEMORY ADDRESS(AVMA)(MC8809E). This output signal in

Global, permanent, and temporary values need to be eas i ly available in a position

Without stacks, most modern block-structured h i gh -level languages would be c um ber