Efficient Amplitude Modulator and Ripple
Canceller for Visible Light Communication
Kumar Arulandu1, Jean-Paul Linnartz1,2, Fellow, IEEE, Xiong Deng2, Member, IEEE
1
Signify (Philips Lighting) Research, 2Eindhoven University of Technology, the Netherlands
Abstract—Power loss is an important design factor for Visible
Light Communication (VLC). Dissipating only a few percent of
the illumination power can still result into a few watts of heat
generation which requires additional provisions for cooling the
modulator circuit. We show that a transistor in series with LED
can be used in linear operation to apply amplitude modulation
which only marginally sacrifices efficiency. Yet, this requires a
novel active control loop. We report its performance and fre-
quency response for VLC modulation. We show that the modu-
lator also effectively cancels mains ripple. Based on our exper-
imental experience, we also propose a model to quantify the
power losses and verify these for pulse amplitude modulation.
Index Terms—Visible Light Communication, Optical Wire-
less Communication, LED drivers, Li-Fi.
I. INTRODUCTION
The rapid transition to LED lighting opens the opportunity
to transmit data via illumination light [1]. Various circuits
for modulation have been studied [2]: a separate illumination
power source and a data power amplifier can be used with a
bias-T circuit (see Fig. 1(a)). Alternatively, if the LEDs are
driven by a stable DC source, the time-varying (data) current
can be modulated via a series transistor, as shown in Fig. 1(b)
[3]-[5]. The use of series transistor becomes attractive, due to
the bulky inductor (L) and capacitor (C) values in the Bias-T.
VLED VLED
L Bias Tee
LED
C measured results are verified in Section IX. Section X con-
Data PA
FET
Data
LED
(a) Bias Tee modulation (b) Serial FET modulation
Fig. 1. VLC modulators commonly studied in literature.
In contrast to what is shown in Fig. 1, most of LED driv-
ers in the market are Switched Mode Power Supplies
(SMPS) that act as current sources [6]-[8]. This paper de-
scribes how a current source as LED driver can nonetheless
co-exist with a series transistor that also regulates the cur-
rent. The combination of a DC current source for illumina-
tion in series with a current control transistor is challenging.
The slightest mismatch between the DC current source and
the average transistor drain current leads to a rapidly deviat-
ing voltage across vital circuit components such as the
modulating FET or the buffer capacitor.
A theoretical evaluation in [9] was limited to modelling
the modulator as a perfect Voltage Drain 1 , i.e., a circuit
1
We avoid the wording “voltage source”, because the transistor is ab-
sorbing power, not delivering power.
978-1-5386-4920-6/18/$31.00 ©2018 IEEE
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component that (actively) forces a certain voltage across its
connectors. In practice, the collector-emitter or drain-source
path of a transistor do not control a voltage, but rather con-
trol a current. In this paper, we resolve this issue. A further
main contribution is that we reuse the VLC modulator to also
remove the ripple from the driver and to dynamically adapt
to any DC current setting from the driver to follow dimming
or component variations.
To achieve these, we introduce a slow control loop to set
the transistor current such that the voltage across the transis-
tor stays within appropriate limits just to accommodate mod-
ulation. In other words, we address a system in which, for its
DC settings, the average current through the transistor auto-
matically adapts to the value dictated by the LED driver
while also rejecting the ripple from the LED driver. In addi-
tion, and in contrast to [10], the transistor circuit adds High
Frequencies (HF) (data) to the ripple free LED driver current
by means of a fast control loop ensuring a consistent modu-
lation for a large combination of LED drivers and LED
loads.
The organization of the paper is as follows. The basic idea
of the modulator is introduced in Section II. Section III mod-
els the LED power consumption, while Sections IV and V
address the power consumed in a system for a very large and
a realistic buffer capacitor, respectively. Parameters related
ripple suppression are described in Section VI. Basic proper-
ties of the control loops are briefly explained in Section VII.
Followed by a transient measurement of the actual circuit
that is explained in Section VIII. Calculated, simulated and
cludes this paper.
II. MODULATOR CONCEPT
To match the average transistor current with that of the
driver and to let transistor QM behave as a voltage regulator
with modulation head room, the drain-voltage of the
MOSFET is measured and used in a feedback control to
stabilize the DC LED current (see Fig. 2). To avoid interfer-
ence between the internal control loops of the LED driver
and the slow control loop of the modulator, a buffer capaci-
tor CD is used at input of the modulator. This capacitor also
suppresses the modulation current towards the DC driver.
The block diagram of the series modulator (Fig. 2) simpli-
fies the LED driver as an ideal (infinite impedance, but pos-
sibly time varying) current source ID with small buffer capac-
itor. Typically, the output capacitance of the LED driver
varies from few micro Farads to few hundreds of micro Far-
ads. Our analysis assumes that the capacitor CD of the modu-
lator circuit adequately captures any driver internal capaci-
tance.
 LED driver output
ID Vbus
IC
VLED
RCD
Vmod_min
VCD
+
LPF
- Vmod
CD
+ +
Vm - Gain
HPF
Fig. 2. Block diagram of the series modulator and its control loop.
III. LED POWER CONSUMPTION
To distinguish between the large average DC current IL
and the small (zero-mean) AC signal i(t) covering time-
varying modulation and ripple, we denote the LED current in
italics, as IL(t) = IL + i(t). When we treat IL(t) as a (stationary)
random variable, we denote it as IL. This notation applies for
voltages and currents. We linearize the LED into a current-
dependent junction voltage Vj(IL) in series with RL, (𝑅𝐿 =
𝑅𝑑𝑦𝑛 + 𝑅𝐸𝑆𝑅 ) consisting of an Equivalent Series Resistance
RESR and a current-dependent dynamic junction resistance
Rdyn(IL) of
𝑑𝑉𝐿 𝑛0 𝑘𝑇
𝑅𝑑𝑦𝑛 ≜ | = ,
𝑑𝐼𝐿 I
𝐿
𝑞I𝐿
where n0 is the LED ideality factor, k is the Boltzmann con-
stant, T is the temperature in Kelvin and q is the electron
charge. For the ease of notation, we omit the explicit de-
pendency on IL in 𝑉𝑗 (I𝐿 ) and 𝑅𝐿 (I𝐿 ), so
(2)
𝑉𝐿𝐸𝐷 (𝑡) = V𝑗 + 𝑅𝐿 I𝐿 + 𝑅𝐿 𝑖(𝑡),
The modulated current is also expressed as IL(t) = IL (1 +
m(t)), thus modulated with -1 < m(t) < 1 and E [m(t)] =
0. Thus, we have i (t) = m (t) IL. We denote the rms modula-
tion index as 𝛼𝑟𝑚𝑠 = √E[𝛼𝑚 2 (𝑡)], with 0 ≤ 𝛼
𝑟𝑚𝑠 ≤ 1.
The extra power (in the LED only) is the difference be-
tween the average power during modulation E[P( 𝛼𝑚 )] and
the unmodulated power 𝑃𝐿𝐸𝐷 (αm = 0), thus 𝑝𝐿𝐸𝐷 =
E[ 𝑃𝐿𝐸𝐷 (𝛼𝑚 )] − 𝑃𝐿𝐸𝐷 (𝛼𝑚 = 0) . For modulation frequencies
that are not heavily affected by the junction capacity, thus
using (2) without any extra parasitic capacitances,
𝑝𝐿𝐸𝐷 ≈ 𝑅𝐿 𝐼𝐿2 𝛼𝑟𝑚𝑠
2 .
At a later stage, we will also introduce ripple D in the
LED-driver. However, since the ripple is effectively counter-
acted by the modulator, only the intentional modulation m
affects pLED. Thus, Eq. (3) remains valid.
IV. POWER FROM RIPPLE-FREE DRIVER
In this section, we initially exclude the capacitor proper-
ties and assume that the bus voltage is constant (Vbus = Vbus).
Enforced by the control loop, the modulator QM acts as a
controlled voltage drop Vmod in series with VLED. In such case,
the system power consumption in the LED plus QM can be
described by a multiplication of the average current times the
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voltage across Vbus, which includes a particular Vmargin for
modulation. The extra supply power is 𝑝𝑒𝑙 ≝ E[V𝐶𝐷 I𝐿 ] −
IL (𝑉𝑗 (IL ) + 𝑅𝐿 IL )I𝐿 = V𝑚𝑎𝑟𝑔𝑖𝑛 I𝐿 . We extend [9] to show that
RL this seemingly oversimplified expression is in fact a correct
expression and can be extended to address imperfect drivers
VJ
with ripple. The extra power correctly equals the average of
the multiplication of the current and voltage, even though we
IT
multiply an average current and an average voltage. Moreo-
QM ver, we quantify Vmargin, as it consists of two terms, Vsat as the
lowest possible saturation value of Vmod , and Vswing which
reflects the highest possible variation to achieve the desired
RS modulation and ripple elimination.
We determine the corresponding capacitor DC voltage as
V𝐶𝐷 = V𝐿𝐸𝐷 + V𝑚𝑎𝑟𝑔𝑖𝑛 , where Vmargin ensures that the buffer
capacitor voltage has sufficient headroom. It needs to ac-
commodate a maximum upswing of modulation αm to deliver
the increased LED voltage. It also accommodates ESR volt-
age drops across Rtot, elsewhere, thus including RCD in the
buffer capacitor, the transistor ohmic bias resistance hRQ and
the sense resistor RS. To minimize losses, hRQ needs to be as
low as possible while ensuring a relatively linear response
between gate-source voltage variation and delta drain current
variation. Secondly, if the transistor is biased in the ohmic
region, RQ becomes temperature dependent. To overcome
these problems, the transistor gate is biased for linear re-
sponse with a factor h > 1. The minimum voltage drop be-
tween the transistor drain and its source will be represented
(1) by hRQ IL.
We consider a string of m LEDs in series. To modulate a
high-amplitude symbol, QM needs to decrease 𝑉𝑚𝑜𝑑 to
𝑉𝑚𝑜𝑑 ≈ [𝑅𝐶𝐷 + 𝑚𝑅𝐿 ]I𝐿 𝛼𝑚𝑎𝑥 , provided that the buffer capaci-
tor can keep VCD constant. This requires a voltage headroom
of
V𝑚𝑎𝑟𝑔𝑖𝑛 ≈ [𝑅𝐶𝐷 +𝑚𝑅𝐿 + ℎ𝑅𝑄 + 𝑅𝑆 ]I𝐿 𝛼𝑚𝑎𝑥 . (4)
Since the voltage drops across RCD, hRQ and RS do not de-
pend on m, the modulator efficiency improves with increas-
ing number of series LEDs. The expected consumed electri-
cal power is an integral over the probability density fI(i) of
the LED current
∞
E[𝑃𝑒𝑙 ] = ∫0 [𝑉𝑚𝑜𝑑 (𝑖) + 𝑉𝐿𝐸𝐷 (𝑖)]𝑖𝑓𝐼 (𝑖)𝑑𝑖 . (5)
If a sufficiently large capacitor is used to consider VCD
constant, Vmod and VLED individually fluctuate with i, but their
sum is constant and Vmod(i) + VLED(i) = Vmargin + VLED, so it can
be taken out of the integral. That is, the extra loss, above the
unmodulated power consumption is pel = Vmargin IL. Thus,
(3)
E[𝑃𝑒𝑙 ] = [𝑅𝐶𝐷 + 𝑚𝑅𝐿 + ℎ𝑅𝑄 + 𝑅𝑆 ]I𝐿2 𝛼𝑚 . (6)
The total extra losses 𝑝𝑒𝑙 scale linearly with the modula-
tion depth m This is in contrast to the case of typical RF
communication, where the power consumed in the transmit-
ter is proportional to m. Yet in other LED modulator, cir-
cuit the power may also grow quadratically with modulation
depth [3].
V. MODULATION WITH IMPERFECT BUFFER CAPACITOR
To model a more realistic driver, we assume an imperfect
capacitor with limited capacitance and with ESR resistance,
yet we maintain the assumption that the LED driver acts as
an ideal current source. Later, we will also introduce ripple.
For DC-free (duty cycle D = 0.5) bi-phase amplitude mod-
ulation of a logical zero, with 𝛼(𝑡) = 𝛼𝑚 for 0 < 𝑡 < 𝐷𝑇𝑠 and
− 𝛼𝑚 in the remaining part of the bit interval 𝐷𝑇𝑠 < 𝑡 <
(1 − 𝐷)𝑇𝑠 , the voltage variation during modulation of the
transistor QM follows
𝑣𝑄𝑀,𝑚 (𝑡) ≈
𝐷𝑇𝑆 −𝑡
(ℎ𝑅𝑄 + ) I𝐿 𝛼𝑚 , 0 < 𝑡 < 𝐷𝑇𝑠
𝐶𝐷
{ . (7)
(2𝑅𝐶𝐷 +
𝑡
+2𝑚𝑅𝐿 + ℎ𝑅𝑄 + 2𝑅𝑆 ) I𝐿 𝛼𝑚 , 𝐷𝑇𝑠 < 𝑡 < (1 − 𝐷)𝑇𝑠
𝐶𝐷
Here, the constant 𝐷𝑇𝑆 /𝐶𝐷 is introduced to ensure that the
voltage does not carry a DC component, as DC biasing is
accounted for separately.
At the start of interval of a +ILαm symbol, the buffer ca-
pacitor CD needs an excess charge to support Vmargin and to
accommodate a drop due to discharge of the buffer capacitor
during this interval. This means that the excess energy re-
quired to modulate a high symbol is supplied from the buffer
capacitor, and the voltage drop across the modulating transis-
tor QM is minimal as the voltage drops across the resistive
elements increase. Similarly, during the modulation of a low
symbol -ILαm, the voltage drop across the modulating transis-
tor is high. The difference between ILαm and -ILαm is 2ILαm,
therefore the voltage drop across QM, due to resistive ele-
ments, increases with a factor 2.
To illustrate the relationship between Vmod and IL(t), Fig. 3
zooms in on the variations of the voltage and current wave-
forms for amplitude modulation, where Vmod(t) is the voltage
at node Vmod; VCD,m(t) the voltage variation across CD; IL(t)
represents the modulated LED current of the DC-free bi-
phase AM signal. Fig. 3 simplifies random data into a regu-
lar sequence. Yet, a random pattern of data will give the
same average, rms and peak values.
So, the maximum voltage variation due to amplitude
modulation at that node vmod is denoted as 𝑣̂𝑚𝑜𝑑,𝑚 and con-
sists of
𝑣̂𝑚𝑜𝑑,𝑚 = (2𝑅𝐶𝐷 +2𝑚𝑅𝐿 + ℎ𝑅𝑄 + 2𝑅𝑆 +
Extra power for modulation can be subdivided into modu-
lator losses
(9)
𝑉𝑄𝑀 (𝑡)I𝐿 𝛼𝑚 I𝐿 (1 + 𝛼𝑚 )
𝑝𝑄𝑀,𝑚 (𝑡) ≈ {
𝑉𝑄𝑀 (𝑡)I𝐿 𝛼𝑚 I𝐿 (1 − 𝛼𝑚 ) 𝐷𝑇𝑠 < 𝑡 < (1 − 𝐷)𝑇𝑠 .
and resistive losses
𝐼𝐿2 𝛼𝑚
2 (𝑅 + 𝑅 + 𝑅 ).
𝐿 𝑆 𝐶𝐷
Integrating (9) over the symbol period Ts with duty cycle
D = 1/2, the average total extra power for amplitude modula-
tion (but not ripple reduction) within the modulator becomes
𝐷𝑇𝑆
𝐷𝑇𝑆
∫ ∆𝑃𝑄𝑀 (𝑡)𝑑𝑡 = (I𝐿2 𝛼𝑚𝑎𝑥 + I𝐿2 𝛼𝑚𝑎𝑥
2 ) (ℎ𝑅𝑄 +
0 2𝐶𝐷
plus
𝑇𝑆
∫ ∆𝑃𝑄𝑀 (𝑡)𝑑𝑡 = (I𝐿2 𝛼𝑚𝑎𝑥 − I𝐿2 𝛼𝑚𝑎𝑥
2 )
𝐷𝑇𝑆
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2𝑛𝑘𝑇 𝐷𝑇𝑆
(2𝑅𝐶𝐷 + +2𝑅𝐿 + ℎ𝑅𝑄 + 2𝑅𝑆 + ) 𝐷𝑇𝑆
𝑞I𝐿 2𝐶𝐷
and by adding losses (10) in the resistive elements, the total
extra power amounts to
𝐷𝑇𝑠
E[𝑃𝑒𝑙 ] = [𝑅𝐶𝐷 +𝑚𝑅𝐿 + ℎ𝑅𝑄 + 𝑅𝑆 + ] I𝐿2 𝛼𝑚𝑎𝑥 . (11)
2𝐶𝐷
As it becomes clear from (11), the extra power losses
increase with the duration of the symbol due to the discharge
of the buffer capacitor CD. For applications with camera de-
tection, typically long Ts will be needed. Increasing CD can
mitigate this, but as we will show later, CD is subject to an
optimization.
D D

Vmod(t)
vCD,m(t)
IL(t)
IL(t)
t
Fig. 3. Spice-simulated time variations due to DC-free bi-phase modulated
LED current IL(t); Required modulator voltage vmod(t), consisting of the
reactive voltage variation VCD,m across a storage capacitor CD minus dissipa-
tive voltages RtotiL(t) caused by mRL, hRQ, RS and also RCD.
If the control loop is designed properly, Vmod does not go
below Vmod_min of 0.3V and ensures that the transistor remains
in the linear operating mode. In Fig. 3, we can clearly distin-
guish the modulation losses related to the resistive compo-
nents as they appear as voltage steps and losses related to the
𝐷𝑇𝑆 capacitance value as they appear as voltage slopes. VCD(t) is
) I𝐿 𝛼𝑚 . (8) added to Fig. 3 to visualize the charging and discharging
𝐶𝐷
slopes of CD w.r.t. modulation as these slopes are significant-
ly smaller in amplitude compared to the resistive voltage
steps at Vmod. Finally, Fig. 3 also shows that the modulated
LED current IL(t) properly alternates with αm around the
0 < 𝑡 < 𝐷𝑇𝑠 average supply current IL(t).
VI. MAINS RIPPLE ON THE BUS
We denote the mains voltage as √2𝑉𝐴𝐶 𝑠𝑖𝑛(2𝜋𝑓𝑚 𝑡 + 𝜃/2) ,
where we inserted a random phase because we prefer to
(10) use the modulation clock as our time reference. Regulations
prescribe that LED drivers need to have a good Power Factor
(PF). That is, these LED drivers need to act as a purely resis-
tive load Rin to the mains. So, these draw a time-varying
power of
2𝑉 2 2
𝑃𝑚𝑎𝑖𝑛𝑠 (𝑡) ≈ 𝐴𝐶 (sin(2𝜋𝑓𝑚 𝑡 + 𝜃)) . (12)
𝑅 𝑖𝑛
) 𝐷𝑇𝑆
A sufficiently loss-less and non-buffering driver thus de-
livers the same power 𝑃𝑚𝑎𝑖𝑛𝑠 (𝑡) = 𝑃𝐷 (𝑡) to the LED load and
to the buffer capacitor CD. For a sufficiently large and ESR-
free capacitor, VCD is a constant, so the ripple current ID(t)
needs to be of the form
 𝐼𝐷 (𝑡) ≈ 𝐼𝐿 (1 − 𝛼𝐷 cos(4𝜋𝑓𝑚 𝑡 + 𝜃)). (13) VCD

Pin (t) VLED (t)

where, at the unbuffered driver output, the modulation depth Pin (t) LED
D = 1. This single frequency sinusoid is a good approxima- Vmod
QM
tion also for imperfect drivers, particularly if we allow other
VCD (t)
values for D in our model. In fact, practical LED drivers do VQM(t)
not provide a perfect Power Factor, particularly these LED
drivers attempt to reduce output ripple. We reflect this as D
< 1. Realistically, D is around 0.3 to 0.5. Fig. 4. Flow of power to illustrate ripple reduction For a LED driver with
The modulation occurs at frequencies above the 100 or power factor 1, without charge storage elements. Pin(t) is the input power;
VCD(t) is voltage drop across the buffer capacitor; VLED(t) is voltage drop
120 Hz mains ripple. It is reasonable to assume that the driv- across the LEDs, and VQM(t) is the voltage drop across the modulating
er ripple and the modulation are independent, so one may transistor.
add to individual contributions due to ripple and modulation,
namely 𝑣𝐶𝐷 = 𝑣𝐶𝐷,𝑚 + 𝑣𝐶𝐷,𝐷 with zero cross terms. VII. FREQUENCY RESPONSE
Justified by experiments, we assume that the transistor
When supplied by a constant current source, the VLC
accommodates any mains ripple variations in the driver out-
modulator requires at least the slow control loop to avoid run
put and prevents these from being present in the LED cur-
away in steady state operation. In that control, the transistor
rent. In such case, all ripple current flows though CD and the
DC current is such that the supplied current from the driver
transistor needs to make an extra voltage swing, equal to the
equals the LED current IL. In addition, this loop also needs to
voltage swing across the buffer capacitor to eliminate ripple
maintain an appropriate Vmargin for the swing to accommodate
in LED current. This further implies that the voltage swing
modulation without distortion while keeping the modulation
across the capacitor 𝑣𝐶𝐷,𝑓𝑙 (𝑡) due to driver ripple is deter-
losses to the minimum. Fig. 5 shows the simulated open-loop
mined by iD(t), RCD and by CD. Fig. 4 gives an example of
response of Vmargin control for the circuit given in Fig. 2.
how the mains ripple reduction function operates when it is
Perturbation is applied to Vmod min and response is measured at
supplied by an ideal LED driver with power factor 1 and Vmod. The simulation is approximate, because the simulation
does not contain charge storage elements. models may not include all component details and external
Since voltage fluctuations across CD are only cause by the parasitic elements, but it is useful to have a better under-
AC ripple, we determine voltage fluctuations across CD as standing of the dynamic response of the circuit design.
1 𝑡 We used an integrator as LPF (see Fig. 2). We choose its
𝑣𝐶𝐷,𝐷 (𝑡) ≈ 𝑅𝐶𝐷 𝑖𝐷 (𝑡) + ∫𝑡 −I𝐿 𝛼𝐷 cos(4𝜋𝑓𝑚 𝑡 + 𝜃) 𝑑𝑡, (14) gain to result in a control loop with unity gain of 25 Hz for
𝐶𝐷 0
Vmod to ensure that this filter does not respond to higher fre-
which results into quencies to let QM remove the rectified mains ripple at har-
(15) monics of 100 Hz (coming in via the driver current) and
2 modulation in the kHz (entered via modulation of the transis-
2 1
𝑣𝐶𝐷 (𝑡) = I𝐿 𝐷 √𝑅𝐶𝐷 +( ) sin(4𝜋𝑓𝑚𝑎𝑖𝑛𝑠 𝑡 + 𝜃𝑣 ). tor). Yet at DC levels it has infinite gain, to ensure that the
4𝐶𝐷 𝜋𝑓𝑚𝑎𝑖𝑛𝑠
QM perfectly follows the average driver current.
To cancel ripple and to create a stable voltage across the
LEDs, the modulator needs to counteract the voltage varia-
tion by a unipolar signal, the modulator voltage incorporates
a DC offset
(16)
1 2
2
𝑣𝑄𝑀,𝑓𝑙 (𝑡) = 𝐼𝐿 𝛼𝐷 √𝑅𝐶𝐷 +( ) (sin(4𝜋𝑓𝑚𝑎𝑖𝑛𝑠 𝑡 + 𝜃𝑣 ) + 1),
4𝐶𝐷 𝜋𝑓𝑚𝑎𝑖𝑛𝑠

𝜋
with phase 𝜃𝑣 = −tan−1 (1/4𝜋𝑓𝑚 𝐶𝐷 𝑅𝐶𝐷 ) − 2 , although its
exact value does influence our further calculations.
Fig. 5. Simulated amplitude (solid curve) and phase (dashed curve) of the
Power losses for ripple reduction are equal to vQM,D(t) multi- loop gain of Vmargin control for the circuit in Fig 2.
plied by IL, as the transistor conducts the ripple-free LED
current IL. Since biasing losses are already taken into account For camera detection, a low frequency modulation signal
in the modulation, ripple-reduction has only additional losses is preferred without phase or amplitude distortions. Moreo-
in transistor QM, with ver, we preferred a circuit that remains within tight specs for
different choices of LED and driver configurations and under
2 various operating conditions. Hence, a second, high frequen-
1 I2
𝐿 𝛼𝐷
𝑝𝑄𝑀,𝐷 = I𝐿2 𝛼𝐷 √𝑅𝐶𝐷
2
+( ) ≈ . (17) cy loop, is added to force the modulating current by monitor-
4𝐶𝐷 𝜋𝑓𝑚𝑎𝑖𝑛𝑠 4𝐶𝐷 𝜋𝑓𝑚𝑎𝑖𝑛𝑠
ing the voltage across RS. As the response of a closed loop
We observe that the power needed to eliminate main ripple is control system is analyzed by the open-loop transfer func-
inversely proportional to CD, but having a large CD is not tion, is simulated open-loop response approximation by
attractive. applying perturbation on modulation input Vm, and measur-
ing the response of modulation current IL(t) across RS, is
presented in Fig. 6.

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Fig. 6. Simulated open-loop response approximation of modulation current
IL(t) control loop.
Other experimental circuits (not reported here in detail)
confirmed that if the second loop is omitted, an open loop
modulation response beyond several MHz can easily be
achieved, but at the cost of some minor linear and non-linear
distortion, and fixed settings, yet adequate for OFDM modu-
lation.
VIII. MEASUREMENTS
We verified our concept by an actual VLC modulator test
circuit, shown in Fig. 7. This circuit is intended to apply αm
of 0.1 for LED drivers with a voltage range of 15-60V (thus
for, say m = 5 to 20 LEDs in series) and a current range of IL
= 250 mA to 2.5 A (thus also realized by paralleling LEDs).
The size of the PCB is mainly dominated by the size of the
capacitor CD and the required heat-sink area for the series
modulator. This re-confirms the core motivation for our
paper to focus on power consumption and on active ripple
mitigation to reduce CD.
As observed from (17), the losses are independent of the
number of LED as losses are mainly related to diver ripple
and the capacitance of CD.
Fig. 7. Evaluation circuit of the VLC modulator optimized for low frequen-
cy VLC.
Firstly, we start with verifying the modulation losses by
using an ideal LED driver with a ripple-free current at the
output. Fig. 8 shows the scope image of the most relevant
signals of our series modulator. The output current of the
LED driver in purple has been measured before CD. It is rela-
tively flat, but contains a high frequency current, which is
caused by the LED driver output stage. Compared to the
mains frequency, the high frequency ripple at the output of
the LED driver is negligibly small due to CD. Thus, this high
frequency ripple will cause additional rms losses within CD,
but it will not affect the control loops nor cause additional
losses within the modulator itself. We verified that high
frequency ripple is filtered out sufficiently by CD. The volt-
age drop across the modulator is dominated by the total of
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RCD, RL, RQ and RS as the slopes are hardly visible due to a
relative high capacitance value of CD.
Fig. 8. Measurement of idealized driver without mains flicker, but with HF
ripple of the LED driver. Green: Voltage drop across the modulator
[500mV/div]. Purple: Output current of the LED driver [200mA/div]. Pink:
LED current [200mA/div]. Time: [500uS/div].
Secondly, and more realistically, a LED driver with a
relatively high mains ripple current is tested on the VLC
modulator as well. Fig. 9 shows a scope plot of signals with-
in the VLC modulator that is supplied by a LED driver with
IL = 0.7A and an output ripple current (αD ≈ 0.7). As ex-
pected, the modulated output current is free of ripple, and the
modulator realized this by making an additional upswing.
Fig. 9. Capture of Oscilloscope of signals within our VLC modulator that is
supplied by a DC LED current IL = 0.7 A and a realistic output main ripple
current of αD = 0.7. Green: Voltage drop Vmod(t) across the modulator
[500mV/div]. Purple: Output current ID(t) of the LED driver [200mA/div].
Pink: LED current IL(t) [200mA/div]. Time scale [2mS/div].
IX. VERIFICATION
In this section, we compare the losses predicted by the
numerical model and the simulations with real hardware. The
DC current setting can accurately be set within a digital LED
driver. However, a setting up a current source with a variable
mains ripple was a challenge. A Kepco BoP (Bipolar Opera-
tional Power supply with the ability to source and sink cur-
rents) was configured in current output mode and used in
combination with an AWG (Arbitrary waveform generator)
to emulate mains ripple of various intensities. Losses related
to modulation of αmax = 0.1 are presented in Fig. 10.
Simulation results match relatively well with the calculat-
ed extra power losses of (11) for VLC modulation with αm =
0.1, which is typical used for in some low rate VLC systems.
The mathematical model is more optimistic than simula-
tions that address more imperfections of the LEDs, Transis-
tor and other components, yet we believe that the theoretical
model can be appropriately accurate for initial system design
and to understand the trade-offs, such as the size of CD versus
power consumption.
As Vmargin is very low at low current levels, the filter im-
plemented in the simulation model appeared less accurate in
controlling it (app. 50%). As shown in Fig 10, efficiency loss
is inversely proportional to the number of LEDs in series.
This is due to the insertion losses of the modulator and resis-
tive losses of the remaining circuit that is constant while the
LED power increases with the number of series LEDs.
Fig. 10. Losses related to modulation of αmax = 0.1. The outcomes of the
equations are represented by the solid lines and simulation results are repre-
sented by ‘X’ in the same order as in the legend.
Similarly, Fig. 11 shows the relative losses related to rip-
ple reduction for m = 20 series LEDs. The losses for ripple
reduction, as also explained trough (17), losses are inde-
pendent on the number of series LEDs.
Fig. 11. Relative losses related to ripple reduction for m = 20 series LEDs.
The outcomes of the equations are represented by the solid lines, simulation
results are represented by ‘X’ and measurement results are represented by
‘O’ in the same order as shown in the legend.
Measurements of the power consumption due to mains
ripple, which is the dominant effect, appeared possible and
fit well with predictions by simulation and theory. For the
much smaller losses due to modulation, typical lab meas-
urement equipment inserts non-negligible disturbances (sig-
nificant compared to 0.1 Ohm) of the ohmic ESR resistances
and made measurements unreliable, but confirmed that ripple
reduction dominates losses.
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X. CONCLUSION
We have shown that it is feasible to implement an OWC
system using a (typical, imperfect) DC current driver, and to
apply modulation via a series transistor. We showed that
ripple can be reduced at the expense of additional dissipation
in the modulator. Our model and expressions provide insight
to optimize the extra volume of the capacitors versus the
extra power dissipation.
The simulation results show that VLC can be applied
efficiently as described in [9]. Simulation results also con-
firm that extra power losses for VLC modulation with α m ≤
0.1, which is typical for low frequency VLC, comes at the
cost of efficiency degradation < 2%. For higher modulation
depths, the total extra loss for modulation is proportional to
αm. This is in contract to radio communication where the
consumed power typically increases with α2. Furthermore,
the extra power losses increase with the duration of the sym-
bol due to the discharge of the buffer capacitor CD, that is, the
consumed energy per symbol increases faster than propor-
tionally with symbol duration. Yet for sufficiently fast modu-
lation a fixed power penalty remains.
Losses due to ripple reduction typically exceed modulation
losses and can be mitigated by increasing capacitance of the
buffer capacitor CD.
We also tested a second control loop to realize a near-
perfect representation of the modulation input signal into
modulated LED current for a wide range of LED current
supplying a large variety series and parallel configuration of
LEDs. Yet this limits the total bandwidth.
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