Logic Design and Computing Systems

Chapter 5
Synchronous Sequential Logic
Outline
 Sequential Circuits
 Storage Elements
 Analysis of Clocked Sequential Circuits

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Introduction
 Almost all electronic devices process, store, transmit, and
receives information.
 These devices depend on electronic components that have the
capability of storing information, i.e. memory.
 So far combinational circuits, which have no memory, only
depend on current inputs.
 Sequential circuits, which have memory, depend on past
values/states & current inputs.

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Sequential Circuits

 Block diagram of sequential circuit.

 Storage elements are used to store past binary information.
 The binary information stored in storage elements at any
given time defines the state of the sequential circuit at that
time.
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Sequential Circuits
 In sequential circuits, the present outputs of the sequential
circuit depend on the its present inputs & its previous states
stored in the memory element.
 External inputs also determine the state of storage elements.
 The next state of storage elements is the function of external
input & the present state.
 A sequential circuit is specified by a time sequence of inputs,
outputs, and internal states.

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Sequential Circuits
Two types of sequential circuits:
oSynchronous SC: its behavior can be defined from the
knowledge of its signals at discrete instants of time.
oAsynchronous SC: its behavior can be defined from the inputs at
any instants of time and the order in which the inputs change.
• Storage elements used are (usually) time-delay elements.
• The storage capability of time-delay depends on the
propagation delay through the device.
• Practically the internal propagation delay might be enough to
create the time-delay needed.

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 Sequential Circuits
 In gate-type asynchronous systems, the storage elements consist
of logic gates whose propagation delay provides the required storage.
 Thus, an asynchronous sequential circuit may be regarded as a
combinational circuit with feedback.
 Because of the feedback among logic gates, an asynchronous
sequential circuit may become unstable at times.

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 Sequential Circuits
 A synchronous sequential circuit employs signals that affect the
storage elements at only discrete instants of time.
 Synchronization is achieved by a timing device called a clock
generator, which provides a clock signal having the form of a
periodic train of clock pulses (Clock or clk). This is called clocked
sequential circuit.
 Clock pulses are distributed throughout the system so that
storage elements are affected only with the arrival of each pulse.
 In practice, the clock pulses determine when computational
activity will occur within the circuit.
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 Sequential Circuits
Inputs Outputs
Combinational
Circuit Storage
Elements
Asynchronous

Inputs Outputs
Combinational
Circuit
Storage
Synchronous Clock Elements

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Storage Elements
A storage element in a digital circuit can maintain a
binary state, until directed by an input signal to switch
states.
The operating speed of the combinational circuit is
critical, and should be considered in designing the
clock.
Storage elements that operate with signal levels (rather
than signal transitions) are referred to as latches; those
controlled by a clock transition are flip-flops.

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Storage Elements
 Controlled latches are level-triggered

Clk

 Flip-Flops are edge-triggered

Clk Positive Edge

Clk Negative Edge

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Storage Elements
Bistable Element
 The simplest storage element
 No inputs
 The output depends on the
initial state.
 Then it will store ‘indefinitely’

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 Storage Elements: Latches
SR-Latch
 The two inputs, S for set and R
for reset
 Two useful states:
R Q  Q = 1 & Q’ = 0 : set state
 Q = 0 & Q’ = 1 : reset state
 when R & S both 1: Q = Q’ = 0
S Q if both inputs changed to 0 then
the device will enter undefined,
unpredictable, or metastable
state.
 Therefore, S=1 & R=1 is
forbidden
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Storage Elements: Latches
SR Latch
S R Q
R Q Q0
0 0 No change
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S R Q
S Q 0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
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Storage Elements: Latches
 In normal condition, both inputs remain at 0 until the state
has to be changed.
 The application of 1 to S will put the latch in to Set state & it
(S) has to return to zero before changing to another state.
 Making both inputs 0 will hold the previous state, this should
be the state before the application of another input.
 The reverse is true for latches with NAND gates.

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 Storage Elements: Latches
SR Latch with Control Input (gated SR latch)
S S
The operation of the basic SR latch can Q
be modified by providing an additional C
input signal that determines (controls) R Q
R
when the state of the latch can be changed
by determining whether S and R (or S’ C S R Q
and R’ ) can affect the circuit. 0 x x Q0 No change
R R 1 0 0 Q0 No change
Q Reset
1 0 1 0
C
1 1 0 1 Set
S Q
S 1 1 1 Q=Q’ Invalid
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 Storage Elements: Latches
D-Latches

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 Storage Elements: Latches
D-latch (Transparent latch):
 To eliminate the undesirable condition of the indeterminate
state in the SR latch is to ensure that inputs S and R are never
equal to 1 at the same time.
D- latch has two inputs: D S
oData input Q
oEnable/control input C
R Q

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Storage Elements: Latches
D-latch

Function table
Logic diagram

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 Storage Elements: Latches
D-latch

• The output follows changes in the data input as long as the enable
input is asserted (En = 1), the latch is said to be open.
• This provides a path from input D to the output, therefore, the
circuit is often called a transparent latch.
• When the enable input signal is de-asserted (En = 0), the binary
information that was present at the data input at the time the
transition occurred is retained (i.e., stored) at the Q output until
the enable input is asserted(En = 1) again.

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Storage Elements: Latches
Graphic symbols for latches

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Latches
74LS279
SR latch, active low

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 Storage Elements: Flip-flops
 A state of a latch is changed
based on a change in control
input. The change is called
trigger. D S
Q
 The D-latch with pulses in its
C
control input is triggered
R
whenever the C goes to level 1. Q

 As long as C is 1, any change in

D will change the state &
output of the latch.
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Storage Elements: Flip-flops
• Latches use level variations of the control input to process the
input data.
• Serious problem if its output is connected to the combinational
ckts. Why?
• b/c of unreliable output, latches can not be directly connected to
combinational circuit or another latch.
• Therefore, edge triggering preferred i.e. flip-flops

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Positive Edge Triggered S’R’ Flip-flop

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Storage Elements: Flip flops
Two ways to modify latches to form a flip flop:
1. To connect two latches serially (master-slave)
• Isolates the output flip flop from the input flip flop preserves
from changing with the input ff.
2. To produce a flip flop that triggers only signal transition (1 to 0
or 0 to 1) of the synchronizing clock and disabled during the
rest.

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 Storage Elements: D-Flip flops
Master-Slave D Flip-Flop

D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C
Master Slave
CLK CLK

QMaster

QSlave
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Storage Elements: D-Flip flops
The behavior of the master–slave flip-flop:
1. The output may change only once,
2. A change in the output is triggered by the negative or
positive edge of the clock.
The value that is produced at the output of the flip-flop is the value that
was stored in the master stage immediately before the negative edge occurred
(for the above negative triggered flip flop).

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 Storage Elements: D-Flip flops
Edge-Triggered D Flip-Flop

S
Q Q
CLK
D Q
Q
R Positive Edge

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Storage Elements: Flip flops
• When the input clock in the positive-edge-triggered flip-flop
makes a positive transition, the value of D is transferred to Q .
A negative transition of the clock (i.e., from 1 to 0) does not
affect the output, nor is the output affected by changes in D
when Clk is in the steady logic-1 level or the logic-0 level.
Therefore, this type of flip-flop responds to the transition
from 0 to 1 and nothing else.

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 Storage Elements: D-Flip flops
 The dynamic indicator (>)
denotes the fact that the flip-flop
responds to the edge transition
of the clock.

Positive-edge Negative-edge

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Other Flip-Flops
 There are three operations that can be performed with a flip-flop:
Set it to 1, reset it to 0, or complement its output.
 With only a single input, the D flip-flop can set or reset the
output, depending on the value of the D input immediately before
the clock transition.
 D flip flops are the most economical, since they require smallest
number of gates.
 Other logics can be constructed with D flip-flop and other logic
gates.
 JK, T flip flops are less common.

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 Other Flip-Flops
JK Flip-Flop (less widely used)

J
D Q Q
K
CLK Q Q

J Q
D = JQ’ + K’Q Clk
K Q
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Other Flip-Flops
T Flip-Flop (Toggle flip flop)

T J Q D Q
T

K Q Q

T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q Q

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Flip-Flop Characteristic Tables
• A characteristic tables define the logical properties of a flip-flop by
describing its operation in tabular form.
• They define the next state (i.e., the state that results from a clock
transition) as a function of the inputs and the present state.
• Note that the clock edge input is implied to occur between t & t + 1.
• Q(t) denotes the state of the flip-flop immediately before the
clock edge.
• Q(t + 1) denotes the state that results from the clock transition.

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Flip-Flop Characteristic Tables
Note: D flip-flop doesn’t
D Q D Q(t+1) have no change condition.
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q Toggle
1 Q’(t)
36
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 Flip-Flop Characteristic Equations
• The logical properties of a flip-flop can be expressed algebraically
with a characteristic equation.
D flip flop:
Q(t+1) = D
JK flip flop:
Q(t+1) = JQ’ + K’Q
T flip flop:
Q(t+1) = T’Q + TQ’

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Direct Inputs
• Some flip-flops has some kind of input that puts them to a
particular state irrespective of the clock, these inputs are called
asynchronous inputs.
• Inputs that set the flip-flop to 1 is called preset or direct set.
• Inputs that clears the flip-flop to 0 is called clear or direct reset.
• When power is turned ON in a digital system, the state of the
flip-flops is unknown.
The direct inputs are used to bring all flip-flops in the system to
a known starting state prior to the clocked operation.

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 Flip-Flops with Direct Inputs
Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q
R
Reset

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Flip-Flops with Direct Inputs
Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q 1 0 ↑ 0
R 1 1 ↑ 1
Reset

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Flip-Flops with Direct Inputs
Asynchronous Preset and Clear

Preset
PR’ CLR’ D CLK Q(t+1)
PR
1 0 x x 0
D Q

Q
CLR
Reset

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Flip-Flops with Direct Inputs
Asynchronous Preset and Clear

Preset
PR’ CLR’ D CLK Q(t+1)
PR
1 0 x x 0
D Q
0 1 x x 1
Q
CLR
Reset

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Flip-Flops with Direct Inputs
Asynchronous Preset and Clear

Preset
PR’ CLR’ D CLK Q(t+1)
PR
1 0 x x 0
D Q
0 1 x x 1
1 1 0 ↑ 0
Q
1 1 1 ↑ 1
CLR
Reset

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Flip-Flops with Direct Inputs

Reset

1
1

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Analysis of Clocked Sequential Circuits
• Analysis describes what a certain sequential circuits do given a
certain operating condition.
• The behavior of a clocked sequential circuit is determined from the
input, output and the state of the flip-flops.
• The output & the next state = f(current input, current state)
• Analysis of sequential circuit is obtaining a table or diagram for
the time sequence of inputs, outputs and present states.
• (if we want to derive Boolean equations the time sequence has to be
specified in the equation)
• A logic diagram is recognized as a clocked sequential circuit if it
includes flip-flops with clock inputs.
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 Analysis of Clocked Sequential Circuits
Algebraic Representation: for specifying the next state condition in
terms of present state & present input.
State table & state diagram: to describe the behavior of the
sequential circuit.
State Equations: the behavior of a clocked Sequential circuit can be
described algebraically by state equations (also called transition equation).
• It describes the next state as a function of the present states and
inputs.

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 Analysis of Clocked Sequential Circuits
State =Values of all Flip-Flops
Eg: Zero detector
AB = 01 x
D Q A
 The two flip flops determine
the next state (after the Q

clock transition)
D Q B

CLK Q

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 Analysis of Clocked Sequential Circuits
State Equations
A(t+1) = DA
x
D Q A
= A(t) x(t)+B(t) x(t)
= Ax + B x Q

B(t+1) = DB
D Q B
= A’(t) x(t)
CLK Q
= A’ x
y(t) = [A(t)+ B(t)] x’(t) y

= (A + B) x’
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Analysis of Clocked Sequential Circuits
State table: the time sequence of inputs, outputs and flip flop states
can be enumerated in a state table (transition table).
State tables usually consists of four sections:
 Input section: shows all the possible input values for the present
state.
 Present-state section: shows the states of the flip flops at any given
time, t.
 Next-state section: shows the states of the flip flops at time t+1
 Output section: shows the values of the output at any given time, t.
The derivation requires the list of all possible values of present state and
input values.
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Analysis of Clocked Sequential Circuits
State Table (Transition Table)
x
D Q A
Present Next
Input Output
State State Q
A B x A B y
0 0 0 0 0 0 D Q B
0 0 1 0 1 0
CLK Q
0 1 0 0 0 1
0 1 1 1 1 0 y

1 0 0 0 0 1
1 0 1 1 0 0 A(t+1) = A x + B x
1 1 0 0 0 1
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t t+1 t ECEG-3121 50
Analysis of Clocked Sequential Circuits
State Table (Transition Table)
x
D Q A

Present Next State Output

Q
State x=0 x=1 x=0 x=1
A B A B A B y y
D Q B
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0 CLK Q

1 0 0 0 1 0 1 0 y
1 1 0 0 1 0 1 0

A(t+1) = A x + B x
t t+1 t
B(t+1) = A’ x
y(t) = (A + B) x’
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Analysis of Clocked Sequential Circuits
State diagram
The information in the state table can be presented in a diagram
(called state diagram).
In state diagram:
• state is presented as a circle.
• The state transitions (clock trigerred) are represented by
directed line connecting the circles (states).

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Analysis of Clocked Sequential Circuits
State Diagram Present Next State Output
State x=0 x=1 x=0 x=1
A B A B A B y y
AB input/output
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0
1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0

00 10
x
D Q A

0/1 Q

1/0 0/1 1/0

D Q B

CLK Q

01 11 y

1/0 ECEG-3121 53
Analysis of Clocked Sequential Circuits
D Flip-Flops
Example: x D Q A
y
Present Next
Input
State State CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A  x  y
0 1 0 1
0 1 1 0
01,10
1 0 0 1
1 0 1 0 00,11 0 1 00,11
1 1 0 0
1 1 1 1 01,10
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Analysis of Clocked Sequential Circuits
JK Flip-Flops J Q A

Example: x K Q

Present Next Flip-Flop

I/P J Q B
State State Inputs
A B x A B J A KA J B KB K Q
0 0 0 0 1 0 0 1 0 CLK
0 0 1 0 0 0 0 0 1 JA = B KA = B x’
0 1 0 1 1 1 1 1 0 JB = x’ KB = A  x
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 A(t+1) = JA Q’A + K’A QA
1 0 1 1 0 0 0 0 0 = A’B + AB’ + Ax
1 1 0 0 0 1 1 1 1 B(t+1) = JB Q’B + K’B QB
1 1 1 1 1 1 0 0 0 = B’x’ + ABx + A’Bx’
55
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Analysis of Clocked Sequential Circuits
A
JK Flip-Flops J Q

x K Q
Example:
J Q B
Present Next Flip-Flop
I/P
State State Inputs K Q

A B x A B J A KA J B KB CLK

0 0 0 0 1 0 0 1 0
1 0 1
0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0 00 11
0 1 1 1 0 1 0 0 1
0
1 0 0 1 1 0 0 1 1 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1 1 1 1 1 1 0 0 0 1
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 Analysis of Clocked Sequential Circuits
T Flip-Flops x T Q
A
y

Example: R Q

Present Next F.F

I/P O/P
State State Inputs
T Q
A B x A B TA TB y B

0 0 0 0 0 0 0 0 R Q
0 0 1 0 1 0 1 0
CLK Reset
0 1 0 0 1 0 0 0
0 1 1 1 0 1 1 0 TA = B x TB = x
1 0 0 1 0 0 0 0 y =AB
1 0 1 1 1 0 1 0 A(t+1) = TA Q’A + T’A QA
1 1 0 1 1 0 0 1 = AB’ + Ax’ + A’Bx
1 1 1 0 0 1 1 1 B(t+1) = TB Q’B + T’B QB
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Analysis of Clocked Sequential Circuits
x A
T Q
T Flip-Flops y

Example: R Q

Present Next F.F

I/P O/P T Q
State State Inputs B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset

0 1 0 0 1 0 0 0 0/0 0/0
0 1 1 1 0 1 1 0 00 1/0 01
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0 1/1 1/0
1 1 0 1 1 0 0 1 11 10
1 1 1 0 0 1 1 1 0/1 1/0 0/0
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