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Calibration Techniques in ADCs

Ahmed M. A. Ali
Analog Devices, Inc.

Live Q&A Session: Feb. 13, 2021, 8:20-8:40am, PST


Self Introduction
 B.SC. and M.Sc. from Ain Shams University in Cairo, Egypt

 Ph.D. from the University of Pennsylvania

 Fellow at Analog Devices

 Work on high-speed data converters and digital-assistance


algorithms

 Author of “High Speed Data Converters”, published in


2016 by the Institution of Engineering & Technology (IET)

Ahmed Ali Calibration Techniques in ADCs 2


Outline
 Introduction to data converters

 Performance metrics of data converters

 Pipelined ADCs and their non-idealities

 Some ADC calibration techniques (Digitally assisted A/D converters)


 Impairments of pipelined ADCs as an example of multi-step ADCs
 Correlation-based (dither-based) calibration techniques

Ahmed Ali Calibration Techniques in ADCs 3


Data Converters

Continuous-time Discrete-time
Continuous-amplitude Discrete-amplitude

x(t) xq[n]
ADC
Analog Digital
Realm Realm
x(t) xq[n]
DAC

Real World Processing World


Ahmed Ali Calibration Techniques in ADCs 4
Applications

Wireless Communication
Defense
Medical
Wired Communication
Satellite
Instrumentation

Video Automative
IoT Radar
Ahmed Ali Calibration Techniques in ADCs 5
Data Converters (Multi-Disciplinary)

x(t) xq[n]
Analog Circuit Design ADC Digital Circuit Design

- Amplifiers and buffers x(t) xq[n] - Digital processors


- Samplers
DAC - Digital filters
- Integrators and filters - Digital up/down converters
- Comparators - Multi-rate processing
- References - Adaptive signal processing
- Clocks and PLLs Algorithms - Digital linearization
- Analog signal processing Signal Processing - System identification
- Analog linearization - Digitally-assisted analog
Software

Ahmed Ali Calibration Techniques in ADCs 6


A/D Converter (ADC)

x(t) xq[n]
Amplitude
xq[n]
ADC

Δ x(t)

x[n]

x(t) x[n] xq[n]


Sampler Quantizer
Ts 2Ts 3Ts 4Ts 5Ts 6Ts Time

Sampling Rate: fs=1/Ts ADC


Resolution N: Δ=VFS/2N
Ahmed Ali Calibration Techniques in ADCs 7
Ideal A/D Converter Quantizer
ADC Output

 ADC Output =
Step Size Δ

 Where:
 [x] is the integer value closest
to x
 N is the number of bits Vin

-VRef VRef
 Vin is the analog input signal
 VRef is the ADC reference
voltage
 Usually in fully differential Quantization
ADCs: Error

 VFS = 2VRef Δ/2=LSB/2


Vin
 The step size Δ is given by:
-VRef VRef
 Δ= VFS/2N −Δ/2=-LSB/2

Ahmed Ali Calibration Techniques in ADCs 8


PERFORMANCE METRICS

Ahmed Ali Calibration Techniques in ADCs 9


Common ADC Performance Metrics

 Sampling Rate  Integral Non-linearity (INL)


Define the converter
 Resolution  Differential Non-linearity (DNL)
 Signal-to-Noise Ratio (SNR)  Offset error
 Signal-to-Noise-and-Distortion  Gain Error
Ratio (SNDR or SINAD)  Bit-Error-Rate (BER)
 Noise Spectral Density (NSD)  Power consumption
 Spurious-Free Dynamic Range  Clock jitter
(SFDR)  Input bandwidth
 Total Harmonic Distortion (THD)  Input impedance
 Inter-modulation Distortion  Input full-scale range
(IMD)

Ahmed Ali Calibration Techniques in ADCs 10


Signal-to-Noise Ratio[1]
• SNR/SINAD are defined as the ratio
of the signal power to the noise
power excluding DC: Signal
• SNR (dBc) = 10log(Signal Power /
Noise Power)
• SINAD/SNDR (dBc) = 10log(Signal
Power / (Noise + Distortion Power))

dB
• SNR (dBFS) = 10log(ADC FS Power /
Noise Power) Noise +
• SINAD/SNDR (dBFS) = 10log(ADC
Distortion
FS Power / (Noise + Distortion
Power))

• NSD is the noise spectral density in


dB/Hz:
• NSD=-SNR-10log(fs/2)
Frequency
Ahmed Ali Calibration Techniques in ADCs 11
Spurious-Free-Dynamic-Range [1]

Signal Power
𝑆𝐹𝐷𝑅(dBc) = 10 log
Worst Harmonic or Spur Power

ADC Full Scale Power


𝑆𝐹𝐷𝑅(dBFS) = 10 log SFDR SFDR
Worst Harmonic or Spur Power
(dBc) (dBFS)

dB
Frequency

Ahmed Ali Calibration Techniques in ADCs 12


Ideal Quantizer

Shown:
• Offset = 0
• Gain error = 0
• DNL = 0
• INL = 0

• The DNL and INL


capture the deviation
of the transfer
characteristic from
the ideal stair-case

Ahmed Ali Calibration Techniques in ADCs 13


Non-Ideal Quantizer
Shown:
• Offset
• Gain error
• DNL
• INL

• Poor large signal


non-linearity (INL)
• Poor small signal
non-linearity (DNL)

Ahmed Ali Calibration Techniques in ADCs 14


INL with Inter-stage Gain Error [1]
Direction of missing codes

8
64000
Output (Code) Codes

Error LSB
(LSB)

-8

Ahmed Ali Calibration Techniques in ADCs 15


INL with Sub-LSB Error [1]

2
Output (Code) 16000
Codes

Error
LSB
(LSB)

-2

Ahmed Ali Calibration Techniques in ADCs 16


PIPELINED ADCS

Ahmed Ali Calibration Techniques in ADCs 17


Flash A/D Converter
 Compares input to all threshold
levels simultaneously

 Very high speed (fs ~ GS/s):

 Not efficient for high resolutions:


 Area & Power α 2N

 Limited accuracy: (≲ 6bit)

 For higher resolutions, multi-step


ADCs are usually used
Ahmed Ali Calibration Techniques in ADCs 18
Pipelined A/D Converter
Ts

Accuracy
not
critical

D1 = 0, ±1, ±2, ±3 …, ±2k1-1


𝑉 =𝐺 𝑉 −𝑉 𝐺 =2
𝐷 ·𝑉
𝑉 =𝐺 𝑉 −
2
Ahmed Ali Calibration Techniques in ADCs 19
NON-IDEALITIES IN PIPELINED
ADCS
Ahmed Ali Calibration Techniques in ADCs 20
Inter-stage Gain Errors

 In pipeline and pipe-SAR


ADCs

 Due to non-ideal gain in the


inter-stage amplifier

 Leads to breaks in the


transfer characteristics

Ahmed Ali Calibration Techniques in ADCs 21


Inter-stage Gain Errors

 In pipeline and pipe-SAR


ADCs

 Due to non-ideal gain in the


inter-stage amplifier

 Leads to breaks in the


transfer characteristics

Ahmed Ali Calibration Techniques in ADCs 22


INL with Inter-stage Gain Error [1]
Direction of missing codes

8
64000
Output (Code) Codes

Error
LSB

(LSB)

n1~3, n~13
SFDR~6n+3n1~87dB*
-8
* H. Pan and A.A. Abidi, ‘‘Spectral Spurs due to Quantization in Nyquist ADCs,’’ IEEE Trans. Circuits and Systems-I: Regular
Papers, 51(8), pp. 1422–1438, August 2004.
Ahmed Ali Calibration Techniques in ADCs 23
Example: FFT with IGE Errors [1]
SNR~75dB, SFDR~86dB

Hz

SFDR
dB

-86dB

n1~3, n~13
SFDR~6n+3n1~87dB

Ahmed Ali Calibration Techniques in ADCs 24


Effect of INL Sawtooth Error on SFDR*
At 0dBFS, SFDR ~ 86dB

n1~3, n~13
SFDR~6n+3n1~87dB

* A.M.A. Ali, High speed data converters, Institution of Engineering and Technology (IET), London, UK, 2016.
Ahmed Ali Calibration Techniques in ADCs 25
Effect of INL Sawtooth Error on SFDR*
At -6dBFS, SFDR ~ 84dB

n1~2, n~13
SFDR~6n+3n1~84dB

* A.M.A. Ali, High speed data converters, Institution of Engineering and Technology (IET), London, UK, 2016.
Ahmed Ali Calibration Techniques in ADCs 26
Effect of INL Sawtooth Error on SFDR*
At -18dBFS, SFDR ~ 78dB

n1~0, n~13
SFDR~6n+3n1~78dB

* A.M.A. Ali, High speed data converters, Institution of Engineering and Technology (IET), London, UK, 2016.
Ahmed Ali Calibration Techniques in ADCs 27
First Stage Residue with Stage DAC Error

 In pipeline and
pipe-SAR ADCs

 Due to non-
idealities in the
stage DAC

 Leads to breaks
in the transfer
characteristics

Ahmed Ali Calibration Techniques in ADCs 28


First Stage Residue with Stage DAC Error

 In pipeline and
pipe-SAR ADCs

 Due to non-
idealities in the
stage DAC

 Leads to breaks
in the transfer
characteristics

Ahmed Ali Calibration Techniques in ADCs 29


INL Showing DAC Errors [1]

Error
(LSB)

Ahmed Ali Calibration Techniques in ADCs 30


Low Order Harmonic Distortion

 Poor large signal non-linearity

 Harmonic distortion is
generated in the frontend

 Third order compressive non-


linearity

Ahmed Ali Calibration Techniques in ADCs 31


INL Showing 3rd Order Non-Linearity [1]

Codes

Error
(LSB)

Ahmed Ali Calibration Techniques in ADCs 32


FFT Showing HD3 Non-linearity [1]

Ahmed Ali Calibration Techniques in ADCs 33


Memory and kick-back errors [1, 2]
0 8000 16000 Codes

4.5 LSB
Error

-4.5 LSB

Ahmed Ali Calibration Techniques in ADCs 34


Memory and kick-back errors [1, 2]
0dB 500MHz

dB
-75dB

Ahmed Ali Calibration Techniques in ADCs 35


CALIBRATION TECHNIQUES:
DIGITALLY-ASSISTED CONVERTERS

Ahmed Ali Calibration Techniques in ADCs 36


Why Calibration? Process Scaling
 Digital circuits have become more efficient with process scaling
 Analog circuits get more challenging and can be even less efficient
 In planar processes, finer geometry gives:
 Faster switches
 Lower parasitics
 But …
 Lower output impedance
 Lower intrinsic gain
 Worse dynamic range
 FinFETs are more analog friendly, but are not getting faster
 Digital processing can be used to correct for analog and interleaving non-
idealities

Ahmed Ali Calibration Techniques in ADCs 37


Calibration Types and Components
 Using a combination of Mixed-signal Linearization
analog and digital signal
processing Analog
Control Circuit
 Correction and estimation
 Foreground Calibration Analog Linearization
 Fixed
 May need an input stimulus Digital
Input ADC
 Background Calibration Calibration
 Converters can measure
their own performance
without disrupting normal
operation and adaptively fix Digital Linearization
their non-idealities
 Tracks process, supply,
temperature, aging, etc.
Ahmed Ali Calibration Techniques in ADCs 38
Real World Challenges
 Improve performance and lower power consumption

 No disruption to normal operation => background


 Combine foreground and background calibrations as needed

 Robustness with input amplitude, input frequency, sample rate, supply,


temperature, etc.

 Convergence time

 Manufacturability

Ahmed Ali Calibration Techniques in ADCs 39


ADC Impairments
 Quantizer impairments:
 Inter-stage gain and settling errors (IGE)
 Inter-stage memory errors (IME)
 DAC errors
 Reference errors
 MDAC amplifier non-linearity
 Sample-and-hold impairments:
 Kick-back errors
 Front-end non-linearity
 Interleaving impairments:
 Offset and gain mismatch errors
 BW/timing mismatch errors

Ahmed Ali Calibration Techniques in ADCs 40


ADC Impairments
 Quantizer impairments:
 Inter-stage gain and settling errors (IGE)
 Inter-stage memory errors (IME)
 DAC errors
 Reference errors
 MDAC amplifier non-linearity
 Sample-and-hold impairments:
 Kick-back errors
 Front-end non-linearity
 Interleaving impairments:
 Offset and gain mismatch errors Not covered in this tutorial
 BW/timing mismatch errors

Ahmed Ali Calibration Techniques in ADCs 41


Digital Error Correction [1]

Vin + Vo1 + Vo2 kn-bit


S/H G1 S/H G2
ADC
- -
kn bits
k1-bit k1-bit k1-1 k2-bit k2-bit k2-1 LSB
DAC
G1 = 2 ADC DAC
G2 = 2
ADC

k1 bits
MSBs
MDAC1
k2 bits
D1 D2 Dn

k1 bits k2 bits k3 bits kn bits

D(Vo1) D(Vo2)
G1-1 G2-1 Gn-1-1

D(Vin)=Dout
Digital Error Correction

N bits

Ahmed Ali Calibration Techniques in ADCs 42


Calibration Techniques
 Correlation-based (dither-based) calibration [15, 2, 5, 8-
11]

 Calibration techniques not covered in this tutorial:

 Using reference ADC [16, 17]

 Split ADC method [18]

 Summing node calibration [3, 14]

 Using statistical methods [19-21]

Ahmed Ali Calibration Techniques in ADCs 43


Calibration of ADC Impairments [15, 2]
 Quantizer impairments:
 Inter-stage gain and settling errors (IGE)
 Inter-stage memory errors (IME)
 DAC errors
Output (Code)
 Reference errors
 MDAC amplifier non-linearity
Error
 Sample-and-hold impairments:
(LSB)
 Kick-back errors
 Front-end non-linearity
 Interleaving impairments:
 Offset and gain mismatch errors
 BW/timing mismatch errors INL Plot

Ahmed Ali Calibration Techniques in ADCs 44


Calibration of ADC Impairments [15, 2]
 Quantizer impairments:
 Inter-stage gain and settling errors (IGE)
 Inter-stage memory errors (IME)
 DAC errors
 Reference errors
 MDAC amplifier non-linearity
 Sample-and-hold impairments:
 Kick-back errors
 Front-end non-linearity
 Interleaving impairments:
 Offset and gain mismatch errors
 BW/timing mismatch errors

Ahmed Ali Calibration Techniques in ADCs 45


Calibration of ADC Impairments [10, 11, 2]
 Quantizer impairments:
 Inter-stage gain and settling errors (IGE)
 Inter-stage memory errors (IME)
 DAC errors 4.5 LSB Output (Code)
 Reference errors
 MDAC amplifier non-linearity

Error
 Sample-and-hold impairments:
 Kick-back errors
 Front-end non-linearity
 Interleaving impairments:
 Offset and gain mismatch errors
-4.5 LSB
 BW/timing mismatch errors
INL Plot

Ahmed Ali Calibration Techniques in ADCs 46


Calibration of ADC Impairments [10, 11, 2]
 Quantizer impairments:
 Inter-stage gain and settling errors (IGE)
 Inter-stage memory errors (IME)
 DAC errors
 Reference errors Hz
 MDAC amplifier non-linearity
 Sample-and-hold impairments:
 Kick-back errors

dB
 Front-end non-linearity -75dB
 Interleaving impairments:
 Offset and gain mismatch errors
 BW/timing mismatch errors

Ahmed Ali Calibration Techniques in ADCs 47


Correlation-Based Calibration
Dither Dither
PN Generator 1 PN Generator 2
DAC1 DAC2

Uncorrelated
Buffer

Vin + + kn-bit
G1 S/H G2
ADC
- -
kn bits
k1-bit k1-bit G1 = 2 k1-1 k2-bit k2-bit G2 = 2 k2-1 LSB
ADC DAC ADC DAC

k1 bits
MSBs
MDAC1
k2 bits

Digital Error Correction

N bits

Ahmed Ali Calibration Techniques in ADCs 48


Simplified Multiplying DAC (MDAC)
 The MDAC
performs input -VRef
sampling, DAC, x8
D’.φ2 Cf=2C
subtraction, and
inter-stage φ1 Ci=C x8
Vin -Vout/A
amplification Vout
φ1a φ1
 Show is a 3-bit D.φ2 x8
MDAC with φ2
shared VRef A
capacitances φ1

φ1a
Ahmed Ali Calibration Techniques in ADCs 49
The IGE/IME Calibration [15, 2, 10, 11]
-VRef
 Dither is injected in the MDAC D’.φ2
x8 Cf=2C
 It encounters the IGE and IME φ1 Ci=C x8
Vin
errors Vout
 Correlation is used in the digital D.φ2
φ1a φ1
x8
domain to estimate the errors
 Mismatches between the dither VRef
path and the signal path can limit
accuracy Ddith’.φ2

 Long convergence time φ1 Cd

 Can be relatively input signal Vd


independent Ddith.φ2

-VRef
Ahmed Ali Calibration Techniques in ADCs 50
The IGE/IME Calibration [15, 2, 10, 11]
• IGE: k=0, IME: k>0
• Estimation (for each k separately):
𝐺𝑒 [𝑛 + 1] = 𝐺𝑒 [𝑛] +

𝜇 × 𝐷 [𝑛 − 𝑘] × (𝐷 𝑛 − 𝐷 𝑛 − 𝑘 × 𝐺𝑒 −𝐷 𝑛 )

• BG Correction:
𝐷 _ 𝑛 =𝐷 𝑛 − (𝐷 [𝑛 − 𝑘] × 𝐺𝑒 ) − 𝐷 𝑛

• FG Correction:
𝐷 _ _ [𝑛] = 𝐷 _ [𝑛] × 𝐺𝑒 LMS: Least Mean Square Algorithm

Ahmed Ali Calibration Techniques in ADCs 51


Kick-back Background Calibration [1, 2]
-VRef

x8 Cf = 2C
D’.φ2
 The kick-back dither
φ1 Ci = C x8
caps kick the input Vin
Vout
similar to the sampling φ1a φ1
capacitances’ kick D.φ2 x8

VRef
 The dither’s kick is
sampled on the total D_dith’.φ2

capacitances and φ1 Cd

propagates down the No resetting


Vd
pipeline D_dith.φ2 is needed
-VRef

Ahmed Ali Calibration Techniques in ADCs 52


Kick-back Background Calibration [1, 2]
 The LMS algorithm is used to estimate the gain/correction
coefficient Gkb of the dither’s kick of the previous sample(s)
 The correction coefficient Gkb is applied to the previous stage-1
flash bits
 Conceptually:

𝐺𝑘𝑏 𝑛 + 1 = 𝐺𝑘𝑏 𝑛 + 𝜇 × 𝐷 [𝑛 − 𝑘] × (𝐷 𝑛 − 𝐷 [𝑛 − 𝑘] × 𝐺𝑘𝑏 [𝑛])

𝐷 _ 𝑛 =𝐷 𝑛 + 𝐷 𝑛 − 𝑘 × 𝐺𝑘𝑏′ − 𝐷𝑑[𝑛 − 𝑘] × 𝐺𝑘𝑏

Ahmed Ali Calibration Techniques in ADCs 53


Input Amplitude Sweep with IGE (SFDR)

Ahmed Ali Calibration Techniques in ADCs 54


Input Amplitude Sweep with IGE (SNDR)

Ahmed Ali Calibration Techniques in ADCs 55


INL without Kick-back Calibration [1, 2]
0 8000 16000 Codes

4.5 LSB
Error

-4.5 LSB

Ahmed Ali Calibration Techniques in ADCs 56


INL with Kick-back Calibration [1, 2]
0 8000 16000 Codes

4.5 LSB

1.5 LSB
Error

-1.5 LSB

-4.5 LSB

Ahmed Ali Calibration Techniques in ADCs 57


FFT without kick-back calibration
0dB 500MHz

dB
-75dB

Ahmed Ali Calibration Techniques in ADCs 58


FFT with kick-back calibration
0dB 500MHz

dB
-75dB

Ahmed Ali Calibration Techniques in ADCs 59


Calibration of ADC Impairments [8, 5]
 Quantizer impairments:
 Inter-stage gain and settling errors (IGE)
 Inter-stage memory errors (IME) Output (Code)
 DAC errors
 Reference errors
 MDAC amplifier non-linearity
 Sample-and-hold impairments:
Error
 Kick-back errors
(LSB)
 Front-end non-linearity
 Interleaving impairments:
 Offset and gain mismatch errors INL Plot
 BW/timing mismatch errors

Ahmed Ali Calibration Techniques in ADCs 60


Calibration of ADC Impairments [20, 8, 9, 5]
 Quantizer impairments:
 Inter-stage gain and settling errors (IGE)
 Inter-stage memory errors (IME)
 DAC errors
 Reference errors
 MDAC amplifier non-linearity
 Sample-and-hold impairments: Codes
 Kick-back errors
 Front-end non-linearity
Error
 Interleaving impairments: (LSB)
 Offset and gain mismatch errors
 BW/timing mismatch errors

Ahmed Ali Calibration Techniques in ADCs 61


Quantization Non-linearity (INL Breaks)
ADC Output ADC Output

Δ4

Δ3

Δ2

Δ1
Input Input

Δ1

Δ2

Δ3

Δ4

Inter-stage Gain Error (IGE) DAC/Reference Errors


Ahmed Ali Calibration Techniques in ADCs 62
INL Breaks and Harmonic Distortion (HD)
ADC Output ADC Output

Δ4

Δ3
Δ3 Δ2

Δ2
Δ1
Δ1 Input Input
Δ5

Δ6 Δ4

Δ7 Δ5
Δ6
Δ8

INL breaks and inter-stage HD INL breaks, inter-stage and overall HD


Ahmed Ali Calibration Techniques in ADCs 63
Dither-based Non-linearity Calibration [20,8,9,5]
+/−𝑉 , 0 +/−𝑉 , 0
 𝑦 =𝑓 𝑥+𝑉 −𝑉
Non-linear function
 𝑦 =𝑓 𝑥−𝑉 +𝑉 𝑦
 Error = y1 - y2
 Use thresholded LMS-like
counting/correlation over 1
half-bounded open Dinsp

Normalized Output
-Dinsp
intervals to estimate the
error
 Calibrates harmonic
distortion

Normalized Input 1
-1
Ahmed Ali Calibration Techniques in ADCs 64
Dither-based Non-linearity Calibration [5]
+/−𝑉 , 0 +/−𝑉 , 0
 𝑦 =𝑓 𝑥+𝑉 −𝑉
 𝑦 =𝑓 𝑥−𝑉 +𝑉 𝑦
 Error = y1 - y2
 Use thresholded LMS-

Normalized Output
like counting/correlation Dinsp
over half-bounded open
intervals to estimate the
error
 Calibrates INL breaks

Normalized Input
Ahmed Ali Calibration Techniques in ADCs 65
Estimation of Non-linear Coefficients [5]

𝐷 =𝑓 (𝐷 )

𝐷 =∝ 𝐷 + ∝ _ · 𝑓𝑙 = 𝑠𝑢𝑏( )
∝ 𝑛 + 1 =∝ 𝑛 − 𝜇 × 𝜀

𝐷 =∝ 𝐷 + 𝑃𝑊𝐿( ∝ 𝐷 + higher order terms)

Ahmed Ali Calibration Techniques in ADCs 66


Harmonic Distortion Inspection Points [20, 5]
𝜀 =𝜀 𝐷 / − 𝜀 −𝐷 / 𝜀 =𝜀 𝐷 / + 𝜀 −𝐷 /

3rd order NL
Normalized Output

2nd order NL

Odd Symmetry about y axis Even Symmetry about y axis


Normalized Error

𝜀 −𝐷 /

𝜀 𝐷 /
𝜀 𝐷 /

-Dinsp2/3 Normalized Input Dinsp2/3 -Dinsp2/3 Normalized Input Dinsp2/3

Ahmed Ali Calibration Techniques in ADCs 67


Dither Added with and without INL Breaks
Inspection Points for INL Breaks
1
► Red: Dd>0 Points where dither changes the sub-range
1
► Blue: Dd<0

Output-dither
Output-dither

► No Errors ► With Errors


-1
×
-1
-1 Normalized Input 1 -1 Normalized Input 1
Ahmed Ali Calibration Techniques in ADCs 68
Locating Inspection Points in Real Time [5,4]
Max point Dd<0

Output-dither
for subrange n
FS/2 Dinsp_8
► Red: Dd>0 Dinsp_7
Output-Dither

► Blue: Dd<0 Dinsp_6


Dinsp_5
Dinsp_4
Dinsp_3 Overlap region
Normalized Input
Dinsp_2 Min point Dd>0
Dinsp_1 for subrange n+1
-FS/2 ► With Errors

1 2 3 4 5 6 7 8 9
Flash Code (sub-range)
Ahmed Ali Calibration Techniques in ADCs 69
Example of DAC/Ref Non-linearity Calibration

Fs=3GS/s, SNR~53dB, SFDR~55dB Fs=3GS/s, SNR~60dB, SFDR~75dB

Without non-linearity calibration With non-linearity calibration

Ahmed Ali Calibration Techniques in ADCs 70


Papers to See This Year
 Paper 10.7: “A 64GS/s 4x-interpolated 1b Semi-Digital FIR DAC for Wideband
Calibration and BIST of RF-Sampling A/D-Converters”
 Wideband calibration of ADC non-linearity
 Paper 27.3: “A 13.8-ENOB 0.4pF-CIN 3rd-Order Noise-Shaping SAR in a Single-
Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise
Cancellation”
 Foreground DAC calibration
 Paper 27.6: “A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping
SAR-Assisted Pipeline ADC with Background Offset Calibration”
 Background offset calibration
 Paper 27.2: “14.1 ENOB 184.9 dB FoM Capacitor Array-Assisted Cascaded Charge-
Injection SAR ADC”
 DAC calibration
 Paper 27.7: “A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter
with Noise-Shaping SAR”
 Interleaving and DAC calibration
Ahmed Ali Calibration Techniques in ADCs 71
Conclusion
 Data converters are ubiquitous and an essential building block in
modern communication systems. The performance of the converter
often decides the performance of the whole system

 Some converter performance metrics and non-idealities were


discussed

 Calibration of the IGE, DAC, IME, kick-back, harmonic distortion and


INL breaks are examples of using digital signal processing to improve
the analog performance

 Digital assistance enables ADC designers to continue building efficient,


accurate and fast ADCs as process geometry shrinks

Ahmed Ali Calibration Techniques in ADCs 72


References
 [1] A.M.A. Ali, High speed data converters, Institution of Engineering and Technology (IET), London, UK, 2016.
 [2] A.M.A. Ali, et al., “A 14b 1GS/s RF sampling pipelined ADC with background calibration”, J. Solid-State Circuits, 49,
no. 12, pp. 2846-2856, Dec. 2014.
 [3] A.M.A. Ali, et al., “A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration”, J. Solid-State
Circuits, 45, no. 12, pp. 2602-2612, Dec. 2010.
 [4] A.M.A. Ali, et al., “A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither”, IEEE VLSI
Symp., 2016.
 [5] A. M. A. Ali et al. “A 12-b 18-GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and
Background Calibration,” IEEE JSSC, 55 (12), pp. 3210-3224, Dec. 2020.
 [6] S. Devarajan, et al. “A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology”, IEEE JSSC, 52 (12),
pp. 3204-3218, Dec. 2107.
 [7] M. Brandolini et al., “A 5GS/s 150mW 10b SHA-Less Pipelined/SAR Hybrid ADC in 28nm CMOS”, ISSCC Dig. Tech.
Papers, pp. 468-469, Feb. 2015.
 [8] A. Panigada and I. Galton, “A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic
distortion correction”, ISSCC Dig. Tech. Papers, pp. 162-163, Feb. 2009.
 [9] N. Rakuljic and I. Galton, “Suppression of Quantization-Induced Convergence Error in Pipelined ADCs with Harmonic
Distortion Correction”, IEEE Trans. Circuits and Systems I, 60(3), pp. 593-602, March 2013.
 [10] A.M.A. Ali, “Methods and structures that reduce memory effects in analog-to-digital converters”, US Patent No
6,861,969. March, 2005.
 [11] J.P. Keane, “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters”, IEEE
TCAS-I, March, 2006.

Ahmed Ali Calibration Techniques in ADCs 73


References (cont.)
 [12] A.M.A. Ali and A. Morgan, “Calibration methods and structures for pipelined converter systems”, US Patent
8,068,045, November, 2011.
 [13] A.M.A. Ali, et al., “Correlation-based background calibration of pipelined converters with reduced power penalty”,
US Patent 7,786,910, August, 2010.
 [14] A.M.A. Ali, “Pipelined converter systems with enhanced accuracy”, US Patent 7,271,750, September, 2007.
 [15] E. Siragusa and I. Galton, “A Digitally Enhanced 1.8-V 15-bit 40-MSample/s CMOS Pipelined ADC,” IEEE J. Solid
State Circuits, vol. 39, Dec. 2004.
 [16] S. Sonkusale, et al., “True background calibration technique for pipelined ADC”, Electronic Letters, pp. 786-788,
36(9), 2000.
 [17] Y. Chiu et al., “Least Mean Square adaptive digital background calibration of pipelined analog-to-digital
converters”, IEEE TCAS-I, Jan. 2004.
 [18] J.A. McNeill et al.,” “Split ADC” Architecture for Deterministic Digital Background Calibration of a 16-bit 1-MS/s
ADC”, IEEE TCAS-I, Dec., 2005.
 [19] E. Iroaga and B. Murmann, “A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling”, J. Solid-State Circuits,
Vol. 42, no. 4, April 2007.
 [20] B. Murmann and B.E. Boser, “A 12 b 75 MS/s pipelined ADC using open-loop residue amplification”, ISSCC Dig.
Tech. Papers, pp. 328 – 497, Vol.1, 2003.
 [21] B. Murmann and B.E. Boser, “Digital Domain Measurement and Cancellation of Residue Amplifier Nonlinearity in
Pipelined ADCs”, IEEE Trans. Inst. Meas., Dec. 2007.

Ahmed Ali Calibration Techniques in ADCs 74

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