Advanced VLSI Design

Dr. Premananda B.S.

BITS Pilani
Pilani Campus
 BITS Pilani
Pilani Campus

MEL ZG623, Advanced VLSI Design

Lecture No. 14
Agenda

• Introduction/Review, Design issues

• Sequential logic circuit
• Dynamic latches and Registers
• Timing issues in clock systems
• Clock generation and distribution
• Asynchronous system design
• Interfacing circuits

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Agenda Contd …

• Wire design principles

• Datapath subsystem design
• High speed computer arithmetic design
• Adders, multipliers, barrel shifter
• Logical efforts
• Optimizing logic circuits
• Deep submicron device engineering
• Scaling theory, geometrical/physical effects

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Reference Books
• Jan M. Rabaey and A. Chandrakasan, “Digital Integrated
Circuits”, 2nd Edition, Prentice Hall Electronics and VLSI
Series.
• Ming-Bo Lin, “Introduction to VLSI systems A logic circuit
and system perspective”, CRC press. Taylor & Francis
Group.
• Neil H. E. Weste, David Harris, and Ayan Banerjee, “CMOS
VLSI Design” 3rd/4th edition, Pearson education.
• John P. Uyemura, “Introduction to VLSI Circuits and
systems” Wiley.
• John P. Uyemura, CMOS Logic Circuit Design Kluwer
Academic Publishers.
• …
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Wire Design Principles
• Electrical wire/Interconnect models
• Transmission Line models
• Parasitic effects of Interconnect
• Capacitive-coupling effects
• Crosstalk
• RLC Effects
• Self-Timed Regenerators
Interconnect
• Interconnect means the wires linking together transistors,
circuits, cell, modules, and systems as well.
• Electrical properties of the interconnect wire are: capacitance,
resistance and inductance.
• These parasitic elements have an impact on the electrical
behavior of the circuit.
• Interconnect in VLSI or digital system controls timing, power,
noise, design functionality, and reliability.
• Interconnect provides power delivery paths, clock delivery
paths, and signal delivery paths.
• Power delivery paths distribute power to every element in the
system and provides appropriate return paths, clock delivery
paths deliver global or local clocks to storage elements.
Interconnect Models
• For multiple-processor systems, a complicated interconnect
network referred as network-on-a chip (NoC) is used.
• The electrical/interconnect models is used to estimate and
approximate the real behavior of a wire.
• A proper interconnect model is needed to represent the wire
as a function of its parameters.
• Models vary from simple to very complex depending upon the
effects that are being studied and the required accuracy.
• The commonly used interconnect models include the:
– Lumped model
– Lumped-RC model
– Distributed-RC model
– Transmission-line model
Lumped Model
• The circuit parasitics of a wire are distributed along its
length and are not lumped into a single position.
• It is often useful to lump the different fractions into a
single circuit element when:
– only a single parasitic component is dominant,
– interaction between the components is small, or
– looking at only one aspect of the circuit behavior
• The advantage is that the effects of the parasitic then
can be described by an ordinary differential equation.
• If resistive component of the wire is small and the
switching frequencies are in the low to medium range,
– consider only the capacitive component of the wire,
and to lump the distributed capacitance into a single
capacitor.

• Distributed versus lumped capacitance model of wire:

– Clumped = L×Cwire
L the length of the wire and Cwire the capacitance per unit length.
– Driver is modeled as a voltage source and a source resistance
Rdriver
• In lumped model, the wire itself does not introduce any
delay.
• The only impact on performance is introduced by the
loading effect of the capacitor on the driving gate.
• The capacitive lumped model is simple, and model is of
choice for the analysis of most interconnect wires in ICs.
• It is useful to present lumped models of a wire with
respect to either resistance and inductance.
• Both the resistance and inductance of the supply wires
can be interpreted as parasitic noise sources that
introduce voltage drops and bounces on the supply rails.
Lumped-RC Model
• The lumped-RC model of a wire is the simplest model.
• The lumped-RC model takes the entire wire as a single
time constant RC circuit and as a combination of an ideal
wire with a single resistor Rwire and capacitor Cwire being
connected at the end of the ideal wire.
• An ideal wire is the one with zero value of resistance and
capacitance.
• If wire length is l, then the wire resistance and capacitance
can be estimated as follows:
Distributed-RC Model
• The distributed-RC model takes the wire as a cascading
of simple RC networks, consisting of a set of segment
resistance and segment capacitance.
• Assume that each segment has a length of ∆l.
• Then each segment has a resistance of Rint∆l and a
capacitance of Cint∆l.
• The total delay of the wire can then be estimated by using the
Elmore delay model as follows:
The Transmission Line
• When the switching speeds of the circuits become fast, and
the quality of the interconnect material become high enough
so that:
– resistance of the wire is kept within bounds,
– inductance of the wire starts to dominate delay behavior,
– transmission line effects must be considered.
• This is the case when the rise and fall times of the signal
become comparable to the time of flight of the signal
waveform across the line as determined by the speed of light.
• With the advent of Copper interconnect and the high switching
speeds enabled by the DSM technologies, transmission line
effects are to be considered in the fastest CMOS designs.
 Transmission-Line Models
• The transmission-line model of a wire can be classified
into the following two types:
1. The lossless transmission line:
• When the wire resistance is small, transmission line
can be simplified to a capacitive/inductive model.
• It is applicable for the wires at the (PCB) level.
2. The lossy transmission line:
• When the wire resistance plays an important role,
transmission line is called lossy transmission line.
• It is applicable to on-chip wires and some thin-film
package wires.
Simulation Models
• To simplify the simulation work for a wire, we need a
simple model to capture the behavior of the wire:
1. L-model, which produces a time constant of RwireCwire.
2. Π-model, which produces a time constant of RwireCwire /2.
3. T-model, which produces a time constant of RwireCwire /2.
• Both the Π-model and T-model produce an accurate model for
long distributed-RC lines, the Π-model is the most popular.

(a) L-model; (b) Π-model; (c) T-model.

Wire Design Principles
• Electrical wire/Interconnect models
• Transmission Line models
• Parasitic effects of Interconnect
• Capacitive-coupling effects
• Crosstalk
• RLC Effects
• Self-Timed Regenerators
Parasitic Effects of Interconnect
• Wires introduce three types of parasitic effects:
– resistive, capacitive, and inductive.
• All of these influence the signal integrity and degrade the
performance of the circuits.
• The signal-integrity problem involves the quality of a
signal being transmitted from one place to another
through wires.
RC Delay
• Resistive parasitics may cause an IR drop such that
noise margins are reduced and the performance of logic
circuits is deteriorated.
• The combination of resistive and capacitive parasitics
induces RC delays of signals and clocks, which may
impact on the performance of logic circuits.
• The reduction of RC delays is an important issue for
designing high-performance logic circuits.
• Three methods are proposed:
1. better interconnect materials
2. better interconnect strategies
3. buffer insertion
1. Better Interconnect Materials

• Better interconnect materials can effectively reduce the

parasitic resistance and capacitance of wires, thereby,
decreasing the RC delay significantly.
• Silicides and copper wires are the approaches to reduce
the resistance of polysilicon and metal wires, respectively
• Use of low-permittivity (i.e., low-k) dielectrics lowers the
parasitic capacitance between two wires.
• To reduce the resistance of a long polysilicon wire, (used
as the word-line of SRAM):
– use a metal bypass wire to tap the polysilicon wordline at
many places such that both metal and polysilicon wires are
effectively connected in parallel, it can reduce the
resistance of the word-line.
2. Better Interconnect Strategies

• The use of a better routing strategy makes possible the

reduction of the RC delay of wires.
• At present, most CAD tools only allow the wires to be
routed horizontally and vertically.
• If the diagonal wiring strategy is allowed, the resulting
chip would have above 20% interconnect length
reduction and above 15% chip area saving and 30% via
reduction.
• This would complicate the parameter models and make
the parameter extraction of layout much more difficult
than the Manhattan style.
3. Buffer Insertion

• The delay of a wire is a quadratic function of its length.

• To reduce the propagation delay of a long wire, break up
the quadratic relationship associated with the length.
• Sub-divide the long wire into many segments:
– insert a buffer between two segments so that the
propagation delay of the resulting long wire becomes
a linear function of the number of segments.
• The design approach based on this is buffer insertion.
• The design issues of buffer insertion are to find the
optimal number of equal-sized buffers and to determine
the optimize size of each buffer.
• The long wire is partitioned into the n segment and the
buffer between two segments has the size of M times
basic inverter.
• The reduction of the RC delay of a wire by inserting
buffers: (a) basic block; (b) equivalent circuit.
• Input capacitance of a basic inverter is

• Output capacitance of a basic inverter is equal to its self-loading

capacitance is given by
• The optimal number of segments n is

• The multiplier M of the optimal buffer size is equal to

• Equivalent circuit
Example of Buffer Insertion
• Assume that a 10-mm metal4 wire driven by a 50X
inverter. If Rint = 0.05ꭥ, Reqn = 8 kꭥ, Cint = 0.15 fF,
Cpara = 3.68 fF, Cg = 3.41 fF, and width of the metal4
wire is 0.5 µm in 0.18-µm process parameters:
1. Estimate the delay of this metal wire.
2. If the buffer insertion approach is used to reduce the
wire delay, calculate the optimal number of buffers
needed, the optimal buffer size, and total delay.
Example of Buffer Insertion: Solution
– Elmore delay of metal wire = 615 ps
– n=4
– M = 115
– Total Elmore delay of entire wire = 428.25 ps.
Wire Design Principles
• Electrical wire/Interconnect models
• Transmission Line models
• Parasitic effects of Interconnect
• Capacitive-coupling effects
• Crosstalk
• RLC Effects
• Self-Timed Regenerators
Capacitive-Coupling Effects
• The capacitive-coupling effects may cause undesired
crosstalk between different wires.
• Figure (a) shows an equivalent circuit taking into account
both resistive and capacitive parasitics.
• The C-only model shown in Figure (b).
• The wire of interest is called the victim while the
neighboring wire is called the aggressor.
• The effective loading capacitance of the victim due to the
coupling capacitance to known and then cope with the
crosstalk.
Effective Loading Capacitance

• The effective loading capacitance of the victim depends on the

switching state of the aggressor.
• When the aggressor is not switching, the effective loading
capacitance of the victim is equal to
Crosstalk
• Crosstalk, also known as capacitive noise is the problem
of noise injection due to capacitive coupling arising from
the situation where there is a non-switching node (the
victim) surrounded by switching aggressor nets.
• To quantify the amount of crosstalk, consider the
equivalent circuit revealed in Figure next.
• The amount of voltage change at node 1 is obtained by
using the voltage-divider rule and can be expressed as
follows.
The crosstalk effects caused by capacitive coupling
Example of Crosstalk
• Suppose that the length l of two metal2 wires between
two inverters is 2 mm and both victim and aggressor are
10X inverters. Find the amount of crosstalk ∆V1 using
0.18-µm process parameters. Assume Carea = 0.06 fF/µm
and Clateral = 0.08 fF/µm.
Solution
Capacitive-Coupling Reduction

• Two basic principles for reducing the capacitive-coupling

effects are spacing and shielding.
• Spacing the separation between wires, reduces the lateral
capacitance between two adjacent wires significantly;
• Interleaving switching signals with non-switching signals, such
as powers and grounds, reduces coupling capacitance.
• Capacitive-coupling effects can also be reduced by:
– using low-k dielectric material to reduce the coupling
capacitance between adjacent layers.
– layout strategy in which wires on adjacent layers are routed
orthogonally to minimize the crosstalk and signal wires on
the same layer are separated by VDD and Gnd shields.
• Another approach is based on the concept of cancellation,
using an inverting replica to cancel the original one.
• Based on this, there are three common approaches:
– Figure (a) depicts the situation when buffers (repeaters) are
used in long wires. We can stagger the place of buffers
properly so that injected noises can cancel out each other.
– Figure (b) illustrates the method of charge compensation in
which an explicitly coupling capacitor injects phase-inverse
noise to attack the unavoidable noise.
– Use of twisted, differential wires, as depicted in Figure (c).
• Both differential buffers and twisted wires are used in this
case.
THANK YOU

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