FPGA Exercise

This exercise is to be undertaken individually. The task is detailed below. You should do the design in
Verilog and produce a suitable test-bench to demonstrate your design. You will need to produce a
set of simulations to demonstrate the functionality of your design. If you have access to labs you
may demonstrate the design working on the FPGA. You may use the RCServo code that is on the site
as part of your code. Make sure that any code you make use of you properly attribute its use. It is
okay to have separate simulations for the state machine and the PWM generator for the barrier
control. You just need to make sure you have a suitable set of input signals to show that each part
works. If you do not get it fully working make sure you submit a report covering the work that you
have done.

Railway line

Detector D

Train lights Traffic lights and Barrier

Main road
Traffic lights and barrier Train lights

Detector D

Figure 1 Layout of road and railway track

Task
In this task you will implement a FPGA solution for an automated barrier for a road/railway level
crossing. The FPGA will form traffic light controller that operates main road traffic lights, the railway
traffic lights and the road barriers. You will be using a finite state machine to implement this
controller. This exercise provides you with a task that will help you gain experience that will be
useful for controlling real world applications. This involves planning your design, coding, and
debugging your design.

There are two major phases. The first is the design phase, which consists of reading through the
exercise, planning, and coming up with a design. The next phase is to implement the task using the
FPGA design and simulation software. If you have access to the FPGA board itself you may
demonstrate the task using the hardware.

You will be required to write a short report on the task.

Figure 1 illustrates the layout of the road and the railway. A busy road is intersected by a little used
railway track, detectors D sense the presence of trains on the track. With no train on the track the
lights remain green on the road direction and the crossing barrier is up (the crossing barrier is shown
as a red line in the figure). If there is a train on the track the road lights go from green to amber to
red (the delay at amber should be 0.Y seconds), when the road lights go to red the barrier is
lowered, allowing the train track lights to change to green. These stay green only as long as a train is
detected but never shorter than a set interval (say, X seconds). When these conditions are met, track
lights transition from green to amber to red, allowing road barrier to be raised and the lights return
to green.

Inputs
• Reset place FSM in initial state
• D (railway track train detector)
• Time delay for train to pass X seconds (X will be second last digit of your Heriot-Watt
registration number, unless it is 0 in which case X=1)
• The time delay on amber 1/Y seconds (Y will be the last digit of your Heriot-Watt registration
number, unless it is 0 in which case Y=1)

Outputs
• RG (road green)
• RA (road amber)
• RR (road red)
• TG (track green)
• TA (track amber)
• TR (track red)
• CG (crossing gates PWM signal)

Required Verilog components

• State machine that produces the required states for you traffic controller.
• Two timers one for the amber state and one for the time for the train to pass that will form
inputs to the controller state machine.
• A Verilog module that will be used to control the barrier so when the road traffic light is red
the barrier comes down. The pulse length required for the barrier to be up is 1ms, the pulse
length for the barrier to be down is 2ms. The pulse repetition frequency (PRF) should lie in
the range 50-80Hz

Guidelines for Report

This document specifies our technical expectations for the write-up of this exercise. It will eventually
count for 10% of your final grade. Please submit your report through Turnitin submission for your
campus. Note Turnitin checks that you have not copied someone else’s work

Cover Page and Abstract Your report should contain a cover page with a title, your name and
registration number, and also contain a paragraph abstract.

Introduction should present a summary of your traffic light controller's functionality and how you
went about implementing this project. We would like for you to describe what the different system
inputs and outputs are.

Module Description/Implementation, describe the various modules in your design. You should
explain what each piece of the system does and explain how these various pieces work together.
This section should make up the majority of your report. We expect a thorough explanation of the
various aspects of your design. When explaining your FSM, make sure to present a detailed
discussion of this module complete with a description of its inputs and outputs. You description
should mention the various FSM states in your design and what happens in each of these state. A
state transition diagram of your FSM is required.

Results and Debugging In this section we would like you to talk about your experiences testing and
debugging. We would like for you to discuss how you tested your digital system and mention ways in
which this could have been done better. Provide us with a description of the design methodology
you used in the creation of your traffic light controller by discussing the simulation (e.g., test bench),
and the FPGA implementation. Additionally, we ask that you submit screen captures from the
simulations of your system.

Conclusion There should be a short conclusions paragraph highlighting the achievements that the
report covers. You should mention where you might have done something differently if asked to
implement this project again.

Appendix For the technical submission of your lab report we ask that you include printouts of your
Verilog code in the Appendix.