ADC using SAR via DAC with PWM

JANUARY 22, 2021

Abstract
Pulse width modulation is that technique by which a low-frequency signal is being generated from
high-frequency pulses. The main use of pulse width modulation is to let the higher load electrical
devices to take over the control of the power supplied to the system. In a simpler sense, pulse width
modulation uses digital signals to control high power applications. Besides, it is easy to convert
the PWM signals back to the analog form with the minimum use of hardware. The power is
controlled by turning a switch on and off between the supply and load at an increased rate. The
power supplied to the load is directly proportional to the duration of the on time. Pulse width
modulation is also called pulse duration modulation. In this project we will ADC using SAR via
DAC with PWM using VHDL in ALTERA Quartus II and the results will be shown on the LCD
of the FPGA board, we will also verify our results through the Vector waveform results and RTL
diagram.

Keywords: PWM, VHDL, Altera Quartus II

 Table of Contents
Introduction ................................................................................................................................................... 3
Problem Description ..................................................................................................................................... 3
VHDL Code (PWM Generation) .................................................................................................................. 4
Analysis & Synthesis (PWM Generation) .................................................................................................... 4
RTL Diagram (PWM Generation) ................................................................................................................ 6
Technology Map viewer (PWM Generation) ............................................................................................... 7
Vector Waveform Results(PWM Generation) .............................................................................................. 7
Conversion via SAR and display it on LCD ................................................................................................. 7
VHDL Code .................................................................................................................................................. 8
Analysis & Synthesis .................................................................................................................................. 27
RTL Diagram .............................................................................................................................................. 27
Technology Map Viewer ............................................................................................................................ 28
Vector Waveform Results ........................................................................................................................... 28
Vector Waveform Compilation................................................................................................................... 29
Introduction
Pulse width modulation (PWM) is a digital technique used for controlling a circuit. A PWM
controller can be implemented either using a microcontroller or an FPGA digital outputs. The
PWM is employed in a wide multiplicity of applications, ranging from measurement and
communications to power control, conversion.
Pulse width modulation (PWM), is a method of reducing the average power delivered by an
electrical signal, by effectively chopping it up into discrete parts. The average value of voltage
(and current) fed to the load is controlled by turning the switch between supply and load on and
off at a fast rate. The longer the switch is on compared to the off periods, the higher the total power
supplied to the load.
PWM also works well with digital controls, which, because of their on/off nature, can easily set
the needed duty cycle. PWM has also been used in certain communication systems where its duty
cycle has been used to convey information over a communications channel.

Figure 1 Pulse-width modulation: a) typical PWM waveforms, b) comparison of pure and "modified" sine

The main parameter to define a PWM waveform are

▪ Modulating Period: the time between two consecutives ON period

▪ Duty Cycle: the ratio of the on-time to the period.
▪ Modulating Frequency: is the inverse of the period.

Problem Description
Our task is to implement ADC using SAR via DAC with PWM and present the results of the
simulations through Vector Waveform Results as well demonstration on FPGA Board. As a
software solution we used Altera Quartus II which is approved and tested for all FPGA systems.
Source code was written in VHDL and the simulations were made and presented in Vector Wave
Form file.
VHDL Code (PWM Generation)
library ieee; if (en = '1') then
use ieee.std_logic_1164.all; if (cnt = 0) then
use ieee.numeric_std.all; cnt <= to_unsigned(PERIOD-1,
use work.pwm_reg_pack.ALL; cnt'length);
entity pwm is clk_en <= '1';
port ( else
clk : in std_logic; cnt <= cnt - 1;
rst : in std_logic; end if;
en : in std_logic; end if;
duty : in end if;
std_logic_vector(DUTY_CYCLE_W-1 downto end process cnt_pr;
0); cnt_duty_pr : process(clk, rst)
pwm_out : out std_logic begin
); if (rst = '1') then
end entity pwm; cnt_duty <= (others => '0');
architecture rtl of pwm is pwm_out <= '0';
signal clk_en : std_logic; elsif (rising_edge(clk)) then
signal cnt : unsigned(PERIOD_W-1 if (clk_en = '1') then
downto 0); cnt_duty <= cnt_duty + 1;
signal cnt_duty : unsigned(DUTY_CYCLE_W- end if;
1 downto 0); if (cnt_duty < unsigned(duty)) then
begin pwm_out <= '1';
cnt_pr : process(clk, rst) else
begin pwm_out <= '0';
if (rst = '1') then end if;
cnt <= (others => '0'); end if;
clk_en <= '0'; end process cnt_duty_pr;
elsif (rising_edge(clk)) then end rtl;
clk_en <= '0';
Analysis & Synthesis (PWM Generation)
To check the results on Vector Waveform we need to first perform analysis and synthesis, to
check that there is no error in the program and we can then verify our design through Vector
Waveform (VWF) results and RTL Diagram.

RTL Diagram (PWM Generation)

Technology Map viewer (PWM Generation)

Vector Waveform Results(PWM Generation)

In Vector Waveform we need to set the input values, to verify that our desired program is
working correctly
Conversion via SAR and display it on LCD

VHDL Code
library IEEE; ); COMPONENT transmitter
use IEEE.STD_LOGIC_1164.ALL; END COMPONENT; PORT(
entity TOPCZECH is clk : IN
Port ( an : out COMPONENT CRC std_logic;
STD_LOGIC_VECTOR (3 downto PORT( enable : IN
0); clk : IN std_logic;
MHZ50 : in STD_LOGIC; std_logic;
R : in STD_LOGIC; data_en : IN sendRequest_T1 : IN
a_to_g : out std_logic; std_logic;
STD_LOGIC_VECTOR (6 downto dataIn : IN data_in_T1 : IN
0); std_logic_vector(71 downto 0); std_logic_vector(13 downto 0);
SW dataOut : OUT
: IN STD_LOGIC_VECTOR (3 std_logic_vector(15 downto 0); sendRequest_H1 : IN
downto 0); dataValid : OUT std_logic;
-- en : in STD_LOGIC; std_logic data_in_H1 : IN
LED ); std_logic_vector(12 downto 0);
: out STD_LOGIC_VECTOR (7 END COMPONENT;
downto 0); sendRequest_T2 : IN
TX std_logic;
: OUT STD_LOGIC; COMPONENT data_in_T2 : IN
DQ : inout STD_LOGIC Binary_To_BCD_16b std_logic_vector(13 downto 0);
); PORT(
end TOPCZECH; ENTERO : IN sendRequest_H2 : IN
std_logic_vector(15 downto 0); std_logic;
architecture Behavioral of POINT : IN data_in_H2 : IN
TOPCZECH is std_logic_vector(3 downto 0); std_logic_vector(12 downto 0);
BCD : OUT enable_LED :
std_logic_vector(18 downto 0); OUT std_logic;
COMPONENT DS18B20 BCDPOINT : serialDataOut :
PORT( OUT std_logic_vector(7 downto 0) OUT std_logic
clk1m : IN ); );
std_logic; END COMPONENT; END COMPONENT;
ds_data_bus :
INOUT std_logic; COMPONENT X7seg SIGNAL CLK1MHZ : STD_LOGIC;
crc_en : OUT PORT( SIGNAL DOK : STD_LOGIC;
std_logic; x : IN signal REQUEST : STD_LOGIC;
dataOut : OUT std_logic_vector(15 downto 0); SIGNAL DATA :
std_logic_vector(71 downto 0) clk : IN STD_LOGIC_VECTOR(71 downto
); std_logic; 0);
END COMPONENT; clr : IN SIGNAL DATA16 :
std_logic; STD_LOGIC_VECTOR(15 downto
COMPONENT an : OUT 0);
divider1MHz std_logic_vector(3 downto 0); SIGNAL DATA12 :
PORT( a_to_g : OUT STD_LOGIC_VECTOR(15 downto
clk_in : IN std_logic_vector(6 downto 0) 0);
std_logic; ); SIGNAL DATA4 :
clk_out : OUT END COMPONENT; STD_LOGIC_VECTOR(3 downto 0);
std_logic SIGNAL Y :
STD_LOGIC_VECTOR(18 downto enable_LED =>
0); U3: CRC PORT MAP( LED(6),
SIGNAL X : clk =>
STD_LOGIC_VECTOR(15 downto CLK1MHZ, sendRequest_T1
0); data_en => =>SW(0),
SIGNAL W : DOK, data_in_T1 =>
STD_LOGIC_VECTOR(7 downto 0); dataIn => DATA16(13 DOWNTO 0),
DATA,
dataOut => sendRequest_H1 =>
DATA16, SW(1),
dataValid data_in_H1 =>
=>REQUEST DATA16(12 DOWNTO 0),
begin );
sendRequest_T2 =>
DATA12 <= "0000" & DATA16(15 U4: Binary_To_BCD_16b SW(2),
DOWNTO 4 ); PORT MAP( data_in_T2 =>
DATA4 <= DATA16(3 DOWNTO 0 ENTERO => DATA16(13 DOWNTO 0),
); DATA12,
POINT => sendRequest_H2 =>
DATA4, SW(3),
U1: DS18B20 PORT BCD => Y, data_in_H2 =>
MAP( BCDPOINT => DATA16(12 DOWNTO 0),
clk1m => W serialDataOut
CLK1MHZ, ); => TX
crc_en => DOK, );
dataOut => U5: X7seg PORT MAP(
DATA, x => X,
ds_data_bus => clk => MHZ50,
DQ clr => R, X( 3 downto 0 ) <= W( 3 downto
); an => an, 0 );
a_to_g =>a_to_g X( 7 downto 4 ) <= W( 7 downto
U2: divider1MHz PORT ); 4 );
MAP( X( 11 downto 8) <= Y(3 downto 0
clk_in => U6: transmitter PORT );
MHZ50, MAP( X( 15 downto 12) <= Y(7 downto
clk_out => clk => MHZ50, 4 );
CLK1MHZ enable =>
); SW(0), end Behavioral;

library IEEE; dataOut : OUT TYPE STATE_TYPE is

use IEEE.STD_LOGIC_1164.ALL; (WAIT_800ms, RESET,
use IEEE.NUMERIC_STD.ALL; STD_LOGIC_VECTOR(71 PRESENCE, SEND, WRITE_BYTE,
downto 0); WRITE_LOW, WRITE_HIGH,
entity DS18B20 is ds_data_bus : GET_DATA, READ_BIT);
port INOUT STD_LOGIC -- momentalni stav FSM
( ); SIGNAL state: STATE_TYPE;
clk1m end DS18B20;
: IN -- nactena data z pameti
STD_LOGIC; architecture Behavioral of scratchpad senzoru
crc_en DS18B20 is SIGNAL data :
: OUT STD_LOGIC_VECTOR(71 downto
STD_LOGIC; -- potrebne stavy FSM 0);
 then
-- synchroni reset citace VARIABLE bit_cnt :
SIGNAL S_reset : STD_LOGIC; INTEGER RANGE 0 TO 71; --
-- citac prave cteny bit presence_signal <=
SIGNAL i : VARIABLE flag ds_data_bus;
INTEGER RANGE 0 TO 799999; : INTEGER RANGE 0 TO
5; -- priznak pro --
-- odesilana instrukce pro senzor odesilany prikaz odebrani vzorku pro zjisteni
SIGNAL write_command : pritomnosti senzoru
STD_LOGIC_VECTOR(7 downto 0); begin
if elsif (i = 1000)
-- vzorek signalu pro detekci rising_edge(clk1m) then then
senzoru na sbernici case
SIGNAL presence_signal state is state
: STD_LOGIC; <= PRESENCE;
when RESET =>
SIGNAL WRITE_BYTE_CNT :
INTEGER RANGE 0 TO 8 := 0;
-- citac pro odesilany -- prechod do stavu
bajt PRESENCE
SIGNAL write_low_flag : -- stav
INTEGER RANGE 0 TO 2 := 0; pro reset senzoru end if;
-- priznak pozice ve
stavu WRITE_LOW S_reset <= '0';
SIGNAL write_high_flag : when PRESENCE =>
INTEGER RANGE 0 TO 2 := 0;
-- priznak pozice
ve stavu WRITE_HIGH
SIGNAL read_bit_flag -- reset citace
: INTEGER RANGE 0 TO -- stav
3 := 0; -- priznak if (i = 0) then pro zjisteni pritomnosti senzoru
pozice ve stavu READ_BIT na sbernici
SIGNAL GET_DATA_CNT
: INTEGER RANGE 0 TO ds_data_bus <= '0'; -- detekce
72 := 0; -- citac pro senzoru na sbernici
pocet prectenych bitu
if
begin -- (presence_signal = '0' and
zacatek resetovaciho ds_data_bus = '1') then
-- Proces pro pulzu -- senzor byl detkovan
komunikaci se senzorem
DS18B20 elsif (i = 485)
process(clk1m) then S_reset <= '1';

-- vystupni data pri

chybe detekce senzoru na sbernici ds_data_bus <= 'Z';
CONSTANT --
PRESENCE_ERROR_DATA : reset citace
STD_LOGIC_VECTOR(71 downto
0):= -- uvolneni state
"1010101010101010101010101 sbernice <= SEND;
01010101010101010101010101
010101010101010101010"; elsif (i = 550)
 WRITE_BYTE;
-- -- stav
inicializace dokoncena, prechod pro odesilani prikazu pro senzor
do stavu SEND -- prechod do stavu
-- sekvence WRITE BYTE
else odesilanych prikazu rizena
priznakem flag elsif (flag = 2)
then
if (flag = 0)
then
--
-- senzor nebyl treti prikaz
detekovan
-- prvni prikaz flag :=
3;
S_reset <= '1'; flag :=
1; state
<= WAIT_800ms;

-- write_command
reset citace <="11001100"; --
prechod do stavu WAIT_800ms,
cekani na ukonceni prikazu 44h
dataOut <= -- prikaz CCh - SKIP ROM
PRESENCE_ERROR_DATA; elsif (flag = 3)
state then
<=
-- nastaveni dat WRITE_BYTE;
indikujicich chybu na vystup --
treti prikaz
-- prechod do stavu
crc_en <= '1'; WRITE BYTE flag :=
4;
elsif (flag = 1)
then
-- write_command
zahajeni vypoctu CRC <="11001100";
--
state druhy prikaz
<= -- prikaz CCh - SKIP ROM
WAIT_800ms; flag :=
2; state
<=
-- WRITE_BYTE;
prechod do stavu WAIT_800ms write_command
<="01000100";
end if; -- prechod do stavu
WRITE BYTE
-- prikaz 44h - CONVERT
when SEND => TEMPERATURE elsif (flag = 4)
then
state
<=
 -- pro precteni pameti scratchpad
ctvrty prikaz -- stav cekani
po dobu 800 ms case
flag := GET_DATA_CNT is
5; CRC_en <= '0';

write_command -- pozice ve
<="10111110"; stavu GET_DATA
--
reset priznaku pro zahajeni when
-- prikaz BEh - READ vypoctu CRC 0 to 71=>
SCRATCHPAD
S_reset <= '0';
state
<= --
WRITE_BYTE; cteni jednotlivych bitu pameti
scratchpad
-- spusteni
-- prechod do stavu citace
WRITE BYTE ds_data_bus <= '0';
if (i = 799999)
elsif (flag = 5) then
then
-- zahajeni
cteni na sbernici
-- -- konec periody citace
ukonceni vysilani prikazu
GET_DATA_CNT <=
flag := S_reset <='1'; GET_DATA_CNT + 1;
0;
--
inkrementace citace pro prave
cteny bit
-- -- resetovani citace
reset priznaku pro odesilany
prikaz state state <=
<= RESET; READ_BIT;
state
<= GET_DATA;
-- prechod do stavu
-- READ_BIT
navrat do stavu RESET
-- prechod do stavu when
GET_DATA end if; 72=>

end if;
when GET_DATA =>
--
when WAIT_800ms => pamet prectena (72 bitu)

-- stav bit_cnt := 0;
 GET_DATA_CNT <= 0;

-- uvolneni sbernice pro

-- prijem bitu ze senzoru
reset citace pro prave cteny bit -- reset citace
pro pocet prectenych bitu
S_reset <= '0';
GET_DATA_CNT <=0; end case;

when READ_BIT => -- zapnuti

-- citace
reset citace prectenych bitu

if (i = 13) then
dataOut <= data(71 -- stav
downto 0); pro cteni bitu

-- odeslani -- sekvence -- cekani 14 us

prectenych dat na vystupni port cteni bitu rizena priznakem
read_bit_flag
S_reset
CRC_en <= case <= '1';
'1'; read_bit_flag is

-- reset citace
-- spusteni
vypoctu CRC prectenych dat -- pozice ve stavu
READ_BIT read_bit_flag
<= 2;
state <= when
WAIT_800ms; 0=>
end if;
--
navrat do stavu WAIT_800ms when
2=>
when -- vyslani zacatku
others => casoveho slotu pro cteni

read_bit_flag <= 1; -- odebrani vzorku dat

-- ze sbernice
chyba ve stavu GET_DATA when
1=>
data(bit_cnt) <=
read_bit_flag <= 0; ds_data_bus;

-- ulozeni
vzorku dat do registru
-- reset pozice ve stavu
READ_BIT
ds_data_bus <= 'Z'; bit_cnt := bit_cnt + 1;
 -- navrat do stavu
GET_DATA -- stav pro
-- zvyseni citace pro zapis bajtu dat na sbernici
prave cteny bit
end if; -- sekvence
zapisu bajtu dat rizena citacem
read_bit_flag <= 3; when WRITE_BYTE_CNT
others =>
when case
3=> WRITE_BYTE_CNT is

-- chyba ve
stavu READ_BIT
-- pozice ve
-- dokonceni casoveho stavu WRITE_BYTE
slotu read_bit_flag <= 0;
when
0 to 7=>
S_reset <= '0';
-- reset pozice ve stavu
READ_BIT
-- odesilani
-- zapnuti bitu 0-7
citace bit_cnt := 0;

if
if (i = 63) then (write_command(WRITE_BYTE_C
-- reset citace NT) = '0') then --
pro prave cteny bit odesilany bit ma hodnotu log. 0

-- cekani 62 us
GET_DATA_CNT <= 0; state <=
WRITE_LOW;
S_reset<='1';

-- reset citace -- prechod do

prectenych bitu stavu WRITE_LOW
--
reset citace
state else
<= RESET;
read_bit_flag
<= 0;
--
reset senzoru -- odesilany bit
-- reset pozice ve stavu ma hodnotu log. 1
READ_BIT end case;

state <=
state when WRITE_BYTE => WRITE_HIGH;
<= GET_DATA;

-- prechod do
stavu WRITE_HIGH -- vyslani zacatku
write_low_flag <= 0; casoveho slotu pro zapis log. 0

end if;
ds_data_bus <= '0';
-- reset pozice ve stavu
WRITE_BYTE_CNT <= WRITE_LOW
WRITE_BYTE_CNT + 1;
-- zacatek casoveho slotu
-- inkrementace citace write_high_flag <= 0;
odesilaneho bitu
S_reset <= '0';
when
8=> -- reset pozice ve stavu
WRITE_HIGH
-- zapnuti
citace
state <=
-- odesilani bajtu RESET;
dokonceno if (i = 59) then
--
reset senzoru
WRITE_BYTE_CNT <= 0;
end -- cekani 60 us
case;

-- reset citace S_reset

odesilaneho bitu when WRITE_LOW => <='1';

state -- reset citace

<= SEND;
-- stav
pro zapis log. 0 na sbernici write_low_flag
<= 1;
-- navrat do stavu SEND -- casovy slot
pro zapis log 0 rizeny priznakem
when write_low_flag end if;
others=>
case when
write_low_flag is 1=>

-- chyba ve
stavu WRITE_BYTE
-- pozice ve stavu
WRITE_LOW -- uvolneni sbernice pro
WRITE_BYTE_CNT <= 0; ukonceni casoveho slotu
when
0=>
ds_data_bus <= 'Z';
-- reset citace
odesilaneho bitu
 -- uvolneni sbernice navrat do stavu WRITE_BYTE -- pozice ve stavu
WRITE_HIGH
when
S_reset <= '0'; others=> when
0=>

-- zapnuti -- chyba zapisu

citace log. 0
-- vyslani zacatku
casoveho slotu pro zapis log. 1
if (i = 3) then WRITE_BYTE_CNT <= 0;

ds_data_bus <= '0';

-- cekani 4 us -- reset citace

na ustaleni sbernice odesilaneho bitu
-- zacatek casoveho slotu

S_reset write_low_flag <= 0;

<= '1'; S_reset <= '0';

-- reset citace -- reset pozice ve stavu

WRITE_LOW -- zapnuti
citace
write_low_flag
<= 2; state <=
RESET; if (i = 9) then

end if; --
reset senzoru
when -- cekani 10 us
2=> end case;

S_reset
when WRITE_HIGH => <= '1';

-- konec zapisu log. 0

-- reset citace

write_low_flag <= 0; -- stav pro

zapis log. 1 na sbernici write_high_flag
<= 1;
-- casovy slot
-- reset pozice pro zapis log 1 rizeny priznakem
ve stavu WRITE_LOW write_high_flag end if;

case when
state <= write_high_flag is 1=>
WRITE_BYTE;

--
 -- reset pozice ve stavu RESET;
-- uvolneni sbernice pro WRITE_HIGH
ukonceni casoveho slotu

state -- reset
ds_data_bus <= 'Z'; <= WRITE_BYTE; senzoru

--
navrat do stavu WRITE BYTE end
-- uvolneni sbernice case;
when end if;
others => end process;
S_reset <= '0';
-- Proces citace se
synchronnim resetem
-- process(clk1m, S_reset)
-- zapnuti chyba zapisu log. 1
citace begin
if
WRITE_BYTE_CNT <= 0; (rising_edge(clk1m)) then
if (i = 53) then if
(S_reset = '1')then --
reset citace
-- reset citace
-- cekani 54 us odesilaneho bitu i <= 0;

-- vynulovani citace
S_reset write_high_flag <= 0; else
<= '1';
i <= i + 1;
--
-- reset citace -- reset pozice ve stavu inkrementace citace
WRITE_HIGH end if;
end if;
write_high_flag end process;
<= 2; state <=
RESET; end Behavioral;

end if; -- library IEEE;

reset senzoru use IEEE.STD_LOGIC_1164.ALL;
when use
2=> end case; IEEE.STD_LOGIC_unsigned.ALL;

when others => entity Binary_BCD is

Port ( b : in
-- konec zapisu log. 1 STD_LOGIC_VECTOR (7
downto 0);
p : out STD_LOGIC_VECTOR
write_high_flag <= 0; -- (9 downto 0));
chyba FSM end Binary_BCD;

state <= architecture Behavioral of

Binary_BCD is 0);
BCDPOINT :
begin OUT STD_LOGIC_VECTOR(7 "0101"&"0000" when "1000",--
DOWNTO 0) 0.5
bcd1: );
process (b)
variable z: end Binary_To_BCD_16b; "0101"&"0110" when "1001",--
STD_LOGIC_VECTOR (17 downto 0.5625
0); architecture Behavioral of
Binary_To_BCD_16b is
begin "0110"&"0011" when "1010",--
signal temper: std_logic_vector(3 0.625 =0.63
for i in 0 to 17 loop downto 0);
z(i):= '0' ; signal point_out:
end loop; std_logic_vector(7 downto 0); "0110"&"1001" when "1011",--
z(10 downto 3) 0.6875 =0.69
:= b; begin
for i in 0 to 4 loop
if z(11 downto temper <= POINT; "0111"&"0101" when "1100",--
8) > 4 then BCDPOINT<= point_out; 0.75
z(11 downto 8)
:= z(11 downto 8) + 3; with temper select
end if; "1000"&"0001" when "1101",--
if z(15 downto point_out<= 0.8125
12) >4 then "0000"&"0000" when "0000",--0
z(15 downto
12) := z(15 downto 12) + 3; "1000"&"1000" when "1110",--
end if; "0000"&"0110" when "0001",-- 0.875 =0.88
z(17 downto 1) 0.0625
:= z(16 downto 0);
end loop; "1001"&"0100" when "1111",--
p <= z(17 downto 8); "0001"&"0010" when "0010",-- 0.9375 =0.94
end process bcd1; 0.125

end Behavioral; "0000"&"0000" when others;

"0001"&"1001" when "0011",--
library IEEE; 0.1875 =0.19
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL; BCD1: PROCESS(ENTERO)
USE "0010"&"0101" when "0100",-- VARIABLE
IEEE.STD_LOGIC_UNSIGNED.ALL; 0.25 Z:STD_LOGIC_VECTOR(34
DOWNTO 0);
BEGIN
entity Binary_To_BCD_16b is "0011"&"0101" when "0101",-- FOR I IN 0 TO 34 LOOP
PORT ( 0.31 Z(I):='0';
ENTERO : IN END LOOP;
STD_LOGIC_VECTOR(15 DOWNTO Z(18 DOWNTO 3):=ENTERO;
0); "0011"&"1000" when "0110",-- FOR I IN 0 TO 12 LOOP
POINT : IN 0.375 =0.38 IF Z(19 DOWNTO 16) > 4 THEN
STD_LOGIC_VECTOR(3 DOWNTO Z(19 DOWNTO 16):= Z(19
0); DOWNTO 16)+3;
BCD : OUT "0100"&"0100" when "0111",-- END IF;
STD_LOGIC_VECTOR(18 DOWNTO 0.4375 =0.44 IF Z(23 DOWNTO 20) > 4 THEN
 Z(23 DOWNTO 20):= Z(23 IF Z(31 DOWNTO 28) > 4 THEN END LOOP;
DOWNTO 20)+3; Z(31 DOWNTO 28):= Z(31 BCD<=Z(34 DOWNTO 16);
END IF; DOWNTO 28)+3; END PROCESS;
IF Z(27 DOWNTO 24) > 4 THEN END IF;
Z(27 DOWNTO 24):= Z(27
DOWNTO 24)+3; Z(34 DOWNTO 1):= Z(33 end Behavioral;
END IF; DOWNTO 0);

library IEEE; -- Proces pro vypocet a CONSTANT

use IEEE.STD_LOGIC_1164.ALL; kontrolu CRC obdrzenych dat PRESENCE_ERROR_DATA_C :
use IEEE.STD_LOGIC_ARITH.ALL; process(clk) STD_LOGIC_VECTOR(71 downto
use 0) :=
IEEE.STD_LOGIC_UNSIGNED.ALL; -- delka obdrzenych dat "1010101010101010101010101
v bitech 01010101010101010101010101
entity CRC is CONSTANT 010101010101010101010";
Port ( clk DATA_WIDTH_C : INTEGER :=
: IN STD_LOGIC; 72;
begin
data_en : IN -- prave zpracovavany
STD_LOGIC; bit if
VARIABLE i (rising_edge(clk)) then
dataIn : IN --
STD_LOGIC_VECTOR (71 : integer range 0 to FSM ridici cinnost modulu CRC
downto 0); DATA_WIDTH_C := 0; case
(crc_state) is
dataOut : OUT -- pomocny registr pro
STD_LOGIC_VECTOR (15 vypocet CRC when IDLE =>
downto 0); VARIABLE CRC_temp
:
dataValid : OUT STD_LOGIC_VECTOR(7 downto 0);
STD_LOGIC -- vychozi stav
); -- registr s vypoctenym
end CRC; CRC dataValid <=
VARIABLE CRC_val '0';
architecture Behavioral of CRC is :
STD_LOGIC_VECTOR(7 downto 0); --
-- obdrzena data ze senzoru + zruseni signalu indikujiciho
prijate CRC -- vystupni data dokonceni vypoctu CRC
SIGNAL data : indikujici chybu CRC
STD_LOGIC_VECTOR(71 downto CONSTANT if (data_en =
0); CRC_ERROR_C : '1') then
STD_LOGIC_VECTOR(15 downto
-- stavy FSM 0) := "0111111111111111"; -- pozadavek na vypocet
TYPE STATE_TYPE IS (IDLE, -- vystupni data CRC
CRC_CALC, CRC_CHECK); indikujici nepripojeni senzoru
-- momentalni stav FSM CONSTANT
SIGNAL crc_state: STATE_TYPE; PRESENCE_ERROR_C : crc_state <= CRC_CALC;
STD_LOGIC_VECTOR(15 downto
0) := "0011111111111111"; --
begin -- vstupni data indikujici prechod do stavu CRC_CALC
nepripojeni senzoru
 end if;
CRC_val(5) :=
CRC_val(6);
when CRC_CALC => --
prijate CRC neni shodne s
CRC_val(6) := vypocitanym
CRC_val(7);
-- stav pro vypocet CRC if
(dataIn /=
if (i < CRC_val(7) := PRESENCE_ERROR_DATA_C) then
DATA_WIDTH_C) then CRC_temp(7); -- vstupni data obsahuji
data ze senzoru
-- pokracovani
s vkladanim dat do posuvneho i:=i+1;
registru dataOut <=
CRC_ERROR_C;
-- -- -- data nebyla
Vypocet CRC pomoci LFSR inkrementace vstupniho bitu prijata spravne, vystup nastaven
vkladaneho do posuvneho na chybovou hodnotu
registru
CRC_temp(7):= dataIn(i) else
XOR CRC_val(0); else

dataOut <=
CRC_temp(2):= crc_state <= PRESENCE_ERROR_C;
CRC_val(3) XOR (dataIn(i) XOR CRC_CHECK; -- senzor neni
CRC_val(0)); pripojen, vystup nastaven na
-- prechod do stavu chybovou hodnotu
CRC_check
CRC_temp(3):= end if;
CRC_val(4) XOR (dataIn(i) XOR end if;
CRC_val(0)); end if;

when CRC_CHECK => CRC_temp

CRC_val(0) := := "00000000";
CRC_val(1);
-- reset
-- stav pro porovnani vypocitaneho CRC
CRC_val(1) := CRC
CRC_val(2); CRC_val :=
if (CRC_val = "00000000";
"00000000") then
CRC_val(2) := -- prijate CRC -- reset pomocneho
CRC_temp(2); shodne s vypocitanym registru

i
CRC_val(3) := dataOut <= dataIn(15 := 0;
CRC_temp(3); downto 0);
-- data prijata spravne,
vystup nastaven na data -- reset prave
CRC_val(4) := obsahujici namerenou teplotu zpracovavaneho bitu dat
CRC_val(5);
else dataValid <=
'1'; crc_state <= case;
IDLE; end if;
-- end process;
indikace dokonceni vypoctu CRC -- navrat do
stavu IDLE end Behavioral;
end

library IEEE; 4);

use IEEE.STD_LOGIC_1164.ALL; when "10" => digit <= x(11 when X"A" => a_to_g <=
use ieee.std_logic_unsigned.all; downto 8); "0001000"; --A
when others => digit <= x(15
downto 12); when X"B" => a_to_g <=
entity X7seg is end case; "1100000"; --B
Port ( x : in end process;
STD_LOGIC_VECTOR (15 downto hex7seg: process(digit) when X"C" => a_to_g <=
0); begin "0110001"; --C
clk : in STD_LOGIC; case
clr : in STD_LOGIC; digit is when X"D" => a_to_g <=
an : out "1000010"; --D
STD_LOGIC_VECTOR (3 downto when X"0" => a_to_g <=
0); "0000001"; --0 when X"E" => a_to_g <=
a_to_g : out "0110000"; --E
STD_LOGIC_VECTOR (6 downto when X"1" => a_to_g <=
0)); "1001111"; --1 when others => a_to_g
end X7seg; <= "0111000"; --F
when X"2" => a_to_g <= end
architecture Behavioral of X7seg "0010010"; --2 case;
is end process;
when X"3" => a_to_g <= -- Digit Select
"0000110"; --3 ancode: process(s, aen)
signal s: std_logic_vector(1 begin
downto 0); when X"4" => a_to_g <= an <= "1111";
signal digit: std_logic_vector(3 "1001100"; --4 if aen(conv_integer(s)) = '1' then
downto 0); an(conv_integer(s)) <= '0';
signal aen: std_logic_vector(3 when X"5" => a_to_g <= end if;
downto 0); "0100100"; --5 end process;
signal clkdiv: std_logic_vector(19 -- Clock Divider
downto 0); when X"6" => a_to_g <= clkdivider: process(clk,clr)
"0100000"; --6 begin
begin if clr = '1' then
s <= clkdiv(19 downto 18); when X"7" => a_to_g <= clkdiv <= (others => '0');
aen <= "1111"; "0001101"; --7 elsif rising_edge(clk) then
mux44: process (s,x) clkdiv <= clkdiv + 1;
begin when X"8" => a_to_g <= end if;
case s is "0000000"; --8
when "00" => digit <= x(3 downto end process;
0); when X"9" => a_to_g <=
when "01" => digit <= x(7 downto "0000100"; --9 end Behavioral;

library IEEE; clk_out : OUT

use IEEE.STD_LOGIC_1164.ALL; entity divider1MHz is STD_LOGIC
use Port ( clk_in : IN );
IEEE.STD_LOGIC_UNSIGNED.ALL; STD_LOGIC; end divider1MHz;
 if clk_out <= '1';
architecture Behavioral of (rising_edge(clk_in)) then
divider1MHz is count else
<= count + 1;
SIGNAL count: INTEGER RANGE 0 clk_out <= '0';
to 99; -- citac if
(count = 49) then end if;
begin end if;
end process;
-- Proces pro deleni count <= 0;
taktu 1/100 end Behavioral;
process (clk_in)
begin

library IEEE; : in STD_LOGIC; "0110" => return '6';

use IEEE.STD_LOGIC_1164.ALL; data_in_H2 when
use IEEE.NUMERIC_STD.ALL; : in "0111" => return '7';
STD_LOGIC_VECTOR (12 downto when
entity transmitControler is 0); "1000" => return '8';
Port ( clk parallelDataOut when
: out "1001" => return '9';
: in STD_LOGIC; STD_LOGIC_VECTOR (7 downto when
0); "1010" => return 'A';
enable transmitRequest when
: in : out STD_LOGIC; "1011" => return 'B';
STD_LOGIC; txIsReady when
: in "1100" => return 'C';
enable_LED STD_LOGIC); when
: out end transmitControler; "1101" => return 'D';
STD_LOGIC; when
sendRequest_T1 architecture Behavioral of "1110" => return 'E';
: in transmitControler is when
STD_LOGIC; "1111" => return 'F';
data_in_T1 -- Funkce pro prevod dat z when
: in binarniho formatu na znak others => return NUL;
STD_LOGIC_VECTOR (13 downto function convertToChar(s: end case;
0); STD_LOGIC_VECTOR(3 downto end convertToChar;
0)) return character is
sendRequest_T2 begin -- pouzite stavy FSM
: in STD_LOGIC; case (s) is TYPE controlerState IS (IDLE,
data_in_T2 when PREPARE_SEQUENCE,
: in "0000" => return '0'; PREPARE_CHAR, SEND_CHAR);
STD_LOGIC_VECTOR (13 downto when -- momentalni stav FSM
0); "0001" => return '1'; SIGNAL ctrl_state :
sendRequest_H1 when controlerState;
: in "0010" => return '2';
STD_LOGIC; when -- navzorkovana data ze senzoru
data_in_H1 "0011" => return '3'; T1: DS18B20
: in when --
STD_LOGIC_VECTOR (12 downto "0100" => return '4';
0); when
"0101" => return '5'; T2: ADT7420
sendRequest_H2 when --
 -- Proces pro rizeni (others => '0');
prenosu dat pres seriovou linku -- reset vsech dat
H1: DHT11 process(clk)
-- charToSend
-- citac prave := NUL;
odesilaneho znaku
H2: DHT22 VARIABLE stringToSend_T1 :=
SIGNAL dataToSend_T1 char_send_cnt : (others => NUL);
: INTEGER RANGE 0 TO 26;
STD_LOGIC_VECTOR(13 DOWNTO stringToSend_T2 :=
0); -- prave odesilany znak (others => NUL);
SIGNAL dataToSend_T2 VARIABLE charToSend
: : stringToSend_H1 :=
STD_LOGIC_VECTOR(13 DOWNTO CHARACTER; (others => NUL);
0);
SIGNAL dataToSend_H1 -- sekvence dat k stringToSend_H2 :=
: odeslani od jednotlivych senzoru (others => NUL);
STD_LOGIC_VECTOR(12 DOWNTO VARIABLE
0); stringToSend stringToSend :=
SIGNAL dataToSend_H2 : STRING(1 TO 26); stringToSend_T1 &
: -- stringy obsahujici data stringToSend_H1 &
STD_LOGIC_VECTOR(12 DOWNTO ze senzoru stringToSend_T2 &
0); VARIABLE stringToSend_H2 & CR & LF;
stringToSend_T1 : STRING(1 TO
-- priznaky prichodu dat ze 6); ctrl_state <=
senzoru T1: DS18B20 VARIABLE IDLE;
-- stringToSend_T2 : STRING(1 TO
6); --
VARIABLE navrat do zakladniho stavu
T2: ADT7420 stringToSend_H1 : STRING(1 TO else
-- 6);
VARIABLE case (ctrl_state) is
stringToSend_H2 : STRING(1 TO
H1: 6); when IDLE =>
DHT11
-- begin

-- zakladni stav modulu,

H2: if cekani na data ze vsech senzoru
DHT22 (rising_edge(clk)) then
SIGNAL dataReady_T1 if --
: STD_LOGIC; (enable = '0') then Cekani na data ze vsech senzoru
SIGNAL dataReady_T2
: STD_LOGIC; if
SIGNAL dataReady_H1 -- vypnuti odesilani (dataReady_T1 = '1' and
: STD_LOGIC; dataReady_T2 = '1' and
SIGNAL dataReady_H2 transmitRequest <= '0'; dataReady_H1 = '1' and
: STD_LOGIC; dataReady_H2 = '1') then

-- konstanty pouzite v -- zruseni

stringToSend zadosti o odesilani char_send_cnt := 0;

begin parallelDataOut <=

 -- reset citace stringToSend_T2 := '+' &
odeslanych znaku elsif convertToChar(dataToSend_T2(1
(dataToSend_T1(13 downto 12) = 1 downto 8)) &
"01") then -- data obsahuji convertToChar(dataToSend_T2(7
ctrl_state zapornou hodnotu namerene downto 4)) & '.' &
<= teploty convertToChar(dataToSend_T2(3
PREPARE_SEQUENCE; -- downto 0)) & ';';
prechod do stavu
PREPARE_SEQUENCE stringToSend_T1 := '-' & elsif
convertToChar(dataToSend_T1(1 (dataToSend_T2(13 downto 12) =
end if; 1 downto 8)) & "01") then -- data obsahuji
convertToChar(dataToSend_T1(7 zapornou hodnotu namerene
downto 4)) & '.' teploty
when &convertToChar(dataToSend_T1(
PREPARE_SEQUENCE => 3 downto 0)) & ';';
stringToSend_T2 := '-' &
-- stav pro else -- convertToChar(dataToSend_T2(1
pripravu sekvence dat pro chyba obdrzenych dat 1 downto 8)) &
odeslani convertToChar(dataToSend_T2(7
downto 4)) & '.'
-- stringToSend_T1 := &convertToChar(dataToSend_T2(
vytvoreni stringu obsahujici data "ER_T1" & ';'; 3 downto 0)) & ';';
ze senzoru teploty DS18B20
end if; else --
if chyba obdrzenych dat
(dataToSend_T1(13 downto 12) =
"11") then -- data obsahuji cislo
chyby -- stringToSend_T2 :=
vytvoreni stringu obsahujici data "ER_T2" & ';';
ze senzoru teploty ADT7420
stringToSend_T1 := "E " end if;
& if
convertToChar(dataToSend_T1(1 (dataToSend_T2(13 downto 12) =
1 downto 8)) & "11") then -- data obsahuji cislo
convertToChar(dataToSend_T1(7 chyby --
downto 4)) & vytvoreni stringu obsahujici data
convertToChar(dataToSend_T1(3 ze senzoru vlhkosti DHT11
downto 0)) & ';'; stringToSend_T2 := "E "
& if
elsif convertToChar(dataToSend_T2(1 (dataToSend_H1(12) = '1') then --
(dataToSend_T1(13 downto 12) = 1 downto 8)) & data obsahuji cislo chyby
"00") then -- data obsahuji convertToChar(dataToSend_T2(7
kladnou hodnotu namerene downto 4)) &
teploty convertToChar(dataToSend_T2(3 stringToSend_H1 := "E "
downto 0)) & ';'; &
convertToChar(dataToSend_H1(1
stringToSend_T1 := '+' & elsif 1 downto 8)) &
convertToChar(dataToSend_T1(1 (dataToSend_T2(13 downto 12) = convertToChar(dataToSend_H1(7
1 downto 8)) & "00") then -- data obsahuji downto 4)) &
convertToChar(dataToSend_T1(7 kladnou hodnotu namerene convertToChar(dataToSend_H1(3
downto 4)) & '.' & teploty downto 0)) & ';';
convertToChar(dataToSend_T1(3
downto 0)) & ';'; elsif
(dataToSend_H1(12) = '0') then -- -- konverze dat z char do
data obsahuji hodnotu namerene else -- std_logic_vector
vlhkosti chyba obdrzenych dat

parallelDataOut <=
stringToSend_H1 := stringToSend_H2 := std_logic_vector(to_unsigned(char
convertToChar(dataToSend_H1(7 "ER_H2" & ';'; acter'pos(charToSend), 8));
downto 4)) &
convertToChar(dataToSend_H1(3 end if;
downto 0)) & "% " & ';'; char_send_cnt :=
char_send_cnt + 1; --
else -- -- inkrementace odesilaneho bitu
chyba obdrzenych dat vytvoreni kompletniho
odesilaneho stringu
ctrl_state
stringToSend_H1 := <=
"ER_H1" & ';'; stringToSend := SEND_CHAR;
stringToSend_T1 & -- prechod do
end if; stringToSend_H1 & stavu SEND_CHAR
stringToSend_T2 &
stringToSend_H2 & CR & LF; -- else
zapis kompletni sekvence dat k
-- odeslani dat
vytvoreni stringu obsahujici data transmitRequest <= '0';
ze senzoru vlhkosti DHT22
ctrl_state <=
if PREPARE_CHAR; -- prechod do -- ukonceni odesilani dat
(dataToSend_H2(12) = '1') then -- stavu PREPARE_CHAR po odeslani 26 znaku
data obsahuji cislo chyby

when ctrl_state
stringToSend_H2 := "E " PREPARE_CHAR => <= IDLE;
&
convertToChar(dataToSend_H2(1 -- stav pro -- prechod do stavu IDLE
1 downto 8)) & pripravu seriovych dat
convertToChar(dataToSend_H2(7 end if;
downto 4)) &
convertToChar(dataToSend_H2(3 transmitRequest <= '0';
downto 0)) & ';'; when
-- zruseni pozadavku na SEND_CHAR =>
elsif odesilani znaku
(dataToSend_H2(12) = '0') then --
data obsahuji hodnotu namerene if -- stav
vlhkosti (char_send_cnt < 26) then pro odesilani bajtu dat
-- pocitani odeslanych
znaku if
stringToSend_H2 := (txIsReady = '1') then
convertToChar(dataToSend_H2(1
1 downto 8)) & charToSend := --
convertToChar(dataToSend_H2(7 stringToSend(char_send_cnt+1); - cekani na submodul UART
downto 4)) & '.' - vyber odesilaneho znaku
&convertToChar(dataToSend_H2(
3 downto 0)) & "%" & ';'; transmitRequest <= '1';
 (sendRequest_T1 = '1') then
-- prichod dat ze senzoru -- Proces pro cekani na
-- pozadavek na odeslani teploty DS18B20 data ze senzoru ADT7420
bajtu dat process(clk)
dataToSend_T1 <= begin
data_in_T1; -- if
ctrl_state odebrani vzorku dat ze senzoru (rising_edge(clk)) then
<= teploty DS18B20 if
PREPARE_CHAR; (sendRequest_T2 = '1') then
-- navrat k dalsimu dataReady_T1 <= '1'; -- prichod dat ze senzoru
odesilani ve stavu teploty ADT7420
PREPARE_CHAR -- nastaveni priznaku
prichodu dat dataToSend_T2 <=
end if; else data_in_T2; --
odebrani vzorku dat ze senzoru
end case; if ctrl_state = teploty ADT7420
end if; PREPARE_SEQUENCE then
end if; dataReady_T2 <= '1';
end process; dataReady_T1
<= '0'; -- nastaveni priznaku
-- Proces pro cekani na -- zruseni prichodu dat
data ze senzoru DS18B20 priznaku prichodu dat else
process(clk)
begin end if; if ctrl_state =
if end if; PREPARE_SEQUENCE then
(rising_edge(clk)) then end if;
if end process;
dataReady_T2 <= '0'; -- zruseni priznaku
prichodu dat -- nastaveni priznaku -- prichod dat
prichodu dat ze senzoru vlhkosti DHT22
end if; else
end if; dataToSend_H2 <=
end if; if ctrl_state = data_in_H2; --
end process; PREPARE_SEQUENCE then odebrani vzorku dat ze senzoru
vlhkosti DHT22
-- Proces pro cekani na dataReady_H1
data ze senzoru DHT11 <= '0'; dataReady_H2 <= '1';
process(clk) -- zruseni
begin priznaku prichodu dat -- nastaveni priznaku
if prichodu dat
(rising_edge(clk)) then end if; else
if end if;
(sendRequest_H1 = '1') then end if; if ctrl_state =
-- prichod dat end process; PREPARE_SEQUENCE then
ze senzoru vlhkosti DHT11
-- Proces pro dataReady_H2
dataToSend_H1 <= cekani na data ze senzoru DHT22 <= '0';
data_in_H1; -- process(clk) -- zruseni
odebrani vzorku dat ze senzoru begin priznaku prichodu dat
vlhkosti DHT11 if
(rising_edge(clk)) then end if;
dataReady_H1 <= '1'; if end if;
(sendRequest_H2 = '1') then end if;
 end process; STD_LOGIC;
enable enable
enable_LED <= '1' when : =>
enable = '1' else '0'; IN STD_LOGIC; enable,

end Behavioral; baudRateEnable

library IEEE; : IN STD_LOGIC; baudRateEnable
use IEEE.STD_LOGIC_1164.ALL; parallelDataIn =>
: IN baudRateEnable,
entity UART is STD_LOGIC_VECTOR(7
Port ( clk downto 0); parallelDataIn
: IN =>
STD_LOGIC; transmitRequest : parallelDataIn,
enable IN STD_LOGIC;
: IN STD_LOGIC; txIsReady
parallelDataIn : IN : transmitRequest =>
STD_LOGIC_VECTOR (7 OUT STD_LOGIC; transmitRequest,
downto 0); serialDataOut
transmitRequest : IN : OUT txIsReady
STD_LOGIC; STD_LOGIC =>
); txIsReady,
txIsReady end component
: OUT STD_LOGIC; UART_transmitter; serialDataOut
serialDataOut : OUT =>
STD_LOGIC signal baudRateEnable serialDataOut
); : STD_LOGIC; );
end UART; end Structure;
library IEEE;
architecture Structure of UART is begin use IEEE.STD_LOGIC_1164.ALL;
baudRateGenerator :
-- viz UART_baudRateGenerator port entity UART_baudRateGenerator
UART_baudRateGenerator.vhd map ( is
component Port ( clk
UART_baudRateGenerator clk
port (clk : in
: => clk, STD_LOGIC;
IN STD_LOGIC; enable
enable enable : in
STD_LOGIC;
: IN => enable, baudRateEnable
STD_LOGIC; : out
STD_LOGIC);
baudRateEnable baudRateEnable end UART_baudRateGenerator;
: OUT =>
STD_LOGIC baudRateEnable architecture Behavioral of
); ); UART_baudRateGenerator is
end component
UART_baudRateGenerator; transmitter : begin
UART_transmitter port map (
-- viz UART_transmitter.vhd -- Proces pro generovani
component UART_transmitter clk taktu pro odesilani dat pres
port (clk serovou linku.
: IN => clk, process (clk)
 variable clockCount -- konec
clockCount : := 0; periody citace
integer range 0 to 868 :=
0; -- citac pro generovani
signalu o periode 8,68 us -- reset citace baudRateEnable <= '1';
else
begin
if baudRateEnable <= '0'; -- nastaveni
rising_edge(clk) then vystupniho signalu
if
(enable = '0') then -- clockCount
zruseni vystupniho signalu := 0;

-- clockCount :=
zastaveni generatoru clockCount + 1; -- reset citace

baudRateEnable <= '0'; -- end if;

inkrementace citace end if;
end if;
-- if (clockCount = 434) end process;
zruseni signalu then
end Behavioral;

library IEEE; type transmitterState is (IDLE, -- priznak k

use IEEE.STD_LOGIC_1164.ALL; SEND_START_BIT, zahajeni odesilani
SEND_DATA_BITS,
entity UART_transmitter is SEND_STOP_BIT); begin
Port ( clk if
-- momentalni stav FSM rising_edge(clk) then
: IN STD_LOGIC; signal txState : if
enable transmitterState := IDLE; (enable = '0') then
: IN
STD_LOGIC; begin
baudRateEnable -- vypnuti
: IN STD_LOGIC; -- Proces pro odesilani odesilani
parallelDataIn dat pres seriovou linku
: IN process(clk) txState
STD_LOGIC_VECTOR (7 <= IDLE;
downto 0); variable dataToTx
transmitRequest :
: IN STD_LOGIC; STD_LOGIC_VECTOR(7 -- navrat do
txIsReady downto 0); -- vychoziho stavu
: OUT navzorkovany bajt dat k odeslani
STD_LOGIC; variable bitToSend txIsReady
serialDataOut : INTEGER <= '0';
: OUT STD_LOGIC); RANGE 0 TO 7 := 0;
end UART_transmitter; -- citac prave
odesilaneho bitu -- indikace
architecture Behavioral of variable go nepripravenosti k odesilani
UART_transmitter is :
STD_LOGIC := '0'; go
-- pouzite stavy FSM := '0';
 SEND_START_BIT;
when -- prechod do stavu
-- IDLE => SEND_START_BIT
zruseni priznaku k zahajeni
odesilani
-- vychozi stav end if;
serialDataOut <= '1';

txIsReady
-- <= '1';
nastaveni seriove linky do when
vychoziho stavu -- submodul SEND_START_BIT =>
else pripraven k odeslani dalsich dat
-- stav
if (transmitRequest = pro odeslani start bitu
'1') then serialDataOut <= '1';
--
prichod pozadavku k odesilani -- serialDataOut <= '0';
nastaveni seriove linky do
go := '1'; vychoziho stavu --
zacatek start bitu

if (go = '1') then

-- nastaveni txState
priznaku k zahajeni odesilani -- <=
zaznamenan pozadavek na SEND_DATA_BITS;
dataToTx odeslani dat -- prechod do stavu
:= parallelDataIn; SEND_DATA_BITS

-- go
navzorkovani prichozich dat := '0';

txIsReady -- when
<= '0'; zruseni priznaku k zahajeni SEND_DATA_BITS =>
odesilani
-- stav
-- indikace k pro odesilani dat
nepripravenosti k dalsimu bitToSend
odesilani := 0;
serialDataOut <=
end if; -- reset citace dataToTx(bitToSend); --
pro odesilany bit nastaveni seriove linky podle
if (baudRateEnable = '1') jednotlivych bitu dat
then
-- txIsReady
prichod taktu pro rychlost <= '0'; if (bitToSend = 7) then
odesilani 115 200 Bd
-- submodul prave --
case(txState) is odesila data odeslan posledni bit dat

txState txState <=

-- stavovy automat <= SEND_STOP_BIT;
 -- when
prechod do stavu SEND_STOP_BIT SEND_STOP_BIT => txState
<= IDLE;
-- stav
else pro odeslani stop bitu -- prechod do stavu IDLE

bitToSend := serialDataOut <= '1'; end if;

bitToSend + 1;
-- inkrementace citace -- end case;
prave vyslaneho bitu zacatek stop bitu
end if;
end if;
end if; if (transmitRequest = end if;
'0') then -- end process;
kontrola zruseni pozadavku na end Behavioral;
vysilani

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; sendRequest_H2 : IN -- viz transmitControler.vhd
STD_LOGIC; component transmitControler
entity transmitter is port ( clk
Port ( clk data_in_H2 : IN : IN
: IN STD_LOGIC_VECTOR(12 STD_LOGIC;
STD_LOGIC; DOWNTO 0);
enable : IN
enable STD_LOGIC;
: IN STD_LOGIC; serialDataOut : OUT
STD_LOGIC enable_LED : OUT
enable_LED : OUT ); STD_LOGIC;
STD_LOGIC; end transmitter; sendRequest_T1 : IN
STD_LOGIC;
sendRequest_T1 : IN architecture Structure of data_in_T1 : IN
STD_LOGIC; transmitter is STD_LOGIC_VECTOR (13 downto
0);
data_in_T1 : IN -- viz UART.vhd
STD_LOGIC_VECTOR(13 component UART sendRequest_T2 : IN
DOWNTO 0); port ( clk STD_LOGIC;
: IN data_in_T2 : IN
sendRequest_H1 : IN STD_LOGIC; STD_LOGIC_VECTOR (13 downto
STD_LOGIC; enable 0);
: IN STD_LOGIC;
data_in_H1 : IN serialDataOut : OUT sendRequest_H1 : IN
STD_LOGIC_VECTOR(12 STD_LOGIC; STD_LOGIC;
DOWNTO 0); parallelDataIn : IN data_in_H1 : IN
STD_LOGIC_VECTOR (7 STD_LOGIC_VECTOR (12 downto
sendRequest_T2 : IN downto 0); 0);
STD_LOGIC; transmitRequest : IN
STD_LOGIC; sendRequest_H2 : IN
data_in_T2 : IN txIsReady : OUT STD_LOGIC;
STD_LOGIC_VECTOR(13 STD_LOGIC); data_in_H2 : IN
DOWNTO 0); end component UART; STD_LOGIC_VECTOR (12 downto
0); =>
parallelDataOut : OUT enable,
STD_LOGIC_VECTOR (7 downto transmitRequest =>
0); transmitRequest, enable_LED
transmitRequest : OUT =>
STD_LOGIC; txIsready enable_LED,
txIsReady : IN =>
STD_LOGIC); txIsReady data_in_T1
end component ); =>
transmitControler; data_in_T1,

signal transmitRequest : transmitControler_1 : data_in_T2

STD_LOGIC := 'U'; transmitControler port map ( =>
signal txIsReady data_in_T2,
: STD_LOGIC := 'U'; clk
signal parallelDataOut : data_in_H1
STD_LOGIC_VECTOR(7 downto 0) => clk, =>
:= "UUUUUUUU"; data_in_H1,

begin sendRequest_T1 data_in_H2

=> =>
UART_1 : UART port sendRequest_T1, data_in_H2,
map (

clk sendRequest_T2 parallelDataOut =>

=> parallelDataOut,
=> clk, sendRequest_T2,

enable transmitRequest =>

=> sendRequest_H1 transmitRequest,
enable, =>
sendRequest_H1, txIsReady
serialDataOut =>
=> txIsReady
serialDataOut, sendRequest_H2 );
=>
parallelDataIn sendRequest_H2, end Structure;
=>
parallelDataOut, enable
Analysis & Synthesis
To check the results on Vector Waveform we need to first perform analysis and synthesis, to
check that there is no error in the program and we can then verify our design through Vector
Waveform (VWF) results and RTL Diagram.

RTL Diagram
Technology Map Viewer

Vector Waveform Results

In Vector Waveform we need to set the input values, to verify that our desired program is
working correctly
Vector Waveform Compilation

Conclusion
In this project we have implemented using VHDL in Altera Quartus II. The simulation results
demonstrate the effectiveness of the approach and it can be seen that the desired level of
performance can be attained using FPGA. The Vector Waveform Results demonstrate the efficacy
of the proposed approach.
References

1.“Removal of Impulse Noise Using Switching Median Filter by designing its Reconfigurable
Architecture” – Manali Mukherjee, Mausumi Maitra, Kamarujjaman - International Conference
on Communication and Computing ICC–2014, Bangalore, June 12-14, 2014 (Elsevier Science
and Technology Publication).

2. A New Decision-Based Adaptive Filter for Removal of High Density Impulse Noise from
Digital Images - Kamarujjaman, Manali Mukherjee and Mausumi Maitra, ICDCCOM - 2014,
September 12-13, 2014, BIT Mesra (IEEE Explorer publication)

3. An Efficient Approach for Suppression of Impulse Noise from Digital Images using Decision-
Based Adaptive filter- Kamarujjaman Sk, Manali Mukherjee and Mausumi Maitra, Accepted in
ICECE-14, BUET, Bangladesh, to be held during December, 2014 (not presented due to lack of
fund).

4.Reconfigurable Architecture of Adaptive Median Filter – A FPGA Based Approach for Impulse
Noise Suppression – Manali Mukherjee, Kamarujjaman, Mausumi Maitra was published by
IEEE Xplore. Presented in 3rd International Conference on Computer, Communication, Control
and Information Technology (C3IT), 2015, was held in Academy of Technology, Adisaptagram,
during 7th – 8th February, 2015.

5.Kamarujjaman, Manali Mukherjee and Mausumi Maitra, “An efficient FPGA based de-noising
architecture for removal of high density impulse noise in images”, IEEE International
Conference on Research in Computational Intelligence and Communication Networks
(ICRCICN), RCCIIT, Kolkata, Sept., 2015.