2019 5th International Conference for Convergence in Technology (I2CT)
Pune, India. Mar 29-31, 2019
Control Approach for a High Voltage Gain
Dual Input Boost DC-DC Converter
Mohan Appikonda
Student Member, IEEE
Department of Electrical and Electronics Engineering
National Institute of Technology
Tiruchirappalli - 620015, TamilNadu, India
appikonda.mohan@gmail.com
Abstract—A DC-DC converter combined with dual input, dual
boost at the input, integrated voltage multiplier cell (VMC) and
larger duty cycles is needed to easily achieve a high voltage
gain from the independent renewable energy resources (RES)
which may be two solar photovoltaic (PV) energy sources. During
load changes and input disturbances, the output voltage is to
be regulated, which requires suitable control design. This paper
presents the procedure for control design of the converter from its
small signal transfer function model. The uncontrolled system is
characterised by right-half s-plane zero (RHPZ) in the control to
output voltage transfer functions and its performance is analysed.
A dual loop control strategy employing PI with compensator is
adopted and simulated using MATLAB. The results ensure the
voltage regulation and active current sharing among the two DC
sources.
Index Terms—small-signal model, voltage multiplier cell
(VMC), right-half-plane-zero (RHPZ), dual loop control, voltage
regulation, active current sharing
I. I NTRODUCTION
Renewable energy sources (RESs) are expanding its
significance and acclaim in an alternative to fossil fuels.
Among others, the interesting of RES is solar power owing
to eco-friendly, fixed near the load points and require less
maintenance. However, solar energy has intermittency, and
single photovoltaic (PV) array generate a low output voltage.
To overcome these issues, multiple input sources and high
voltage gain boost converter; typically greater than 10 are
required. To achieve high voltage gain the turn ratio of
the transformer is increased in isolated type of converter,
where as in the non-isolated topologies require strategies
such as switched-capacitor, coupled-inductor, cascaded or
interleaved. Former provide the galvanic isolation, however
difficulties, such as power transformer design, electromagnetic
interference and high leakage inductance in comparison with
the non-isolated type. For portable electronic equipment where
DC-DC isolation is not must, the switched-capacitor based
boost converter is the ideal choice.
The boost converter with the above strategies achieves high
voltage gain. However, the converter alone cannot regulate
the output voltage without the controller. Converter control
design is primarily, based on the mathematical modelling and
analysis. Many high voltage gain DC-DC boost converter
978-1-5386-8075-9/19/$31.00 ©2019 IEEE
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Dhanalakshmi K.
Senior Member, IEEE
Department of Instrumentation and Control Engineering
National Institute of Technology
Tiruchirappalli - 620015, TamilNadu, India
dhanlak@nitt.edu
topologies with voltage multiplier cell (VMC) are available
in the literature. Still, not many works reported in converter
control. The dynamic model of the reduced-order boost
converter with single VMC and the proportinal-integral (PI)
controller design presented in [1]. Voltage multiplier integrated
quadratic boost converter, and the corresponding current mode
controller design reported in [2]. Single VMC integrated boost
converter and sliding mode control discussed in [3]. A new
high voltage-gain boost converter topology proposed in [4]. It
includes the dual source, and two input boost stages combined
with VMCs to achieve high voltage gain. Also, the larger duty
ratios of the two active switches preferred to attain a high gain.
The complete dynamic model of this converter is still not
available in the literature. The main focus of this paper is to
present the small signal transfer function model considering
the internal series resistance of the energy storing elements and
to investigate the control strategy for output voltage regulation
of this converter with a single VMC.
The The right-half s-plane zero (RHPZ) in the system
transfer function leads to non-minimum phase behavior of
the system. For DC-DC converters usually, voltage mode
control strategy is followed for voltage regulation. But, for
non-minimum phase system, dual loop control strategy is
adopted to avoid narrow closed-loop bandwidth. An inner
current loop with current controller and outer voltage loop
with the voltage controller designed in this work.
This paper organized as follows: in section II, the small
signal model of the converter with a single VMC is presented.
Section III describes the dual loop control strategy with inner
current loop and outer voltage loop. Section IV discusses the
simulation and section V concludes the paper.
II. S MALL SIGNAL MODEL OF THE CONVERTER WITH
SINGLE VMC
The small signal averaged state-space technique, a general
analysis tool is applied to the converter circuits to obtain
the linear averaged time-invariant models. The following
assumptions are adopted to simplify the derivation of the
model: 1) The major components (MOSFETs and diodes)
are ideal 2) voltage sources are constant and 3) continuous
1
 v̂out (s) −4.396 ∗ 105 (s + 5.165 ∗ 106 )(s − 1.249 ∗ 105 )
G1 (s) = = 2 (1)
dˆ1 (s) (s + 200.5s + 1.114 ∗ 107 )(s2 + 144.1s + 7.978 ∗ 107 )
v̂out (s) −70902(s − 1.28 ∗ 105 )(s2 + 115.5s + 3.125 ∗ 107 )
G2 (s) = = 2 (2)
dˆ2 (s) (s + 200.5s + 1.114 ∗ 107 )(s2 + 144.1s + 7.978 ∗ 107 )

îL1 (s) 7.99 ∗ 105 (s + 178.6)(s2 + 300.6s + 5.96 ∗ 107 )

G3 (s) = = 2 (3)
dˆ1 (s) (s + 200.5s + 1.114 ∗ 107 )(s2 + 144.1s + 7.978 ∗ 107 )

îL2 (s) 7.99 ∗ 105 (s + 341.3)(s2 + 365s + 3.122 ∗ 107 )

G4 (s) = = 2 (4)
dˆ2 (s) (s + 200.5s + 1.114 ∗ 107 )(s2 + 144.1s + 7.978 ∗ 107 )

L1 Single VM TABLE I: Circuit Parameter Values

Parameters Values
Vin1 S1
Vin1 , Vin2 20 V
D1 Dout d1 , d2 0.75
L1 , L2 100 μH
rL1 , rL2 11 mΩ
c1 c1 20 μF
L2 + rc1 2.2 mΩ
Cout Vout R Cout 22 μF
− rCout 8.8 mΩ
Vin2
S2 R 400 Ω
fs 100 kHz

Fig. 1: High voltage gain boost converter with single VMC.

4
1.0x10

10000
Poles Poles
Zeros Zeros
mode-I mode-II mode-I mode-III
3
5.2x10

5000
TS
S1

Imaginary Axis
Imaginary Axis

d 1 TS
0.0

0
TS t
S2
3
-5.2x10

-5000
d 2 TS

t
4
-1.0x10

6 5

Real Axis
-5.2x10 0.0 1.0x10 -200 -100 0 126000 128000 130000

Fig. 2: Switching signals for the boost converter. Real Axis

(a) G1 (s) (b) G2 (s)

conduction mode (CCM) of operation. The parasitic resistance
of inductors and capacitors are considered in the modelling.
Figure 1 shows the dual input high voltage gain DC-DC
boost converter with single VMC. Fig. 2 shows the gating
signals for the two switches S1 and S2 with the duty ratio of
d1 and d2 respectively. The small-signal transfer functions of
this converter in CCM are presented in this section.
For the circuit parameter values given in Table I the
corresponding output voltage to duty cycle small-signal
transfer functions of switches S1 and S2 are represented in
(1)and (2). The inductor current to duty cycle small-signal
transfer functions corresponding to switches S1 and S2 are
represented in (3) and (4).
III. C ONTROL STRATEGY FOR OUTPUT VOLTAGE
REGULATION
The output voltage to duty cycle transfer function
corresponding to switch S1 and S2 given in (1), (2) and their
Fig. 3: Open loop poles and zeros
respective pole-zero map in s-plane shown in Fig. 3. The poles
of the derived transfer functions in (1) - (4) have the negative
real part, which implies that the open loop system is stable.
Whereas, for the output voltage to duty cycle transfer functions
in (1), (2) have one of the zeroes with the positive real part,
which implies the system is the non-minimum phase and that
cause the closed-loop system unstable. The gain margin of
G1 (s) and G2 (s) without a controller in the closed-loop is
negative, which indicates the system is unstable. Also, the
output voltage is unregulated during step change in load and
input as shown in Fig. 4.
A dual loop control strategy is chosen to regulate the output
voltage. The single-input single-output (SISO) system have a
single input current loop and output voltage loop. Whereas
for the double-input single-output (DISO) system have two

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 where fs is the switching frequency.

Considering the two sources are not identical, i.e., Vin1 as

a low power voltage source compared to Vin2 [8]. The current
references for the two current controllers Ci1 (s) and Ci2 (s)
are not identical as shown in Fig. 5, which results in the
imbalance of two inductor currents IL1 and IL2 i.e voltage
source Vin2 supply the major load share. The procedure for
the compensators design are as follows:

A. Design of input current controller

The design objectives of the current loop compensators
Ci1 (s) and Ci2 (s) are to achieve the 1) gain margin (GM)
greater than 20 dB 2) phase margin (PM) of 90° and 3)
crossover frequency of decade below the switching frequency
(a) Load distubance (b) Line disturbance (up to 10 kHz) for their corresponding compensated current
Fig. 4: Output voltage without controller. control loops and their loop gains are given by Til (s) and
Ti2 (s). Toil (s) and Toi2 (s) are the uncompensated current loop
gains as shown in Fig. 6.
input current loops and output voltage loops corresponding to
power converter
two independent sources Vin1 and Vin2 [7] as shown Fig. 5. vref v
^err
Cv1 (s)
^
iL1r ^
iL1e
Ci1 (s) PWM1
d^1 ^
iL1
^
iL1 v
^out
^
The current and voltage compensators corresponding to source +
- +
− d^1 iL1
+
v
^out
Ti1 (s)
Ri1 (s)
L1 +
^
iL2r ^ ^
iL2e d^2 ^
iL2 iL2 v
^out
Cv2 (s) Ci2 (s) PWM2 ^
PWM1 Ci1 (s) Ri1 (s) + d^2 iL2
−

Vin1 S1
− Ti2 (s)
Ri2 (s)
D1 Dout
+
Hv (s)
Cv1 (s)

c1
Fig. 6: Closed-loop block diagram of input current loops.
L2 +
Cout Vout R
−
Vin2
S2 Toil (s) = Ri1 (s) ∗ P W M1 (s) ∗ G3 (s) ∗ He (s) (7)

Toi2 (s) = Ri2 (s) ∗ P W M2 (s) ∗ G4 (s) ∗ He (s) (8)

PWM2 Ri2 (s) Rv (s) Til (s) = Toil (s) ∗ Ci1 (s) (9)
− −
+
Ci2 (s) Cv2 (s)
+
Ti2 (s) = Toi2 (s) ∗ Ci2 (s) (10)
vref
The closed-loop transfer function of the inner current loop
Fig. 5: Block diagram of the converter with single VMC. corresponding to sources Vin1 and Vin2 are as follows:

Vin1 are namely Ci1 (s) and Cv1 (s). Whereas for source Vin2 P W M1 (s) ∗ G3 (s) ∗ Ci1 (s)
G3,CL (s) = (11)
are Ci2 (s) and Cv2 (s). Ri1 (s) and Ri2 (s) are the current 1 + Til (s)
sensing resistances from inductors L1 and L2 respectively. P W M2 (s) ∗ G4 (s) ∗ Ci2 (s)
Hv (s) is the voltage sensing gain from the load. P W M1 (s) G4,CL (s) = (12)
1 + Ti2 (s)
and P W M2 (s) are the pulsewidth modulated (PWM) dynamic
model. Here chosen that Ri1 (s) = Ri2 (s) = 0.25 and Hv (s) =
1 0.1. P W M1 (s) = P W M2 (s) = 0.25 given in (5). G3 (s)
P W M1 (s) = P W M2 (s) = (5)
VM and G4 (s) given in (3) and (4) respectively. The current
loop compensators are appropriately tuned using MATLAB
where VM = 20 V is the peak-to-peak amplitude of the
SISOtool to achieve the design objectives and are given by
triangular carrier wave. He (s) represents the effects of
Ci1 (s) = 1.22 and Ci2 (s) = 1.2.
high-frequency ripples from the PWM in the form of transfer
Ci1 (s) provides a PM of 88.1° (wpc of 510 kHz) and a GM
function [1] and considered in the feedback loop.
of 30.3 dB (wgc of 9.78 kHz) as shown in Fig. 7a. Ci2 (s)
s2 s provides a PM of 87.9° (wpc of 510 kHz) and a GM of 30.5 dB
He (s) = − +1 (6) (wgc of 9.7 kHz) as shown in Fig. 7b.
(πfs )2 2fs

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 60 60 80
Ti1(s) Ti2(s) 60 Tv1(s) Tv2(s)

Magnitude (dB)
Magnitude (dB) Toi1(s) Tov1(s) 40
40
Toi2(s) T0v2(s)

Magnitude (dB)
40
0

Magnitude (dB)
20 0
20
-60

-40
0
0 -120

-80
-20
-20 -180
-120
-40
-40 -240
450
450 360 360
Phase (deg)

270
360

Phase (deg)
360 270

Phase (deg)

Phase (deg)
180
270 180
270
90
180
0 90
180

90
-90 0
90
0 -180
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

Frequency (Hz) Frequency (Hz) Frequency (Hz) Frequency (Hz)

(a) Til (s) and Toil (s). (b) Ti2 (s) and Toi2 (s). (a) Tvl (s) and Tovl (s). (b) Tv2 (s) and Tov2 (s).
Fig. 7: Bode plot of current loop gain. Fig. 9: Bode plot of voltage loop gain.

B. Design of output voltage controller The closed-loop output voltage to input current transfer
function corresponding to sources Vin1 and Vin2 are as
The design objectives of the voltage loop compensators follows:
Cv1 (s) and Cv2 (s) are to achieve the 1) positive gain
G3,CL (s) ∗ G5 (s) ∗ Cv1 (s)
margin (GM) 2) phase margin (PM) of 25° and 3) crossover G5,CL (s) = (19)
frequency of decade below the crossover frequency of 1 + Tv1 (s)
inner current loop compensator (up to 1 kHz) for their G4,CL (s) ∗ G6 (s) ∗ Cv2 (s)
corresponding compensated voltage control loops as shown G6,CL (s) = (20)
1 + Tv2 (s)
in Fig. 8. The closed-loop DISO system can be viewed
The design of output voltage compensator based on the
as the two independent closed-loop SISO systems. Each
closed-loop input current to the duty cycle (3), (4) and output
of these closed-loop SISO systems can be seen as a
voltage to input current transfer functions (13), (14). The
voltage-controlled current source and their compensated loop
transfer functions corresponding to Cv1 (s) and Cv2 (s) are
gains are given by Tv1 (s) and Tv2 (s). Tov1 (s) and Tov2 (s)
given as follows:
are the uncompensated voltage loop gains. G5 (s) and G6 (s)
are the output voltage to input current transfer function 23.08(s + 7938)
Cv1 (s) = (21)
corresponding to sources Vin1 and Vin2 are as follows: s(s + 2.68 ∗ 104 )
v̂out (s) G1 (s) 1.5 ∗ 105 (s + 1423)
G5 (s) = = (13) Cv2 (s) = (22)
îL1 (s) G3 (s) s(s + 1.952 ∗ 105 )
Cv1 (s) provides a PM of 19.1° (wpc of 654 Hz) and a GM of
v̂out (s) G2 (s) 19.2 dB (wgc of 180 Hz) as shown in Fig. 9a. Cv2 (s) provides
G6 (s) = = (14)
îL2 (s) G4 (s) a PM of 24° (wpc of 10 kHz) and a GM of 14.5 dB (wgc of
867 Hz) as shown in Fig. 9b.
Tov1 (s) = G5 (s) ∗ G3,CL (s) ∗ Hv (s) (15) C. Design of inductor current balancing controller
Considering the voltage sources Vin1 and Vin2 are identical.
Tov2 (s) = G6 (s) ∗ G4,CL (s) ∗ Hv (s) (16)
In order to avoid the current imbalance among the two
DC sources, the current-balancing is integrated in the
Tv1 (s) = Tovl (s) ∗ Cv1 (s) (17) control strategy. Here the dominant among the two voltage
compensators Cv1 (s) and Cv2 (s) is chosen as the common
Tv2 (s) = Tov2 (s) ∗ Cv2 (s) (18) voltage compensator Cv (s). The current reference generated
from voltage compensator Cv (s) is shared by the two current
compensators as shown in Figs. 10 and 11, which results in
vref v
^err ^
iL1r ^
iL1 v
^out
Cv1 (s) G3;CL (s) ^ equal current sharing among the two sources Vin1 and Vin2
+
- iL1 +
v
^out with voltage regulation under different scenarios.
^ ^ +
iL2r iL2 v
^out
Cv2 (s) G4;CL (s) ^
iL2
IV. SIMULATION RESULTS

Tv2 (s) Tv1 (s)

The output voltage without controller for a load step from
Hv (s) 50 % to 100 % of the full load, at time t = 0.02 sec and a
load reduced from 100 % to 50 % of the full load, at time t
Fig. 8: Closed-loop block diagram of output voltage loops. = 0.04 sec is shown in Fig. 4a. The output voltage without

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 power converter
Vref v
^err ^
iL1r ^
iL1e d^1 ^
iL1
^
iL1 v
^o ut
Cv (s) 0:5 Ci1 (s) PWM1 ^
+
- +
− d^1 iL1
+
v
^out
Ti1 (s)
Ri1 (s)
+
^
iL2r ^ ^
iL2e d^2 ^
iL2
v
^o ut
Ci2 (s) iL2
PWM2 ^
+ d^2 iL2
−

Ti2 (s)
Ri2 (s)

Hv (s)

Fig. 10: Closed-loop block diagram of input current loops and

equal current sharing.

vref v
^err ^
iL1r ^
iL1 v
^out
Cv1 (s) 0:5 G3;CL (s) ^
+
- iL1 +
v
^out
^
iL2r
^ +
iL2 v
^out
G4;CL (s) ^
(a) Load distubance (b) Line disturbance
iL2

Tv2 (s) Tv1 (s)

Fig. 13: Voltage regulation and balanced currents.
Hv (s)

Fig. 11: Closed-loop block diagram of output voltage loop V. C ONCLUSION

equal current sharing.
controller for a source voltage Vin1 reduced from 20 V to
10 V at time t = 0.06 sec and a voltage step from 10 V to
20 V at time t = 0.08 sec is shown in Fig. 4b.During the load
and line disturbances, the output voltage drops permanently
without regulating to the actual value but regulates only with
the removal of the disturbances. Voltage regulation is observed
with the use of controller and shown in Fig. 12. The source
Vin2 supply major load current share among the two DC
sources with the implementation of control strategy shown in
Fig. 6. Voltage regulation with equal current sharing is shown
in Fig. 13 with the implementation of control strategy shown
in Fig. 10.
(a) Load distubance
Fig. 12: Voltage regulation and major load share from Vin2 .
This paper presents a small-signal dynamic model of dual
input high voltage gain DC-DC boost converter with a VMC
and operates at the extreme duty cycle. The validity of the
derived model have performed through MATLAB and PSIM
simulation. The stability study shows that the closed-loop
non-minimum system is unstable. Dual loop control strategy
with simple PI and lead compensator has designed. Voltage
regulation has achieved with the designed controller under load
and line disturbances. The simulation results corroborate the
performance of the designed controller.
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