IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO.
10, OCTOBER 2011
Ageing and Failure Modes of IGBT Modules in
High-Temperature Power Cycling
Vanessa Smet, Francois Forest, Member, IEEE, Jean-Jacques Huselstein, Frédéric Richardeau,
Zoubir Khatir, Stéphane Lefebvre, and Mounira Berkani
Abstract—This paper presents an experimental study on the
ageing of insulated-gate bipolar transistor (IGBT) power modules.
The aim is to identify the effects of power cycling on these devices
with high baseplate temperatures (60 ◦ C to 90 ◦ C) and wide
temperature swings (60 ◦ C to 100 ◦ C). These values for thermal
stresses have been defined according to automotive applications.
The test conditions are provided by two types of test benches
that will be described in this paper. The changes in electrical
and thermal indicators are observed regularly by a monitoring
system. At the end of the test (reaching damage criterion or
failure), different analyses are performed (acoustic scanning and
SEM imaging), and the damage is listed systematically. Nineteen
samples of 600-V 200-A IGBT modules were thus aged using five
different power-cycling protocols. The final summary of results
shows that ageing mechanisms mainly concern wire bonds and
emitter metallization, with gradual impact depending on protocol
severity.
Index Terms—Power electronics, reliability testing, semicon-
ductor devices.
I. I NTRODUCTION
P OWER semiconductor devices are the main components
of power electronic systems, as well as one of their most
critical parts in terms of reliability.
Considering the increasing role of power electronic convert-
ers in critical functions, particularly in human transport appli-
cations [1]–[5] with significant safety requirements, features
such as reliability, lifetime, health monitoring, and predictive
maintenance become increasingly important. In addition, in
this application context, the operating conditions often induce
stress, particularly high ambient temperatures and strong tem-
perature variations.
Manuscript received February 21, 2010; revised May 25, 2010, July 21,
2010, and November 7, 2010; accepted January 25, 2011. Date of publication
February 10, 2011; date of current version August 30, 2011.
V. Smet, F. Forest, and J.-J. Huselstein are with the Université of
Montpellier 2, Institut d’Electronique du Sud, 34095 Montpellier CEDEX 5,
France (e-mail: vanessa.smet@ies.univ-montp2.fr; forest@univ-montp2.fr;
huselstein@univ-montp2.fr).
F. Richardeau is with Laboratoire Plasma et Conversion d’Energie, In-
stitut National Polytechnique de Toulouse, 31000 Toulouse, France (e-mail:
frederic.richardeau@Laplace.univ-tlse.fr).
Z. Khatir is with the Laboratory of New Technology, French Institute of
Science and Technology for Transport, Development and Networks, 78000
Versailles, France (e-mail: khatir@inrets.fr).
S. Lefebvre is with Ecole Normale Supérieure de Cachan, Systèmes et
Applications des Technologies de l’Information et de l’Energie, 94230 Cachan,
France (e-mail: lefebvre@satie.ens-cachan.fr).
M. Berkani is with University of Paris XII, 94010 Paris, France (e-mail:
mounira.berkani@satie.ens-cachan.fr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2011.2114313
0278-0046/$26.00 © 2011 IEEE
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4931
This paper presents ageing procedures, failure modes, and
lifetime estimation for standard insulated-gate bipolar transistor
(IGBT) modules used in harsh thermal conditions. The study is
mainly experimental. On the one hand, its originality results
from the high number of tested samples and, on the other hand,
from the high temperature stress (up to 170 ◦ C) applied to the
samples in power-cycling operating modes.
Section II of this paper describes the main causes and effects
of power cycling, described as the general research orientations
on the topic. In the subsequent two sections, the aims of this
paper are defined, and tests and analysis methodologies are
explained. The last section presents the experimental results and
analysis concerning the ageing of IGBT modules.
II. K NOWN C AUSES AND E FFECTS OF P OWER
C YCLING IN P OWER E LECTRONICS
A. Thermal Cycling and Power Cycling in High Temperature
Thermal stresses have two origins in power electronics. The
first origin is power cycling, obtained when using converters
subject to load variations due to mission profiles that induce
loss variations in the power devices. The second origin is the
thermal cycling due to the variations of the surrounding thermal
environment in which the converters are placed.
Power converters used in transport applications typically un-
dergo both cycling modes, with different levels of temperature
swings and frequency. In ground or air transport applications,
converters operate under intermittent and/or variable-load con-
ditions that create power cycling. Thus, the temperature range
on chips is typically situated between 30 ◦ C and 60 ◦ C, leading
to lifetimes greater than one million cycles. In addition, the
power module can be submitted for a few thousand cycles with
ambient temperatures that can vary over a very broad range
(−40 ◦ C to −55 ◦ C in cold ground zones and 120 ◦ C near
engines).
B. Main Effects on Semiconductor Power Devices
At this time, the main effects of thermal and power cycling on
IGBT power modules have been quite well known for about ten
years [6]–[10]. These effects are thermomechanical and mainly
concern the layer assembly under the chips and the connections.
They lead to fracture initiation and propagation in solders and
in the different interface layers of the direct-bonded-copper
(DBC) substrates, but they also generate metallurgical damage
to wire bonds and emitter metallization.
4932
C. Study Goals
Different methods are investigated on the topic related to
the reliability and failure modes of power devices and the
consequences on converters and systems. A first main direction
is the analysis and modeling of ageing mechanisms in order
to estimate lifetimes or improve technologies. The resulting
works are based on thermomechanical considerations [11]–[16]
and are frequently sustained by the use of finite-element (FE)
simulation tools [17]–[19]. These models must be validated for
any components or systems by experimental results, which are
very difficult and very time consuming to obtain.
Other considerations to be addressed are the consequences
and management of faults during converter operation [20]–[25].
In this respect, it is essential to consider redundancy options
or degraded operating modes. This concerns many applications
for which availability and/or safety are critical, such as embed-
ded power systems for human transport, which are typical in
this area.
Health monitoring is another important point of study [26]–
[29]. It is an essential step for developing efficient approaches
to predictive maintenance.
III. P RESENTATION OF THE S TUDY
This paper mainly deals with the ageing and failure modes
of standard IGBT power modules operating under harsh tem-
perature cycling conditions and in high temperature ranges (for
silicon). It is more specifically dedicated to ground and air
transport applications. This is part of a larger project that also
addresses the problem of thermal cycling [30].
The term “ageing mode” defines a degradation process that
leaves the device functional. Metallurgic degradation of metal-
lization or wire bonds is typical of this type. The term “failure
mode” is associated with a destructive process that renders the
device nonfunctional, as a thermal runaway of the chip (short
circuit) or as a completely broken connection (open circuit).
Ageing modes inevitably lead to failure modes if device opera-
tion is not interrupted in time.
A. Context-Tested Devices
Different kinds of power-cycling tests were used on various
power modules. The originality of this work arises from the par-
ticular test conditions applied to the power devices (switching
under nominal conditions and pulsewidth modulation (PWM)
operating mode) from high thermal stress values (up to 90 ◦ C
for the baseplate temperature and up to 170 ◦ C on chips) and
from the high number of tested samples.
The tested IGBT power modules were chosen because they
represent current technologies. The general aim is not to char-
acterize these specific devices in particular, but to obtain as
many generic results as possible. Modules include three inverter
legs (see Fig. 1) and use the most current assembly technology,
alumina-copper DBC, and aluminum wire bonds.
Further connection technologies have been developed and
seem more robust, but wire bonds still represent the most
frequently used technology.
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 10, OCTOBER 2011
Fig. 1. Interior view of the tested module.
Typical electrical ratings are 600 V and 200 A, which
are specifications in accordance with the target context, and
the maximal junction temperature is 175 ◦ C. The three-phase
structure allows ageing four or six IGBTs simultaneously (see
Section IV-A).
B. Goals
Based on the application of high thermal stress, the aims of
this paper are as follows:
1) to compare obtained ageing modes with those resulting
from more classical stress;
2) to estimate and validate the capability of high-
temperature test protocols to accelerate ageing;
3) to compare two test methodologies, with power cycling
generated by dc current injection without high voltage
(typical usage) or by current injection under switching
conditions, such as for a real converter;
4) to evaluate commonly used ageing indicators VCEo (ON-
state voltage) and RTHJC (junction to case or baseplate
thermal resistance) in these particular test conditions;
5) to assess failure modes by allowing chip destruction
under controlled conditions.
This last aspect is directly connected to the design problem
of fault-tolerant converters. Such orientation requires knowing
the failure mechanisms of the power devices in order to define
appropriate redundancy and reconfiguration strategies. The au-
thors are currently working on this topic, and this paper has
contributed to providing relevant information on that topic.
IV. AGING T EST B ENCHES
A. Power Part of the Test Benches
Two test benches were developed according to each of the
goals mentioned in the previous section. These are referred to
as the dc test bench and the PWM test bench, respectively.
In both cases, the thermal stress is identical, and the electrical
power consumption is limited to the loss generated in the IGBT
power modules.
1) DC Test Bench: The goal of dc current injection (see
Fig. 2) is to induce thermal stress by creating a thermal flux
in the IGBT module.
The advantages of the dc test bench are the relative simplicity
and the possibility to easily perform “online” measurements
of electrical and thermal indicators without stopping power
SMET et al.: AGEING AND FAILURE MODES OF IGBT MODULES IN HIGH-TEMPERATURE POWER CYCLING
Fig. 2. DC test bench.
cycling. Conversely, the electrical excitation of devices is not
realistic (no switching and no high voltage).
The dc test bench allows the simultaneous testing of three
IGBT modules. These modules are mounted on plate heat
exchangers using water-glycol circulation of which temperature
and flow are regulated. The plate temperature is the reference
temperature for the tests. The junction temperature is ad-
justed by controlling the duration and amplitude of the current
injection.
2) PWM Test Bench: The PWM test bench was designed
to generate power cycling with realistic electrical stress on the
power devices.
Two legs (two DBCs) of the IGBT module are joined to con-
stitute a single-phase PWM inverter (see Fig. 3). Its switching
frequency is adjustable between 13 and 30 kHz, and it provides
a regulated sinusoidal current (100 Hz) to an inductive load (no
loss). For power devices, the operating conditions are similar to
those existing in a drive inverter. The principle of this test bench
is described in [31] in more detail.
The PWM test bench is modular. The previous arrangement
(one module) constitutes an elementary block. Six elementary
blocks were used for this paper (six modules). The IGBT
module is mounted on a copper spreader that is mounted on
a typical air heat exchanger. In order to extract the thermal
flux from the test room, this first part is placed in a closed
chamber and associated with a coupled air–water exchanger/fan
(see Fig. 3).
The water circuit operates at low temperature and pressure,
with a constant flow. It is connected to an outdoor cooling stage.
The spreader temperature is the reference temperature for the
tests. This temperature may be adjusted between 40 ◦ C and
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4933
Fig. 3. Elementary block of the PWM test bench.
120 ◦ C (for a thermal flux up to 1100 W) by regulating the fan
speed.
Power cycling is generated by periodically allowing PWM
operation. Cycles are controlled by the maximal value of
the sinusoidal current and the duration of its injection. Here,
the switching frequency is another control parameter because
switching loss is significant in the chosen frequency range and
contributes to thermal flux generation.
It is worth noting that this property makes power-cycling
adjustment possible without any change to the electrical stress
amplitude.
B. Monitoring
Both test benches are driven by controlling/monitoring sys-
tems that include sensors (temperature, voltage, and current),
PWM controller boards (one for two blocks), data acquisition
boards (one for two blocks), and personal computers that handle
supervision using LabView tools. Measurements of the differ-
ent temperatures are automated.
Three parameters are generally considered as good ageing
indicators in power device ageing tests and are monitored:
the thermal resistance between the junction and the baseplate
(RTH ), the ON-state voltage (VCEo ), and the gate threshold
voltage (VGSTH ).
RTH is an indicator for characterizing the assembly integrity
between the IGBT die and the baseplate. RTH increases if a
4934
Fig. 4. Monitoring on test bench. (a) Thermal instrumentation of a module in
dc test bench. (b) Thermal instrumentation of a module in PWM test bench.
fracture appears and significantly modifies the heat transfer. Its
evaluation is the most delicate and requires measuring junction
and baseplate temperatures under a fixed thermal flux.
The VCEo measurement makes it possible to detect wire
bonds or emitter metallization damage. The relative variations
due to this damage are very low because the voltage across
the connections constitutes a weak part of the total ON-state
voltage. Therefore, this measurement must be made with a very
high degree of accuracy.
Lastly, VGSTH is measured to identify changes in the gate ox-
ide properties that should induce changes in electrical behavior.
This classical monitoring protocol was chosen, and measure-
ments of the three parameters were made regularly (interval of a
few thousand cycles) under controlled conditions (temperature,
current, and thermal flux).
The monitoring process is quite similar for both test benches.
All temperatures are measured in operation, while sampled
values are stored continually. Indicator measurements are taken
every few thousand cycles (from 1000 to 5000, depending on
the ageing process) under low-voltage conditions, with PWM
operations stopped and the high-voltage source disconnected.
Measurements are not carried out “online” because of the dif-
ficulty in mixing accurate low-level measurements and power
injection, particularly with the PWM test bench. Electrical
conditions, particularly the current, are not modified during the
test. If RTH or VCEo increases, the junction temperature also
increases by a few degrees. This procedure is recognized as the
most realistic with respect to applications and is generally used
in power-cycling tests.
The ageing criteria leading to the test stop are the RTH
increase of 20% and the VCEo increase of a few percent.
Fig. 4(a) and (b) shows the thermal sensor positioning in
and around the modules. The baseplate sensors are placed in
holes made respectively in the water plate for the dc bench (one
sensor under each chip) and in the copper spreader for the PWM
bench. The main difference between the two test benches lies
in the junction temperature measurement. This is performed
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 10, OCTOBER 2011
by thermo-optical sensors in the PWM test bench and by an
indirect method performed on each chip in the dc test bench
(VCEo measurement with low current after thermal calibration).
A particular feature of the PWM test bench is the capability
to reach local failure modes by avoiding fault propagation.
The IGBT drivers include short-circuit protection. When fail-
ure occurs in a chip, the short circuit created through the
leg is detected by the other driver, which transmits a fault
signal immediately to the PWM controller, and the healthy
IGBT is turned off. The total turnoff delay is around a few
microseconds.
V. E XPERIMENTAL R ESULTS AND A NALYSIS
Two sets of tests were performed. The first test included two
protocols that were applied to both test benches to evaluate the
possible impact of different electrical stresses on device ageing.
Using three protocols, the second set of tests was carried out
only on the PWM test bench to complete and refine the results.
A. General Test Conditions
Every 5000 cycles, the three indicators (RTH , VCEo ,
and VGSTH ) are measured for a junction temperature of 125 ◦ C.
If any change is detected, the period is reduced to 2500 cycles,
or even to 1000 cycles in the cases of severe degradation. The
test continues until it reaches the stop criteria or the destruction
of the component if no change is detected (see Section V-D3).
Before starting the tests, each IGBT module undergoes
acoustic analysis in order to evaluate the initial state of the two
solder layers between the die and the baseplate. When a sample
is considered as faulty, a second acoustic analysis is performed.
Then, it is opened for a final analysis sequence:
1) preliminary examination under an optical microscope;
2) SEM examinations with the systematic positioning of the
different visible damage zones;
3) in some cases, the cutting and creation of polished cross
sections for examination under a SEM.
B. First Test Series
Both protocols of this series are based on a reference temper-
ature set to 90 ◦ C. Two values for junction temperature variation
are then set, 60 ◦ C (protocol 1-1) and 80 ◦ C (protocol 1-2),
adjusted by the thermal flux generated in the chips. The cycle
durations are 30 and 45 s, respectively. The main results are
given in Table I, which also indicates the number of samples
tested in each case.
C. Second Test Series
The second protocol series only used the PWM test bench
(see Section V-D1). Three protocols were chosen according to
a logical progression of thermal stress:
1) Protocol 2-1: Treference = 60 ◦ C, ΔTJ = 60 ◦ C, and
TJM = 120 ◦ C;
2) Protocol 2-2: Treference = 60 ◦ C, ΔTJ = 80 ◦ C, and
TJM = 140 ◦ C;
SMET et al.: AGEING AND FAILURE MODES OF IGBT MODULES IN HIGH-TEMPERATURE POWER CYCLING 4935

TABLE I
R ESULTS OF T ESTS IN P ROTOCOL 1

TABLE II
R ESULTS OF T ESTS IN P ROTOCOL 2

3) Protocol 2-3: Treference = 60 ◦ C, ΔTJ = 100 ◦ C, and
TJM = 160 ◦ C.
The main results are given in Table II.
D. General Analysis
The experimental studies on reliability are difficult and time
consuming. In the test series described in this paper, the test
duration varied from a few hundred hours to 5000 h for the
least stress-inducing protocol. One unique aspect of this paper
is the high number of tested samples (19) with respect to the
system tests required by such power modules. This makes it
possible to elaborate a broader analysis on temperature effects,
while limiting the influence of singular results.
This section will emphasize the main ageing mechanisms
observed with respect to protocol stresses. From this point on,
it must be added that VCEo was the only indicator that varied
significantly during the tests. No significant variation on VGSTH
or on RTH was observed. For this reason, only the parameter
VCEo is evoked in the following sections.
1) DC–PWM Differences: One of the aims in this paper was
to compare the results given by a test bench operating under dc
conditions (the most commonly used) and a more original and
realistic test bench (PWM).
First, balancing the current between the module’s three legs
on the dc test bench cannot be very accurate, and the electrical
stress is not strictly identical. On the PWM test bench, the
switched currents in the device are set identically by the load.
A second difference concerns electrical stress. To generate
the thermal fluxes needed by the protocols, from 700 to 1000 W,
the rms current per chip must be higher and adjusted on the
dc test bench (see Table III) due to the absence of switching

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4936 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 10, OCTOBER 2011

TABLE III
E LECTRICAL S TRESSES AND L OSSES IN IGBT AND D IODES

Fig. 5. Example of simulated spatial temperature distributions. (a) DC mode. (b) PWM mode.

loss. In the PWM test bench, the rms current per chip is fixed
(60 A), and the thermal flux is adjusted by the switching loss
that depends on the switching frequency value.
Third, spatial temperature distribution is not identical due to
the fact that the diodes are not used in the dc mode and the
central DBC is not used in the PWM mode. Fig. 5 shows the
temperature cartographies resulting from 3-D FE simulation
performed in conditions close to those of protocol 1-2. They
are given for the maximal temperature reached on the thermal
cycle. In both cases, the same average temperatures on each
chip (mentioned near the chips in Fig. 5) cannot be imposed
because of the module and DBC asymmetry. In addition, the
difference between the two modes is significant, and the respect
of strictly similar conditions cannot be achieved. In the PWM
mode, the average temperature dispersion is low due to the use
of two separated DBCs and to the best repartition of heat sinks
(two IGBTs and two diodes). In the dc mode, the three DBCs
are thermally unbalanced and cannot be ageing identically. In
that case, the temperature fixed in tests according to protocol
definition is the average temperature of the six chips, wherein
the temperature of the central DBC is higher.
Unfortunately, both methods of junction temperature mea-
surement contribute to amplifying the previous problem. In
the PWM test, the local measured temperature is close to the
maximal temperature of the chips (even if the asymmetry of
DBC shifts the hot spot toward the DBC center). In the dc test,
the measured temperature given by the indirect method is the
average temperature of the chip. For the same reference value
in both cases, with this condition being chosen in the present
tests, the average temperature is higher in the dc mode than
in the PWM mode. A test carried out under dc conditions,
on a sample equipped with the two measurement systems, has

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SMET et al.: AGEING AND FAILURE MODES OF IGBT MODULES IN HIGH-TEMPERATURE POWER CYCLING 4937

shown a difference of a few degrees for a maximal temperature

of 160 ◦ C. Thus, the lifetime dispersion observed in protocol
1-1 probably results from the combination of two facts: a higher
rms current in the connections and a higher average temperature
in the dc tests.
The results are quite similar for both tests in protocol 1-2,
with the average lifetime remaining lower in the dc test. There
is a lower dispersion of the results that can be explained by
greater test harshness and lower lifetime values.
One last difference concerns the changing behavior of mod-
ules in the previous protocol. In the dc mode, the tests were
stopped because of a progressive increase in the junction tem-
perature (unexplained for the moment). In the PWM mode, it is
mainly failure that leads the test benches to stop (local fusion
of the chip, see Section V-D3). In both cases, no changes in the
indicators were detected previously.
To summarize, the two methods do not yield strictly identical
results. This paper emphasizes the nonrepresentative test condi-
tions of the dc mode because there are no switching operations
and no high voltage applied to the chips. For a given device, the
Fig. 6. Examples of bonding damages. (a) Metallurgic damage (DC5).
rms values for currents have to be significantly higher than the (b) Heel crack (PWM7). (c) Fracture (PWM1). (d) Liftoff (PWM2).
standard values used in applications.
With the diodes not being used, temperature repartition on
the DBC is not realistic. Lastly, it is not possible to reproduce
real failure situations as in the PWM mode (see Section V-D3).
The counterpart is the simplicity of the electrical element and
the relative facility to collect parameter measurements. These
latter points constitute a significant advantage for testing very
high power modules (a few kilovolts and 1000 A).
Conversely, the PWM mode places devices in realistic con-
ditions, but it makes parameter measurement more challenging.
The online measurement of VCEo should be of primary interest,
but its implementation is very delicate and was not included in
the scope of this paper. In addition, this PWM method cannot
be applied easily to very high power modules.
Considering the more realistic test conditions and the possi-
bility to achieve controlled failure situations, the complemen-
tary tests of the second series were carried out with the PWM
test bench.
2) Connections—Metallization-Acceleration Factor: Con-
versely to the results usually provided by power cycling in long-
term cycle operations, the ageing modes here mainly concern
Fig. 7. Examples of bonding damage cartographies.
the connections (wire bonds) and metallization, while the DBC
and solders are lightly damaged by the hardest cycles.
The following damage modes were observed on the wire In this latter case, metallurgical damage represents the main
bonds (see Fig. 6): damage, and failure frequently occurs before the development
of other ageing modes.
1) heel crack and fractures (mechanical constraints in the
The less stress-inducing modes generate cracks, fractures,
wires and fatigue phenomenon due to the deformation
and liftoff. Due to lower temperature variations, a progressive
related to temperature swings);
degradation of the connections is observed, with the device
2) wire bond liftoff (mechanical stress on Al–Si joints due
remaining functional. This can be observed on the damage
to the difference in the thermal expansion coefficient
cartographies of Fig. 7. PWM2 and PWM4 are samples of the
between Al and Si);
protocols 1-1 and 1-2, respectively.
3) metallurgic damage due to the thermomechanical stress
The emitter metallization is the other area suffering from
on aluminum resulting in part from the difference in the
degradation. Metallurgical damage was observed on almost all
thermal expansion coefficient between Al and Si.
the devices, regardless of the protocol (see Fig. 8). Neverthe-
The previous order gives the predominant mode appearing in less, the average area concerned by this mechanism in a given
the different protocols from the least to the most severe stress. chip increases with the amplitude of the thermal cycle.

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4938 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 10, OCTOBER 2011

Fig. 8. Examples of emitter metallization damages. (a) Initial state.

(b) Damage beginning. (c) Protocol 1-1—PWM2. (d) Protocol 2-3—PWM12.

These results first point out the critical feature that consti-
tutes connection ageing and, then, the similar ageing behavior
observed in the different protocols. Therefore, the hardest pro-
tocols (1-2 or 2-3) can be used to perform accelerated tests,
in the considered range of thermal swings. A generalization to
lower swing conditions cannot be made without experimental
results. Unfortunately, such tests would most likely require
several million cycles.
3) Chip Destruction: The PWM test bench has the capabil-
ity to immediately stop power injection in the case of a chip
failure (see Section IV-B). This functionality has frequently
operated in the protocols 1-2 and 2-3 for which chip failure
without any previous evolution of the indicators is the most
common occurrence. In the other cases, VCEo is a good indi-
cator for bond wire ageing. To illustrate this fact, Fig. 9 shows
the evolutions of VCEo during the test for three devices.
Fig. 9(a) corresponds to a device tested using high-
temperature protocol 1-2 and immediately stopped after failure.
No evolution of VCEo (as for the other indicators) can be
observed. The device in Fig. 9(b) was submitted to the inter- Fig. 9. VCEo evolution in protocols 1-1, 1-2, and 2-2. (a) Protocol 1-2.
(b) Protocol 2-2. (c) Protocol 1-1.
mediate protocol 2-2. A strong increase of VCEo was detected,
and the test bench stopped while the device was still functional.
Lastly, in the case of the less stress-inducing protocol 1-1, is representative of the mode that should be generated without
a progressive increase of VCEo was measured and is due to the short-circuit protection.
successive fractures or liftoff of the wire bonds. The destructive mode, without detecting indicator evolution,
Despite the occurrence of failure, ageing effects can be was not expected when the testing began but is highly interest-
analyzed correctly because the fault consequence on the con- ing. First, these results define an objective lifetime. They can
cerned chip is limited by short-circuit protection. The views of also give information on the mechanisms that lead to failure
Fig. 10(a)–(c) show examples of the resulting damage, which is and the origin of this failure. This information is essential for
localized. the development of fault-tolerant converters.
The result of Fig. 10(d) was obtained in a particular case: In the present case, a rigorous identification of the failure
The test bench stopped normally after a first failure (protection scenario should require thermal simulation and metallurgic
triggering) but was then restarted by mistake. Fault propagation analysis. The authors are currently working on the understand-
and the quasi-destruction of the chip are the consequences. This ing and theoretical analysis of these failures. Nevertheless, as

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SMET et al.: AGEING AND FAILURE MODES OF IGBT MODULES IN HIGH-TEMPERATURE POWER CYCLING
Fig. 10. Examples of chip destruction. (a) PWM3. (b) PWM12. (c) PWM4.
(d) Destroyed chip after test error.
Fig. 11. Fractures in solders. (a) Corner fracture of DBC-baseplate solder
in PWM2 (SAM). (b) Chip-DBC solder fracture in IGBT1—PWM2 (SEM).
(c) Chip-DBC solder in IGBT1—PWM5 (SEM).
the destroyed zones are generally localized around wire bond
heels, a realistic assumption can be formulated. As the first
bond wire contact fails, the remaining bond wires must then
conduct a higher current. As the degradation proceeds, an
increasing number of bond wire contacts fail, and the current
continues to increase in the remaining contacts until localized
overcurrent failures occur.
4) DBC and Solder Fractures: In the particular test con-
ditions of this paper, the delamination of solders is an age-
Authorized licensed use limited to: Universite du Quebec en Outaouais. Downloaded on February 14,2021 at 18:01:30 UTC from IEEE Xplore. Restrictions apply.
4939
ing mode that has been rarely encountered. Acoustic analysis
and SEM examination of cross sections carried out on aged
modules confirm that fact. Nevertheless, regarding the less
stress-inducing protocol (1-1), the initiation of fracture in
solders was observed. Fig. 11(a) shows some weak fractures
(acoustic analysis) in the corners of the DBC-baseplate solder
for sample PWM2 (520 kC). Fig. 11(b) shows fractures in chip-
DBC solders revealed by the SEM examination of the section.
Conversely, the SEM does not reveal any fracture for the same
section realized on a sample aged under protocol 1-2 (failure at
60 kC).
As it has already been mentioned, no significant variation
in RTH was measured during ageing tests on the concerned
samples, despite the previously described damage. They are
localized on the border of the DBC-baseplate solder and there-
fore do not really affect the heat transfer. Very accurate RTH
measurements would be necessary to reveal such degradation.
An intermediate conclusion can be drawn on the modules
tested in this paper: In the competition between ageing modes,
wire bond degradation is the predominant mechanism in the
case of high thermal stress. In less stress-inducing protocols,
the different modes can occur simultaneously.
VI. C ONCLUSION
The study presented in this paper is a contribution to the
understanding and the quantification of ageing mechanisms
observed in IGBT modules stressed under power-cycling con-
ditions. From the test of 19 samples in five different protocols,
five families of results were obtained, reported, and analyzed.
They show the high sensitivity of wire bonds and metallization
to high-temperature power cycling (maximal temperature up
to 170 ◦ C). Gradual occurrences of three ageing modes, heel
fractures, liftoff, and metallurgical damage were observed in all
protocols. This is the main cause of module degradation and,
in the severest protocol, leads to failures whose propagation is
avoided by test bench protections. As ageing mechanisms are
similar in the different protocols, the possibility to use high-
temperature cycles to accelerate test conditions was confirmed
in the 60 ◦ C–100 ◦ C temperature swing range.
In addition, this paper demonstrates the interest of test
benches close to the real converter topology (PWM). Devices
are placed in realistic electrical conditions, with a heat flux
and temperature distribution that cannot be reproduced with
the dc test bench (no switching loss and no loss in diodes).
The thermal parameter adjustment is easier, as the current
levels in switches are more representative and failure modes
can be attempted under controlled conditions. The counterpart
is the difficulty in carrying out online measurements of ageing
parameters.
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Vanessa Smet graduated from the Ecole Normale
Superieure de Cachan, Cachan, France. She received
the B.S. degree in applied physics from Paris XI
University, Orsay Cedex, France, in 2004, and the
M.S. degree in electrical engineering and the Ph.D.
degree from the Montpellier University of Science
(Institut d’Electronique du Sud laboratory, Unité
Mixte de Recherche Centre National de la Recherche
Scientifique 5214), Montpellier, France, in 2007 and
2010, respectively.
She is currently a Postdoctoral Researcher with the
Tyndall National Institute, University College Cork, Cork, Ireland. Her research
interests include reliability of power semiconductor device, high-temperature
packaging, and thermomechanical modeling.
Francois Forest (M’06) received the B.S. degree
in electrical engineering from the Ecole Normale
Superieure de Cachan, Cachan Cedex, France, in
1982, and the Ph.D. degree from the University of
Paris 6, Paris, France, in 1985.
From 1989 to 1999, he was a Professor with the
Electrical Engineering Department, Ecole Normale
Supérieure de Cachan. Since 1999, he has been a
Professor with the Montpellier University of Sci-
ence, Montpellier, France. His research activities (In-
stitut d’Electronique du Sud laboratory, Unité Mixte
de Recherche Centre National de la Recherche Scientifique 5214) concern es-
sentially parallel or series multilevel converters from low-power dc-to-dc stages
to high-power pulsewidth-modulation inverters, power devices and converter
reliability, and passive component modeling.
Jean-Jacques Huselstein received the B.S. degree
in electrical engineering from the Ecole Normale
Superieure de Cachan, Cachan Cedex, France, in
1988, and the Ph.D. degree from the Montpellier
University of Sciences, Montpellier, France, in 1993.
He is currently an Associate Professor with the
Montpellier University of Sciences. His research ac-
tivities (Institut d’Electronique du Sud laboratory,
Unité Mixte de Recherche Centre National de la
Recherche Scientifique 5214) cover insulated-gate
bipolar transistor converter reliability, direct ac–ac
converters, and low-power direct-drive wind power génération.
SMET et al.: AGEING AND FAILURE MODES OF IGBT MODULES IN HIGH-TEMPERATURE POWER CYCLING
Frédéric Richardeau received the M.Sc. and Agre-
gation degrees in electrical engineering from the
Ecole Normale Supérieure de Cachan, Cachan
Cedex, France, in 1991 and 1992, respectively, and
the Ph.D. degree in power electronics from the In-
stitut National Polytechnique de Toulouse (INPT),
Toulouse, France, in 1996.
He was a Lecturer and Researcher Assistant with
the INPT from 1996 to 1997. He joined the Lab-
oratoire d’Electrotechnique et d’Electronique In-
dustrielle, Toulouse, as a Centre National de la
Recherche Scientifique (CNRS) Reseacher and a part-time Lecturer at the
INPT, in 1997. He is currently the Head of the Static Converter Group with
the Laboratoire Plasma et Conversion d’Energie at the Toulouse University and
CNRS. His research interests include reliability and diagnosis of power devices,
safety design and management, fault-tolerant converter, and multicell converter.
Zoubir Khatir received the Dipl.Ing. degree in the
physics of solids from the Institut National des Sci-
ences Appliquées de Toulouse, Toulouse, France, in
1984, and the Ph.D. degree in electronics prepared
in the Laboratoire d’Analyse et d’Architecture des
Systèmes-Centre National de la Recherche Scien-
tifique laboratory, Toulouse, in 1988.
Since 1988, he has been with the Laboratory of
New Technology, French Institute of Science and
Technology for Transport, Development and Net-
works, where he was in charge for high-power semi-
conductor device modeling and computer-aided design tool development. His
actual research interests include the reliability in the high-temperature environ-
ment of high-power electronics in the field of transport applications.
Authorized licensed use limited to: Universite du Quebec en Outaouais. Downloaded on February 14,2021 at 18:01:30 UTC from IEEE Xplore. Restrictions apply.
4941
Stéphane Lefebvre received the Ph.D. degree in
electrical engineering from the Ecole Normale
Supérieure de Cachan, Cachan Cedex, France,
in 1994.
He is currently a Professor with the Conserva-
toire National des Arts et Métiers, Paris, France,
where he teaches power electronics. His research
interests (Systèmes et Applications des Technologies
de l’Information et de l’Energie Laboratory, Unité
Mixte de Recherche Centre National de la Recherche
Scientifique 8029) include the test and the modeling
of power semiconductor devices in hard working conditions and at high
operating temperature.
Mounira Berkani received the Ph.D. degree in
electrical engineering from the Ecole Normale
Supérieure de Cachan, Cachan, France, in 2008.
She is currently an Associate Professor with the
University of Paris XII, Paris, France. Her research
interests (Systèmes et Applications des Technologies
de l’Information et de l’Energie Laboratory, Unité
Mixte de Recherche Centre National de la Recherche
Scientifique 8029) include the behavior and reliabil-
ity of power semiconductor devices under extreme
operating conditions and high temperature.