The Timepix3 chip

C.Brezinaa, Y.Fua, M.De Gasparib, V.Gromovc, X.Llopartb*,

T.Poikelab, F.Zapponc and A.Krutha

On behalf of the Medipix3 collaboration

a Bonn university
b CERN
c NIKHEF
 • Introduction
– Timepix3 Motivation
– Pixel operation

• Measurements
– Timepix3 Readout System
– PC and iTOT mode:
• Single Pixel gain and ENC
Outline

• Full chip ENC

• Equalization
– TOA and TOT:
• TOT linearity
• Timewalk
• TOT linearity
– Results summary
– Wafer Probing
– Timepix3 TPC [Preliminary]

• Conclusions

25th February 2014 ESE Seminar – X.Llopart 2

 Hybrid Pixel Detectors Operation Modes
• In a hybrid pixel detector the energy threshold is used to eliminate noise
or low energy events → Noise-free system

• Nature of measurements after discriminator:

– Particle Counting (PC)
• Count of number of events in a fix time (Shutter)
Threshold
– Time-Over-Threshold (TOT)
• TOT charge per event
• iTOT integral of the charge over a fix time (Shutter)
– Time of Arrival (TOA)
TOT
• Measure of the arrival time (Time stamping)
– Binary (Bi) TOA

• 1 bit per event tagged with Bx

25th February 2014 ESE Seminar – X.Llopart 3

 Hybrid pixel ASICs classification
(from 2012 seminar)
Pixel Size Pixel Data Start Acquisition Trigger
Chip Name Technology Year Pixel Operation Bits/Pixel Output data port
[um] Array Type readout Type Readout
Non- 1-LVDS
Medipix2 IBM 250n 2005 55 256*256 PC 14 Full frame External
continuous
No Imaging
@ 180 Mbps
32-bit CMOS DDR
EIGER UMC 250nm 2010 75 256*256 PC 4, 8 or 12 Full frame External Continuous No
@ 200 Mbps
1,2,4 or 8-LVDS
Medipix3RX IBM 130n 2012 55 256*256 PC 1,6,12 or 24 Full frame External Continuous No
@ 250 Mbps
Non- 32-bit CMOS
Timepix IBM 250n 2006 55 256*256 PC, TOT or TOA 14 Full frame External No
continuous @ 100 Mbps
384*384 TOA and TOT 1,2,4 or 8-LVDS
SmallPix IBM 130n 2014 ? 35-40 24-32 0-compressed External Continuous No
512*512 PC and iTOT @ 250 Mbps
Non- 1 or 2-LVDS
ClicPix_demo TSMC 65nm 2012 25 64*64 TOT and TOA 9 0-compressed External
Continuous
No HEP Low Rate
@ 640 Mbps
32-GTL
Alice1LHCb IBM 250n 2001 50*425 256*32 TOA and Binary 2 FIFO of 8 bit BCO 0-compressed External Continuous Yes
@ 40 Mbps
6-8 bit analog
PSI46 (CMS) IBM 250n 2005 100*150 52*80 Analog ? 0-suppresed External Continuous Yes
@ 40 MHz
8-bit TOA +
address 1-LVDS
FEI3 (ATLAS) IBM 250n 2006 50 *400 160*18 TOA and TOT 0-suppresed External Continuous Yes
EOC event @ 40 Mbps
Buffering
1-LVDS
FEI4 (ATLAS) IBM 130n 2011 50*250 336*80 TOA and TOT ? 0-suppresed External Continuous Yes HEP Triggered
@ 320 Mbps
Data 4 CML
TDCpix (NA62) IBM 130n 2012 300 45*40 TOA and TOT 48 0-suppresed Continuous No
driven @ 3.2 Gbps
Data 1-LVDS
ToPIX (PANDA) IBM 130n 2012 100 116*110 TOA and TOT 48 0-suppresed Continuous No
driven @ 312.4 Mbps
PC and iTOT
Data 1 to 8-SLVDS DDR
Timepix3 IBM 130n 2013 55 256*256 TOA and TOT 44 0-suppresed Continuous No
driven @ 640 Mbps
TOA
PC Data 4 CML
VeloPix IBM 130n 2014? 55 256*256
TOA and TOT
30 0-suppresed
driven
Continuous HEP Trigger-less
No
@ 5.2 Gbps
25th February 2014 ESE Seminar – X.Llopart Semi-
4
1-CMOS
Dosepix IBM 130n 2010 220 16*16 TOT 256 Full frame External No Dosimetry
Continuous @ 10 Mbps
 Timepix (2006)
• IBM 250nm 6-metals 14.111 mm
• Operation modes:
– Particle arrival time (TOA) 55 µm
– Charge information (iTOT)
– Event counting (PC)
• Frame based readout

Previous Pixel

Ref_Clkb Clk_Read

16.12 mm
Mux

4 bits thr Adj

Mask
Mux
Input CSA
Disc 14 bits
THR Shutter Timepix Shift
Shutter_int
Ctest Synchronization Register
P0 Logic
Conf
Testbit Polarity P1
8-bits PCR

Test Input
OvControl
Ref_Clk Clk_Read
Next Pixel
Analog Digital

Timepix Pixel Schematic Timepix picture

25th February 2014 ESE Seminar – X.Llopart 5
 Timepix chip architecture
Main Specs:
• 256x256 55µm square pixels
• Analog Power → 440mW

14080 m (pixel array)

3584-bit Pixel Column-255
3584-bit Pixel Column-1
3584-bit Pixel Column-0

• Bits stored in pixel → 14

• Serial readout (@100Mbps) → 9.17 ms
16120 m

• Parallel readout (@100Mbps) → 287 µs

• Full custom design
• > 36M Transistors

256-bit Fast Shift Register

Bandgap + 13 DACs
LVDS IO LVDS
In Logic 32-bit CMOS Output Out

14111 m

25th February 2014 ESE Seminar – X.Llopart 6

 Timepix
• The Timepix (2006) has proven to be a versatile chip with a large
range of applications:
– X-ray radiography, X-ray polarimetry, low energy electron microscopy
– Radiation and beam monitors, dosimetry
– 3D gas detectors, neutrons, fission products
– Gas detector, Compton camera, gamma polarization camera, fast
neutron camera, ion/MIP telescope, nuclear fission, astrophysics
– Imaging in neutron activation analysis, gamma polarization imaging
based on Compton effect
– Neutrino physics
– Main Linear Collider application: pixelated TPC readout

• > 350 original paper citations

25th February 2014 ESE Seminar – X.Llopart 7

 L. Pinsky

25th February 2014 ESE Seminar – X.Llopart 8

 Timepix3 motivation
• Main driving requirements:
1. Simultaneous TIME (TOA) and CHARGE (TOT) information per pixel
2. Minimize dead time → Event-by-event readout and 0-supressed
3. Monotonic TOT in both detection polarities
4. Improve time measurements resolution

• Experience gained in the design of the Medipix3 chip (2009):

– Technology (130nm CMOS)
– Building blocks recycled (CERN’s HD Standard Cell library, DACs, …)

• Designed by CERN, Nikhef and Bonn University with the support of

the Medipix3 Collaboration

25th February 2014 ESE Seminar – X.Llopart 9

 CERN 130nm HD Library
6 µm
• Physical specs:
– “Mainly” Low power transistors
– Row Height is fixed to 2.4 µm
– Well Tap library

4.8 µm
• Maximum frequency < ~700 MHz (@1.5V)
• Encounter Library Characterizer (ELC) used:
– Full Synopsis library: Minimum DFF available
• lib, ecsm, ecsm_si and ccs in default CERN Standard
• delays, static and dynamic power
• Corners:
Cell 130nm library
– 1.2V : -55C FF, 25C TT and 125C SS
– 1.5V : -55C FF, 25C TT and 125C SS
– Verilog library 5.6 µm
3.8 µm
– LEF files
– HTML documentation
• ~50 cells are available in the library µm
1.8µm
MinimumDFF DFFavailable
In the
2.4
Minimum
• Used in Medipix3RX in acustom made Standard
commercial High
density 130nmlibrary
Cell 65nm library
x2
x4smaller
smaller!!!
!!!
25th February 2014 ESE Seminar – X.Llopart 10
 CERN 130nm HD Special cells (I)
• Cells with “non-standard” functional behaviour can
be integrated

2.4 µm

3.6 µm 2.8 µm

VOTERI_B_XL NOR5_A_XL
(VeloPix) (Medipix3RX)

25th February 2014 ESE Seminar – X.Llopart 11

 CERN 130nm HD Special cells (II)
• Cells with non-standard row height are also possible to
integrate:
– Row height multiple (2.4 µm)
– Pitch length multiple (0.4 µm)

9.6 µm

4.8 µm
18 µm 14.8 µm

640MHz VCO CLK_Q_RVT_XL

(Timepix3) (Timepix3)
25th February 2014 ESE Seminar – X.Llopart 12
 Timepix vs Timepix3
Timepix (2006) Timepix3 (2013)
Pixel arrangement 256 x 256
Pixel size 55 x 55 µm²
Technology 250nm CMOS - 6Metals 130nm CMOS - 8Metals
1) Charge (iTOT) 1) Time (TOA) AND Charge (TOT)
Acquisition modes 2) Time (TOA) 2) Time (TOA)
3) Event counting (PC) 3) Event counting (PC) AND integral charge (iTOT)
1) Data driven (DD)
Readout Type 1) Full-Frame
2) Frame (FB)
Zero suppressed readout NO YES

Dead time per pixel > 300µs > 475ns ~600x

readout time of one frame Pulse measurement time + packet transfer time

Minimum timing resolution 10ns 1.562ns 6.4x

On-chip Power pulsing (PP) NO YES
Minimum detectable charge ~750e- >500e- 1.5x
1 LVDS ≤200Mbps
Output bandwidth
32 CMOS ≤3.2Gbps
1 to 8 SLVS @640Mbps DDR ≤5.2Gbps 1.6x

25th February 2014 ESE Seminar – X.Llopart 13

 Swiss technology comparison

Timepix (2006) Timepix3 (2013)

25th February 2014 ESE Seminar – X.Llopart 14

 Trigger-less frame based
and zero-supressed readout

Shutter Acquisition time

Qin

DataOut 48bit 48bit 48bit 48bit 48bit

0xA Address[16-bit] Data[28-bits] 0x71 0xA0 ChipID [32b]

Data Packet (48 bits) End of Command (48 bits)

• Maximum frame rate (all pixels hit): 1300 fps @5.12Gbps

25th February 2014 ESE Seminar – X.Llopart 15

 Maximum frame rate [fps]
Frame Based Readout
10000 Worst case: all pixels readout
48bit/pixel and 8b10b → 3.932 Mbits/frame (x2.5 Mpix3)

1000 ~1300 fps

[fps]

100

40Mbps
80Mbps
10
160Mbps
320Mbps
640Mbps
1
1 2 3 4 5 6 7 8
number of active links [8b10b ON]

25th February 2014 ESE Seminar – X.Llopart 16

 Trigger-less event-by-event data driven
and zero-supressed readout

Shutter Acquisition time

Qin

DataOut 48bit 48bit 48bit 48bit 48bit 48bit

0xB Address[16-bit] Data[28-bits] 0x71 0xB0 ChipID [32b]

Data Packet (48 bits) End of Command (48 bits)

• Achievable count rate:

– uniformly distributed events → ~40 Mhits/s/cm2 @5.12Gbps
• Full matrix readout: ~800 µs @5.12Gbps

25th February 2014 ESE Seminar – X.Llopart 17

 Maximum Event Readout
Data Driven Readout
85.3 Mhits/s
90
80
70
MHitsProccessed/s

60
50 Sys Clock
20MHz
40 40MHz
30 60MHz
80MHz
20 >86MHz
10
0
1 2 3 4 5 6 7 8
number of active links @640Mbps and 8b10b ON

25th February 2014 ESE Seminar – X.Llopart 18

 Pixel Operation in TOA & TOT [DD]
Tpeak < 25ns

Preamp Out

Disc Out

Pixel Readout Starts

Clk (40MHz) (475ns→ 19 clock cycles)

Global TOA (14-bit) 16382 16383 16384 0 1 2 3 4

FTOA (4 bits)=7
VCO Clk (640MHz)

TOA (14-bit) X 16383 TOA (14 bits)=16383

TOT (10 bits) =4

TOT Clk (40MHz)
25th February 2014 ESE Seminar – X.Llopart 19
 Pixel Operation in TOA only [DD]
Tpeak < 25ns

Preamp Out

Disc Out

Pixel Readout Starts

Clk (40MHz) (475ns→ 19 clock cycles)

Global TOA (14-bit) 16382 16383 16384 0 1 2 3 4

FTOA (4 bits)=7
VCO Clk (640MHz)

TOA (14-bit) X 16383 TOA (14 bits)=16383

25th February 2014 ESE Seminar – X.Llopart 20

 Pixel Operation in PC and iTOT [FB]

Preamp Out

Disc Out
Pixel readout
can start in
Clk (40MHz) Data Driven or
Frame based

Shutter

PC (10-bit) 0 1 2 3 PC (14 bits)=3

iTOT (14-bit) 0 1 2 3 4 5 iTOT (14 bits)=5

25th February 2014 ESE Seminar – X.Llopart 21

 T. Poikela

Timepix3 Pixel Schematic

1 pixel Common for 8 pixels

Front-end (Analog) Front-end (Digital) Super pixel (Digital)

Leakage
Current TOA & TOT TOA (14-bit) TOT (10-bit) FTOA (4-bit) Token Deserializer
compensation arbitration
TOA TOA (14-bit) FTOA (4-bit) [1x31]
Input 3fF PC & iTOT iTOT (14-bit) PC (10-bit)

31-bits
pad
Preamp Counters
Synchronizer
& & Super pixel
TestBit MaskBit Clock gating
Latches
~50mV/ke- FIFO
3fF
4-bit Local
640MHz
VCO [2x31]
Threshold
@640MHz

14-bits

handshake
37-bits
TpA TpB Global threshold clock Time stamp OP Mode Control Data out clock
(LSB= ~10e-) (40MHz) voltage (40MHz)
to EOC

25th February 2014 ESE Seminar – X.Llopart 22

 Timepix3 Pixel Operation
Valid
Superpixel
Acquisition Modes VCO
Measurement type On-pixel counter depth Data
bits
TOA 14-bit (gray counter)
ON TOT 10-bit (LFSR with overflow)
Time (TOA) AND Charge (TOT) Fast ToA 4-bit (binary counter with overflow)
28
TOA 14-bit (gray counter)
OFF TOT 10-bit (LFSR with overflow)
Event Counter 4-bit (LFSR with overflow)
TOA 14-bit (gray counter)
ON
Fast ToA 4-bit (binary counter with overflow)
Time (TOA) TOA 14-bit (gray counter)
18
OFF
Event Counter 4-bit (LFSR with overflow)
iTOT 14-bit (LFSR)
ON
Event counter 10-bit (LFSR with overflow)
Event counting (PC) AND integral charge (iTOT) iTOT 14-bit (LFSR) 28
OFF Event counter 10-bit (LFSR with overflow)
Event Counter 4-bit (LFSR with overflow)

• 4 Look-up-tables (LUT) needed to decode pixel data:

– 14-bit gray counter
– 14-bit LFSR
– 10-bit LFSR
– 4-bit LFSR

25th February 2014 ESE Seminar – X.Llopart 23

 T. Poikela

Asynchronous column data transfer

• 2-phase handshake protocol
using single rail coding
• Globally-asynchronous
locally-synchronous column
readout protocol (GALS)

CORNER

SS TT FF
1.4V 1.5V 1.6V
125C 25C -55C
[MHits] [MHits] [MHits]

SP 0 only 0.45 0.45 0.45

SP 63 only 0.41 0.45 0.465

All SPs 1.36 1.5 1.6

Full
174 192 205
Matrix

25th February 2014 ESE Seminar – X.Llopart 24

 Pixel Matrix Clock distribution
• Nominal clock frequency is 40MHz (up to 80MHz)
• Synchronous clock distribution in the pixel matrix required for TOA time
stamping:
– Simulated bottom to top skew is (1.05ns, 1.45ns and 2ns) in (FF, TT and SS)
corners
• Minimize peak digital current consumption:
– Configurable double-column pixel matrix clock phase shift:
– In pixel clock is gated if pixel is not hit

# Columns with Peak current

Number of phases phase delay
same clk phase clk distribution only
1 128 25ns 1.075 A
2 64 12.5ns 537.6 mA
4 32 6.25ns 268.8 mA
8 16 3.125ns 134.4 mA
16 8 1.5625ns 67.2 mA

25th February 2014 ESE Seminar – X.Llopart 25

 SuperPixel[63]

SuperPixel[63]

SuperPixel[63]
14080 µm

SuperPixel[0]

SuperPixel[0]

SuperPixel[0]
Timepix3 Floorplan

Pixel Matrix
OscB[0] OscB[2] OscB[63]

PPul[128]
PPul[127]
EoC[126]

EoC[127]
PPul[2]
PPul[0]

PPul[1]
EoC[0]

EoC[1]
OscBias640 Buffered
Bias Voltage

Bus Controller
1260 µm

Pixel Matrix 48 bit bus

Data controller

Analog Periphery Control Logic

Slow Control

Command
Decoder
Reset

40,80,160 or 320
&

PLL
ClkOut

BandGap E-Fuses
Clk40

x 2,4,8 Output Block

Global DACs 32 bits

Periphery
and 16

Reset DataIn ClkIn40 DataOut[7:0] DACOut

870 µm

EnableIn PLLOut ClkOutData ExtDAC VDDA33

T0_Sync
Shutter VDDA/GNDA

IOPads
EnablePowerPulsing VDDPLL/GNDPLL
25th February 2014 ExtTPulse
ESE Seminar – X.Llopart VDD/GND
26
SLVS_TERM
 Timepix3 Active Periphery
64 VCO control
VCO Buffer [0] VCO Buffer[2] voltage buffers VCO Buffer[63]

Buffered

EoC[126]

EoC[127]
EoC[2]
EoC[0]

EoC[1]

bias voltages

128 End of
VCO bias
Column logic
1260 µm

640MHz
Bus
Controller

Periphery bus Analog Periphery Control Logic

Slow Control (3.84Gbps)
&
Command 8x Serializer 1 BandGap E-Fuses
PLL
Clk40

Decoder 8b10b DDR 18 Global DACs 32 bits

Data output DDR 8b10b encoding

(1 to 8 links) Up to 8x640 Mbps (5.12 Gbps)

25th February 2014 ESE Seminar – X.Llopart 27

 Timepix3 IO
Timepix3 Differential I/O
VID(mV) VICM (V) VOD (mV) VOCM (V)
Name Type
Min Max Min Max Min Max Min Max
DataIn I SLVS/LVDS 80 1500 0.1 1.3 - - - -
EnableIn I SLVS/LVDS 80 1500 0.1 1.3 - - - -
Reset I SLVS/LVDS 80 1500 0.1 1.3 - - - -
T0_Sync I SLVS/LVDS 80 1500 0.1 1.3 - - - -
Shutter I SLVS/LVDS 80 1500 0.1 1.3 - - - -

EnablePowerPulsing I SLVS/LVDS 80 1500 0.1 1.3 - - - -

ExtTPulse I SLVS/LVDS 80 1500 0.1 1.3 - - - -
ClkIn40 I SLVS/LVDS 80 1500 0.1 1.3 - - - -
ClkInRefPLL I SLVS/LVDS 80 1500 0.1 1.3 - - - -
PLLOut O SLVS - - - - 70 380 0.19 0.25
DataOut[7:0] O SLVS - - - - 70 380 0.19 0.25
ClkOut O SLVS - - - - 70 380 0.19 0.25
Timepix3 CMOS I/O
VIL(V) VIH (V)
Name Type
Min Max Min Max
SLVS_TERM I CMOS -0.2 0.5 1 1.6
Timepix3 Analog I/O
VI(V) VO (V)
Name Type
Min Max Min Max
DACOut O Analog - - GNDA VDDA (1.5)
ExtDAC I Analog -0.2 1.6 - -

25th February 2014 ESE Seminar – X.Llopart 28

 Periphery Command List
Periphery Operation Header [8 bits] Header DataIN [16 bits] DataOut [40 bits]
SenseDACsel I 0x00 {DAC Code}[4:0]
ExtDACsel I 0x01 {DAC Code}[4:0]
SetDAC_Code I 0x02 {DAC Value}[13:5] {DAC Code}[4:0]
ReadDAC_code IO 0x03 {DAC Code} [4:0] {DAC Value}[13:5] {DAC Code}[4:0]
EFuse_Burn I 0x08 {FuseProgramConfig}[10:0]}
AnalogPeriphery EFuse_Read I 0x09 {8’b0} [39:32]{ChipID}[31:0]
EfuseRead_BurnConfig O 0x0A {FuseProgramConfig}[20:0]}
TP_Period I 0x0C {TPphase} [11:8]{ TPperiod }[7:0]
TP_PulseNumber I 0x0D {TPnumber }[15:0]
TPConfig_Read O 0x0E {TPphase, TPperiod, TPnumber}[27:0]
TP_internalfinished O 0x0F 8’b{0000_1111}{ChipID}[31:0]
OutBlockConfig I 0x10 {OutputBlockConfig}[12:0]
OutputBlockConfig OutBlockConfig_Read_en O 0x11 {27’b0} [39:13] {OutputBlockConfig}[12:0]
PLLConfig I 0x20 {PLLConfig}[7:0]
PLLConfig PLLConfig_Read_en O 0x21 {32’b0} [39:8] {PLLConfig}[7:0]
GeneralConfig I 0x30 {GeneralConfig}[11:0]
GeneralConfig_Read_en O 0x31 28’b0} [39:12] {GeneralConfig}[11:0]
SLVSConfig I 0x34 {SLVSConfig}[4:0]
GeneralConfig SLVSConfig_Read_en O 0x35 {35’b0} [39:6] {SLVSConfig}[4:0]
PowerPulsingPattern I 0x3C {PowerPulsingPattern}[7:0]
PowerPulsingConfig_Read_en O 0x3D {32’b0} [39:8] {PowerPulsingPattern}[7:0]
PowerPulsingON_finished O 0x3E 8’b{0011_1111}{ChipID}[31:0]
ResetTimer I 0x40
SetTimer_15_0 I 0x41 {SetTimer[15:0]}[15:0]
SetTimer _31_16 I 0x42 {SetTimer[31:16]} [15:0]
SetTimer _47_32 I 0x43 {SetTimer[47:32]} [15:0]
RequestTimeLow O 0x44 {8’b0} [39:32]{Timer[31:0]}[31:0]
Timer RequestTimeHigh O 0x45 {24’b0} [39:16]{Timer[47:32]}[15:0]
TimeRisingShutterLow O 0x46 {8’b0} [39:32]{TimerShutterR[31:0]}[31:0]
TimeRisingShutterHigh O 0x47 {24’b0} [39:16]{TimerShutterR[47:32]}[15:0]
TimeFallingShutterLow O 0x48 {8’b0} [39:32]{TimerShutterL[31:0]}[31:0]
TimeFallingShutterHigh O 0x49 {24’b0} [39:16]{TimerShutterL[47:32]}[15:0]
T0_Sync_Commnad O 0x4A
Acknlowledge O 0x70 {H1,H2,H3} [39:32] { ChipID} [31:0]
EndOfCommand O 0x71 {H1,H2,H3} [39:32] {ChipID} [31:0]
ControlOperation OtherChipCommand O 0x72 {8’b0} [39:32] { ChipID} [31:0]
WrongCommand O 0x73 {H1,H2,H3} [39:32] {ChipID} [31:0]

25th February 2014 ESE Seminar – X.Llopart 29

 Power pulsing strategy in Timepix3
• Analog power-pulsing:
– Preamp (3µA), DiscS1 (2µA) and DiscS2 (2µA) are the ~98% of the
analog power consumption in the pixel matrix (460mA)
– One Periphery multiplexer for the 3 biasing lines in each double
column selects between the Power-ON or Power-OFF states
– Power-ON (8-bits) and Power-OFF (4-bits) values are programmed in 2
periphery DACs for each power pulsed bias line
– Power pulsing multiplexer is selected by a sequential column to
column signal with independent adjustable turn-on and turn off times
• System clock gating:
– Clock gating is applied at the end of the analog power-off sequence
– This feature can be disabled

25th February 2014 ESE Seminar – X.Llopart 30

 Power pulsing time diagram
0.8 µs ≤ Ramp-up/down ≤ 2.56 ms @40MHz
64 bits
DataIn PowerPulsingSettings

ClockDividerPP_ON[2:0] = 000
NumberOfSimultaneousColumnsPP_ON[5:3] = 100 0.8 µs @ 40 MHz
ClockDividerPP_OFF[8:6] = 010
NumberOfSimultaneousColumnsPP_ON[11:9] = 101 6.4 µs @ 40 MHz
EnablePowerPulsingInDigitalDomain = 1

EnablePowerPulsing

AnalogPower ON (~750mW) OFF (<25mW) ON

Ramp-down Ramp-up

Clock (internal) ON OFF ON

DataOut 0h3F3F ChipID

Power Pulsing ON Finished

25th February 2014 ESE Seminar – X.Llopart 31
 ToA and ToT mode {1010 or 1011}[47:44] Address[43:28] TOA[27:14] TOT[13:4] FTOA[3:0]

Only ToA {1010 or 1011}[47:44] Address[43:28] TOA[27:14] dummy[13:4] FTOA[3:0]

Event Count and iToT {1010 or 1011}[47:44] Address[43:28] iTOT[27:14] EventCounter[13:4] dummy[3:0]
Acquisition (VCO ON)

{1010 or 1011}[47:44] Address[43:28] TOA[27:14] TOT[13:4] HitCounter[3:0]

ToA and ToT mode
Data output packet types
{1010 or 1011}[47:44] Address[43:28] TOA[27:14] dummy[13:4] HitCounter[3:0]
Only ToA
{1010 or 1011}[47:44] Address[43:28] iTOT[27:14] EventCounter[13:4] HitCounter[3:0]
Event Count and iToT
Acquisition (VCO OFF)

Stop Matrix Readout {1111 or 1110}[47:44] dummy[43:0]

or Reset Sequential
@ data readout

Pixel Configuration {1001}[47:44] Address[43:28] dummy[27:20] PCR[19:14] dummy[13:0]

CTPR Configuration {1101}[47:44] Address[43:37] Dummy[36:28] EoC[27:10] dummy[9:2] CTPR[1:0]

Pixel Matrix Configuration

Periphery Command {0}[47] {H2,H3}[46:40] DataOutPeriphery [39:0]

Periphery Configuration

Acknowledge cmd {0111_0000}[47:40] {H1,H2,H3}[39:32] ChipID[31:0]

End of cmd {0111_0001}[47:40] {H1,H2,H3}[39:32] ChipID[31:0]

Other Chip cmd {0111_0010}[47:40] {0000_0000}[39:32] ChipID[31:0]

Wrong cmd {0111_0011}[47:40] {H1,H2,H3}[39:32] ChipID[31:0]

Control Commands

25th February 2014 ESE Seminar – X.Llopart 32

 Power Consumption Data Driven
[VDD=1.5V and VDDA=1.5V]
2.2
2.1
2 Hit Processing
1.9 Idle
1.8 Periphery
1.7 Digital
1.6 Analog
1.5 <1.5 W @80MHit/s
Total
1.4
1.3
Power [W]

1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1 1 10 100 1000 10000 100000
Chip Hit Rate [Mhits/s]

25th February 2014 ESE Seminar – X.Llopart 33

 Power Consumption PC Frame-based
[VDD=1.5V and VDDA=1.5V]
2.2 Hit Processing
2.1 Idle
2 Periphery
1.9 Digital
1.8 Analog
1.7 Total
1.6
~100 KHz/pixel
1.5 Data Driven limit
1.4
Power [W]

1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1 1 10 100 1000 10000 100000
Chip Hit Rate [Mhits/s]

25th February 2014 ESE Seminar – X.Llopart 34

 14100 µm

Timepix3 Layout
Analog Front-End:
Double column: • 13x55 μm2
2x256pixels • <25% pixel area
64 super pixels IO Pad on digital area:
• Careful shielding 55 µm

Sensitive Area (14080 µm)

• Pad is ½ of Timepix

16210 µm

55 µm
VCO (FTOA):
• 9.6x20 μm2
Full Pixel Matrix: • < 0.8% SP area
256x256 pixels
128 double columns

8192 VCOs (640MHz) Super Pixel (SP):

177 Mtransistors • 2x4 pixels
• 110x220 μm2

Active Periphery
Active Periphery (1260 µm)

Pad Extenders: Pad extenders (870 µm)

Removed if TSV
25th February 2014 ESE Seminar – X.Llopart 35
 Medipix chip family
10
Transistor density per pixel [trts/µm2]

Clicpix (2013)
Timepix3 (2013)
1

Timepix (2006)
Medipix3RX (2011)

0.1
Medipix2 (1998)

Medipix1 (1998)

0.01
0 100 200 300 400 500 600 700
CMOS process [nm]

25th February 2014 ESE Seminar – X.Llopart 36

MEASUREMENTS

ESE Seminar – X.Llopart

 Timepix3 readout → SPIDR (Nikhef)
• Speedy PIxel Detector Readout (SPIDR):
– Readout system for Medipix3 and Timepix3 (single upto quads)
– 1 x 10Gbps Ethernet link IO
• First chips available since beginning of September 2013
• All measurements reported use data readout @640Mbps/link
Timepix3 Chip
10 Gbit
Ethernet

Virtex 7 FPGA VC707

Evaluation Board
25th February 2014 ESE Seminar – X.Llopart 38
 J. Alozy

Timepix3 CERN PCBs

Timepix3 CERN chip board

Timepix3 Probe card

Timepix3 translator FMC/VHDCI

25th February 2014 ESE Seminar – X.Llopart 39

 Timepix3 DACs
1.5
IB_PRE_ON
1.4
TestPulse (~50e- LSB) VPRE_NCAS
1.3 IB_IKRUM
Range : > 18ke-
1.2 VFBK
1.1 IB_DIS1_ON
1 IB_DIS2_ON

0.9 IB_PIXDAC
IB_TPBIN
0.8
[V]

IB_TPBOUT
0.7
VTP_COA
0.6 VTHR (~10e-
LSB) IB_CP_PLL
0.5 Range: 5.11 ke- VTHR_FIN
0.4 VTP_FINE
0.3 IB_PRE_OFF
0.2 VTHR_COA

0.1 IB_DIS1_OFF
IB_DIS2_OFF
0
0 64 128 192 256 320 384 448 512 PLL_VCNTRL

DAC Code [LSB]

25th February 2014 ESE Seminar – X.Llopart 40
 Pixel Data readout
• Data readout in Data Driven and Frame Based readout works as predicted
in post-layout digital simulations
Frame based Full column readout
2.1

1.9
Event rate (MHits)

1.7

1.5

1.3
TT1.5V25C
1.1 SS1.4V125C
SS1.4V125C
FF1.6V-55C
0.9 FF1.6V-55C
Measured
0.7
0 50 100 150 200 250
Event number

25th February 2014 ESE Seminar – X.Llopart 41

 250 Test Pulses in 1 pixel
[Threshold scan in PC & iTOT mode, 1 pixel]
500
Noise Floor
400 ENC ~5.7 LSBrms = ~60 e- TP=988e-
Couunts

300 TP=1542e-
TP=2004e-
200

100

0
-25 0 25 50 75 100 125 150 175 200 225 250
2500 Threshold DAC [LSB]
y = 10.4 e-/LSB
2000 R² = 0.999
Couunts

1500

1000
Assuming:
500 Ctest=3fF → Tpulse=20e-/mV
0
-25 0 25 50 75 100 125 150 175 200 225 250
Threshold DAC [LSB]

25th February 2014 ESE Seminar – X.Llopart 42

 250 Test Pulses in 256 pixels
[Threshold scan in PC & iTOT mode, pixel matrix equalized]
500
Noise Floor
TP=988e-
375
TP=1542e-
Counts

TP=2004e-
250

125

0
100 0 250 500 750 1000 1250 1500 1750 2000 2250 25002500
[e-] y = 1.0014x
80 R² = 0.9999
~3.9% rms pixel-to-
2000
pixel gain variation
60 1500

40 1000

20 500

0 0
0 250 500 750 1000 1250 1500 1750 2000 2250 2500
[e-]

25th February 2014 ESE Seminar – X.Llopart 43

 Pixel ENC
[Threshold scan over noise floor in PC & iTOT mode, 3 random pixels]

900
800
ENC = 56.2e-rms
700 ENC = 56.7e-rms
600
Counts

500
ENC = 59.8e-rms
400
300
200
100
0
-500 -400 -300 -200 -100 0 100 200 300 400 500
Threshold [e-]

25th February 2014 ESE Seminar – X.Llopart 44

 Full Matrix ENC
[Threshold scan over noise floor in PC & iTOT mode]
256
10000
µ = 59.9e-
8000 σ = 2.85e-

6000

Counts
4000
Y
9 pixels not 15 pixels
2000 responding ENC > 80e-

0
0 10 20 30 40 50 60 70 80 90 100
ENC [e-]

1 • ENC matches predictions from simulations

1 X (column number) 256

0 25 50 75 100

25th February 2014 ESE Seminar – X.Llopart 45

 Pixel-to-pixel Threshold Equalization
[Threshold scan over noise floor in PC & iTOT mode]
9000
256 256 256

8000

7000

Y Y Y
6000

5000
Counts

4000
1 1 1
1 X (column number) 256 1 X (column number) 256 1 X (column number) 256
3000
-1500 -750 0 750 1500 -1500 -750 0 750 1500 -1500 -750 0 750 1500

2000 µeq = 0e-

µ0 = -762e- σeq = 35e- µF = 762e-
1000 σ0 = 195e- σF = 197e-
Pixel DAC = 0x0 Pixel DAC = 0xF
0
-1500 -1250 -1000 -750 -500 -250 0 250 500 750 1000 1250 1500
[e-]
25th February 2014 ESE Seminar – X.Llopart 46
 Full chip minimum threshold
[Equalized pixel matrix, 16 pixels masked]

65536
32768
16384 TOA and TOT in Data Driven Readout mode
8192
4096 PC and iTOT in Sequential Readout mode
Number of active pixels

2048
1024
512
256
128
64
32
16 ~100e-
8
4 PC and iTOT ~400e- TOA and TOT (VCO ON) ~500e-
2 ENC of ~60e-rms ENC of ~77e-rms
1
0 100 200 300 400 500 600 700 800 900 1000
Threshold [e-]
25th February 2014 ESE Seminar – X.Llopart 47
 FTOA Uniformity (1.562 ns/bin)
[ Full matrix TOA & TOT mode, 1 single Test Pulse]

256 256
50000
45000
Vertical spread: 40000 σ=~0.55 LSBrms
~3ns Test pulse propagation delay (3 bins) 35000

pixel number
30000
25000
Y Y
20000
15000
10000
5000
0
Horizontal spread: -10 -5 0 5 10
16-clock phase distribution (16 bins) VCO bin [LSB]
1 1
1 X (column number) 256 1 X (column number) 256

947 951.5 956 960.5 965 [FTOA LSB] 947 951.5 956 960.5 965
RAW TOA measurement → data 18 bins Corrected TOA measurement
25th February 2014 ESE Seminar – X.Llopart 48
 Timewalk and TOT linearity
[Qin scan in TOA & TOT mode, pixel (0,0), threshold at 500e-, 64 events averaged]

80 TOT slope ~75ns/ke-

1.6
Threshold at ~500e-
70 1.4
60 1.2
50 1
time [ns]

TOA

[µs]
40 0.8
TOT
30 TOT (Linear fit) 0.6
20 Electrical Test Pulse: 0.4
• ~18 ke- maximum Test Pulse
10 • Resolution ~50e-/step 0.2
0 0
0 2.5 5 7.5 10 12.5 15 17.5 20
[ke-]
25th February 2014 ESE Seminar – X.Llopart 49
 Timewalk and TOT linearity
[Qin scan in TOA & TOT mode, pixel (0,0), threshold at 500e-, 64 events averaged]

80
Threshold at ~500e-
70

60
TOA (TOT>0)
50
TOA (TOT>7)
time [ns]

40

30

20 Timewalk < 10ns

@Threshold + 1ke-
10

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
[ke-]
25th February 2014 ESE Seminar – X.Llopart 50
 TOT spread
[Qin scan in TOA & TOT mode, diagonal pixels, threshold at 500e-]

1.6

1.4

1.2 Threshold at ~500e-

1
[µs]

0.8
TOT spread ~6.5%rms
0.6

0.4

0.2

0
0 2.5 5 7.5 10 12.5 15 17.5 20
[e-]

25th February 2014 ESE Seminar – X.Llopart 51

 Summary of measurements
Timepix (2006) Timepix3 (2013)
ENC (without sensor) 100e-rms 59.9e-rms ± 2.85e-rms
Threshold distribution 250e-rms ~195e-rms
Threshold distribution equalized 35e-rms < 35e-rms
>400e- (PC & iTOT)
Minimum Threshold (without sensor) >650e-
>500e- (TOA & TOT)
< 12µW @ 1.5V
Pixel analog power consumption 6.5µW @ 2.2V
< 0.5µW if power pulsing ON
Measured Timewalk <50ns @ 1ke- over threshold <10ns @ 1ke- over threshold
TOT spread ~5%rms ~6.5%rms

An absolute calibration using a radiation source is needed in order to confirm the

values presented

25th February 2014 ESE Seminar – X.Llopart 52

 S. Kulis

Timepix3 Wafer Probing

1. Burning e-fuses → Produces a unique ChipID
2. Power consumption (analog, digital)
3. Control voltages (Bandgap, PTAT, PLL control, …)
4. Register values after reset
5. DACs scan
6. Matrix configuration write & read
7. S-curves with analog test pulses (Event counting mode) →
gain spread
8. Noise scan (Event counting mode) → baseline & noise
spread
9. TOA & TOT measurement with digital test pulses → TOT
counter, TOA gray counter, fine TOA counter & VCO

25th February 2014 ESE Seminar – X.Llopart 53

 S. Kulis

Power Consumption after Reset

Digital Power Consumption [W] Analog Power Consumption [W]

25th February 2014 ESE Seminar – X.Llopart 54

 S. Kulis

Wafer Probing Yield [W1]

 Category A (52%):
 less than 30 bad pixels
(randomly distributed across the
whole matrix)
 Category B (8%):
 one dead column (more than 8
bad pixels in one column),
 or one dead super pixel (more
than 4 bad pixels in one sp),
 or more than 30 bad pixels
 Category C (20%):
 two dead double columns or
dead super pixels,
 or more than 256 bad pixels
 Category K (15%): Kidnapper pixel
 Category Y (5%) : Yelling pixel

25th February 2014 ESE Seminar – X.Llopart 55

 J. Visser
M. Van Beuzekom

First Timepix3 based TPC

Micromegas:
• 50 μm pillars;
• square pitch of holes: 60 μm
Timepix-3:
• no protection layer:

25th February 2014 ESE Seminar – X.Llopart 56

 J. Visser
M. Van Beuzekom

Hitmap

• Few minutes data at the 2 GeV

electron beam at DESY

• Moire pattern due to mismatch of

TPX3 and micromegas grid (55 and 60
um, resp.)

25th February 2014 ESE Seminar – X.Llopart 57

 J. Visser
M. Van Beuzekom

Track projections

Gas: He-Isobutane Gas: Ar-Isobutane

25th February 2014 ESE Seminar – X.Llopart 58

 Conclusions
• Timepix3 is a new version of the Timepix chip. Main characteristics:
– Simultaneous TOA and TOT measurement
– Data driven and zero-suppressed readout (80Mhits/s/chip)
– Minimum detectable charge > 500e- (all modes)
– Time resolution up to 1.562 ns

• All measurements (without sensor) indicate that the Timepix3 chip

is fully functional as designed

• First wafer probed shows reasonable yield comparable to

Medipix3RX

• First assemblies with a semiconductor sensor should be available in

< 2 months

25th February 2014 ESE Seminar – X.Llopart 59

 University of Canterbury, Christchurch, New Zealand
CEA, Paris, France
CERN, Geneva, Switzerland,
DESY-Hamburg, Germany
Albert-Ludwigs-Universität Freiburg, Germany
Acknowledgements
University of Glasgow, Scotland, UK
Leiden University, The Netherlands
NIKHEF, Amsterdam, The Netherlands
Mid Sweden University, Sundsvall, Sweden
IEAP, Czech Technical University, Prague, Czech Republic
ESRF, Grenoble, France
Universität Erlangen-Nurnberg, Erlangen, Germany
University of California, Berkeley, USA
VTT, Information Technology, Espoo, Finland
KIT/ANKA, Forschungszentrum Karlsruhe, Germany
University of Houston, USA
Diamond Light Source, Oxfordshire, England, UK
Universidad de los Andes, Bogota, Colombia
University of Bonn, Germany
AMOLF, Amsterdan, The Netherlands
Technical University of Munich, Germany
Brazilian Light Source, Campinas, Brazil
25th February 2014 ESE Seminar – X.Llopart 60
 Timepix4?

25th February 2014 ESE Seminar – X.Llopart 61

 SPARE

25th February 2014 ESE Seminar – X.Llopart 62

 S. Kulis

Wafer Probing - Digital Issues

• Dead pixels: Change of pixel configuration (trim
DAC, mask, test pulse) is not possible

• Kidnapper pixels: Pixel grabs readout token and

does not release it, preventing other pixels from
sending data (matrix reset is required)

• Yelling pixels: Once pixel starts sending data, it

does not stop (it produces continuous stream of
~400 khits/s)

19/02/2014
25th February 2014 ESE Seminar – X.LlopartSzymon KULIS (CERN) 63
 Pixel Operation Modes
ToA/ToT Mode:

Header Address ToA ToT Fine time

4 bits 16 bits 14 bits 10 bits 4 bits

Only ToA mode:

Header Address ToA Not used Fine time

4 bits 16 bits 14 bits 10 bits 4 bits

Event count mode:

Event
Header Address iToT Not used
count
4 bits 16 bits 14 bits 4 bits
10 bits

25th February 2014 ESE Seminar – X.Llopart 64

 Some photos

Diced chips in gelpack

25th February 2014 ESE Seminar – X.Llopart 65

 Motivation: Data driven Readout
instead of frame-based
% of pixels hit
1.00E+00
0.001 % 0.01
% % 0.1 % 1 % 10
% 100

1.00E-01

1.00E-02
Readout time of pixel matrix (s)

1.00E-03

1.00E-04 Frame-based (Timepix)

1.00E-05

1.00E-06
Break-even point
1.00E-07
Non-sparse

1.00E-08 Sparse-readout
Assumptions:
32 bits/pixel
1.00E-09
65536 pixels / chip

25th February 2014 ESE Seminar – X.Llopart 66

 Voltage DAC INL and DNL
5

1
LSB

1

2

3

4

5
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256

DAC Code
DNL
INL
+1 LSB
-1 LSB

25th February 2014 ESE Seminar – X.Llopart 67

 Timepix to Timepix3

Timepix (2006) Timepix3 (2013)

25th February 2014 ESE Seminar – X.Llopart 68

 Timepix chip architecture
Main Specs:
• 256x256 55µm square pixels
• Analog Power → 440mW

14080 m (pixel array)

• Bits stored in pixel → 14

3584-bit Pixel Column-255

3584-bit Pixel Column-1

•
3584-bit Pixel Column-0

Serial readout (@100Mbps) → 9.17 ms

• Parallel readout (@100Mbps) → 287 µs
• Full custom design
16120 m

• > 36M Transistors

Dynamic power is mitigated because:

• EoC is a serializer (FSR)
– 256-to-1 in serial readout
• Pixel Matrix frequency clock / 256
256-bit Fast Shift Register – 256-to-32 in parallel readout
• Pixel Matrix frequency clock / 8
Bandgap + 13 DACs
LVDS IO LVDS • Pixel column sequential readout clock:
In Logic 32-bit CMOS Output Out – Max readout clock frequency (parallel readout) at
pixel matrix is 12.5 MHz for a 3.2 Gbps chip
14111 m readout
– Column clock tree made by one “large” buffer in
the EoC
25th February 2014 ESE Seminar – X.Llopart 69