This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2016.2520913, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
An Envelope Type (E-Type) Module:
Asymmetric Multilevel Inverters
With Reduced Components
Emad Samadaei, S.A. Gholamian, A. Sheikholeslami, J. Adabi
1
Abstract— This paper presents a new E-Type module for
asymmetrical multilevel inverters with reduced components.
Each module produces 13 levels with four unequal DC sources
and 10 switches. The design of the proposed module makes some
preferable features with a better quality than similar modules
such as the low number of semiconductors and DC sources and
low switching frequency. Also, this module is able to create a
negative level without any additional circuit such as an H-bridge
which causes reduction of voltage stress on switches. Cascade
connection of the proposed structure leads to a modular topology
with more levels and higher voltages. Selective harmonics
elimination pulse width modulation (SHE-PWM) scheme is used
to achieve high quality output voltage with lower harmonics.
MATLAB simulations and practical results are presented to
validate the proposed module good performance. Module output
voltage satisfies harmonics standard (IEEE519) without any filter
in output.
Index Terms— Asymmetric, components, E-Type, multilevel
inverter, power electronics, selective harmonics elimination
I. INTRODUCTION
M ultilevel inverters (MLIs) have been innovated as
necessary cost benefit devices with a wide range of
applications. They have been in the focus for decades because
of interesting features such as high quality output voltage,
operation in high voltage/power, low stress on switches, etc.
Multilevel converters have a wide range of applications which
has rapidly developed the area of power electronics with good
potential for further technology [1-6].They can be used in
photovoltaic systems, wind farms, and HVDC systems.
Multilevel converters are different arrangements of
semiconductor switches with DC links to create n-level output
waveform which are divided into three main categories [7]:
Neutral Point Clamped (NPC), Flying Capacitor (FC) and
Cascade H-Bridge (CHB). In 1981, NPC was introduced as
the first multilevel converter which can be used in medium
voltage applications [8]. Early 1990s, FC was presented [9]
and in 1996, CHB was reintroduced [10]. Design of multilevel
inverters depends on the number of voltage levels, number of
semiconductors, output quality, number of DC supplies and
Manuscript received June 22, 2015; revised October 3, 2015, November
23, 2015 and January 4, 2016; accepted January 9, 2016.
Copyright © 2016 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be
obtained from the IEEE by sending a request to pubs-permissions@ieee.org.
Emad Samadaei, S.A. Gholamian, A. Sheikholeslami and J. Adabi are with
the Babol Noshirvani University of Technology, Department of Computer and
Electrical Engineering, Babol, Iran (email: e.samadaei@stu.nit.ac.ir,
gholamian@nit.ac.ir, asheikh@nit.ac.ir, j.adabi@nit.ac.ir).
0278-0046 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
DC link capacitors, THD amplitude, maximum voltage level,
creating positive and negative level, modularity, switch stress
and total standing voltage (TSV).
Researchers presented different types of modular multilevel
inverters. As shown in Fig.1.a, each level is created by two
switches and one source in [11]. These levels are connected in
series together to achieve positive voltage levels and an
auxiliary H-bridge circuit is used to create alternative voltage.
Note that, H-bridge switches tolerate more voltages than other
switches. As shown in Fig.1.b, the stress of H-bridge switches
are divided between each sub-module [12]. Two capacitors are
added for each DC source to reach more voltage levels with
the penalty of using more components. Researchers tried to
reach more levels with lower components. Asymmetric
multilevel inverters which have unequal DC links become
interesting in order to increase the quality of output waveform
by minimizing the number of components. Modules are
designed based on optimal using of DC links by reduced
switches [13-15]. Other MLI topologies are proposed in [16-
17] which are shown in Fig.1.f & Fig.1.g Also some
interesting MLI topologies are investigated in [18-19].
One of the important factors of MLI design for high voltage
applications is high voltage stress on the switches of the
output H-bridge. Therefore, a redesign is vital to reduce the
stress of the switches by dividing H-bridge voltage into all
sub-modules in order to have a uniform stress on all switches
which in turn leads to the increasing number of
semiconductors and total standing voltage (TSV) of the
module. This paper aims to achieve maximum capacity from
DC link by a suitable arrangement of switches which improves
economic implementation cost, switching frequency, TSV,
number of levels, and THD. It presents a new asymmetric
multilevel module based on cascade category which does not
need any additional circuit to create negative voltage levels.
Also, it makes 13 levels by reduced switches. Section 2
illustrates proposed multilevel inverters including module
description, switching patterns, cascade connection and
comparison table with similar modules. Selective harmonic
elimination (SHE) is introduced for switching modulation in
section 3. Loss Calculation is presented in section 4.
Simulation and experimental results are shown in sections 5,
and 6, respectively. Conclusions are presented in section 7.
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S21 T11 T21

V1 S11
2V1 V0,1

V1 S31 T31 T41

+ S41
VDC S1 S2
V0,1 S1 S′1
-
T12 T22 VDC1
S22
V2 S12
+ S′1 S′3
VDC S2 S4 2V2 V0,2
S′3 S3
V0,2 S32 T32 T42
V2 S42
- + VL - +
S2 S′2 Vo
Vo -
VDC2

S2m T1m T2m

Vm S1m
S′4 S′2 2Vm S4 S′4
VDC S2n-1 + V0,m

S2n S3m T3m T4m

V0,n Vm S4m
-

(a) (b) (c)

VDC
SNs-1 SNs
S1 S31
T1 T3
VDC S21 S11
VDC
VDC
+
+ VDC T1 T2
S2 Vo,1
-

S6 S5
VDC S′11
+ VDC
T2 T4 S′21
VL S3 + VL -
- VDC1
VDC AC Vo
VDC S32
Load
VDC S22 S12
S3 S4
T3 T4
T5 T7 VDC
VDC2
+
VDC Vo,1 -
S1 VDC S2
-
S′12
T6 T8 VDC
S′22

(d) (e) (f) (g)

Fig.1 Some modular multilevel inverter topologies
to generate a different number of output voltage levels. An
II. PROPOSED MOUDLE elimination in harmonic content peak with a same switching
Fig.2 shows a general schematic diagram of a typical frequency and the same structure is approximately expected
asymmetrical multilevel inverter with two DC links for by increasing the number of output voltage levels in the
description of multilevel operation. Unequal DC links can be asymmetrical inverter [20].
arranged with different connections (through switching
A. Module Configuration
components) in order to achieve high number of voltage
levels. This paper introduces a new topology of asymmetric
multilevel modular with a new component arrangement
including 10 switches, 10 diodes and 4 unequal DC sources
(two 2𝑉𝐷𝐶 , two 1𝑉𝐷𝐶 ) named as Envelope type (E-Type). This
VC1 arrangement synthesizes voltage sources produces 13 levels (6
- positive level, 6 negative level and zero level) without any
Vout additional circuit. The main concept of this circuit is to create
different paths from different sides of a DC source to be
VC2 connected to other sources. Fig.3 shows the configuration of
- E-Type asymmetrical module in where DC sources are located
in the middle of the circuit and are connected together to form
Fig.2 The general structure of asymmetric multilevel inverters different voltage levels via surrounding switch (S1-S6). A
bidirectional switch (S7) is required to avoid short circuit of
For example, assuming VC1=𝑉𝐷𝐶 and VC2=2𝑉𝐷𝐶 , voltage DC sources on left or right sides of the module. Another
levels of ±𝑉𝐷𝐶 ،±2𝑉𝐷𝐶 and ±3𝑉𝐷𝐶 can be achieved by bidirectional switch (S8) is also needed to achieve voltage
choosing suitable paths from switches and DC links depends levels of ±5𝑉𝐷𝐶 . Different switching conditions of this
on the module topology. Using this idea for multilevel structure are shown in Fig.3 and Table I.
inverters, a different ratio of DC link voltages may be utilized

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S1 S2

2VDC 2VDC

S3 S7 S4
1VDC 1VDC

S8
S5 S6

B
(a)

1VDC 2VDC 3VDC 4VDC 5VDC 6VDC

-1VDC -2VDC -3VDC -4VDC -5VDC -6VDC

(b)
Fig. 3 Proposed E-Type module of multilevel inverter (a) Circuit topology (b) different switching states

TABLE I to positive and negative levels, respectively. In addition, (S 1,

SWITCHING TABLE
S2) and (S3, S4) cannot be on at the same time. Fig.4 shows
S1 S2 S3 S4 S5 S6 S7 S8
1VDC 1 0 0 0 0 1 1 0 output voltage of the proposed inverter with the associated
2VDC 1 0 0 0 0 0 1 1 pulse pattern in one cycle of fundamental voltage. As shown
Positive
Level

3VDC 1 0 0 0 1 0 1 0 in Fig.4, switches S1, S2, S3, S4 and S7 are turned on and off in
4VDC 1 0 0 1 0 1 0 0 low frequency which reduces switching losses to a great
5VDC 1 0 0 1 0 0 0 1
6VDC 1 0 0 1 1 0 0 0 extent. Other switches also operate in a reasonable switching
-1VDC 0 1 0 0 1 0 1 0 frequency.
-2VDC 0 1 0 0 0 0 1 1 Table II shows number of voltage levels, semiconductor
Negative

-3VDC 0 1 0 0 0 1 1 0
level

components, DC sources and drivers based on number of

-4VDC 0 1 1 0 1 0 0 0
-5VDC 0 1 1 0 0 0 0 1
module units (n) and number of desired levels (N L).
-6VDC 0 1 1 0 0 1 0 0 TABLE II
EQUATIONS OF E-TYPE MODULE
6VDC Based on number of Based on number of
5VDC module units desired levels*
4VDC Levels 12n+1 NL
3VDC
2VDC
Number of Switches 10n 5(NL-1)/6
1VDC Number of Diodes 10n 5(NL -1)/6
Driver 8n 8(NL -1)/6
-1VDC
-2VDC
Number of DC Link 4n (NL -1)/3
-3VDC TSV 20n 10(NL-1)/6
-4VDC *
Number of levels are in the form of 12n+1 (n=1, 2, 3, ….)
-5VDC
-6VDC
Fig.3.b shows all switching states of E-type module. The
S1
S2
designing of the proposed module and their switching paths
S3 are smartly selected in such a way that there are no positive
S4 pole of DC links on the anode side of diode to conduct. Thus,
S5
S6 diodes prevent short circuiting of the switches. Also Fig.3.b
S7
S8
illustrates the switching paths dose not form any close loop for
Fig.4 Switching pattern of proposed converter in one cycle DC links. It guarantees that short circuiting will be not
As shown in Table I, switch pairs (S1, S4) and (S2, S3) belong occurred in E-type module.

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B. Module Extension 11,….., 1 paths to achieve 1VDC ,2VDC , ……, 12VDC,

Modular connection of the proposed topology leads to respectively in this configuration. This in turn led to an
achieve more voltage levels with different possible paths. improvement in the reliability of the modular inverter which
Fig.5 shows a two-module structure which facilitates enables it to use different paths in case of any failure or
generation of 25 levels. According to Table III, there are 12, malfunction for a switch or a driver.
TABLE III
SWITCHING PATHS FOR TWO MODULES
Level Paths Num. of paths
12VDC (u1=6, u2=6) 1
11VDC (u1=5, u2=6), (u1=6, u2=5) 2
10VDC (u1=4, Vu2=6), (u1=5, u2=5), (u1=6, u2=4) 3
9VDC (u1=3, u2=6), (u1=4, u2=5), (u1=5, u2=4), (u1=6, u2=3) 4
8VDC (u1=2, u2=6), (u1=3, u2=5), (u1=4, u2=4), (u1=5, u2=3), (u1=6, u2=2) 5
7VDC (u1=1, u2=6), (u1=2, u2=5), (u1=3, u2=4), (u1=4, u2=3), (u1=5, u2=2), (u1=6, u2=1) 6
6VDC (u1=0, u2=6), (u1=1, u2=5), (u1=2, u2=4), (u1=3, u2=3), (u1=4, u2=2), (u1=5, u2=1), (u1=6, u2=0) 7
5VDC (u1=-1, u2=6), (u1=0, u2=5), (u1=1, u2=4), (u1=2, u2=3), (u1=3, u2=2), (u1=4, u2=1), (u1=5, u2=0), (u1=6, u2=-1) 8
4VDC (u1=-2, u2=6), (u1=-1, u2=5), (u1=0, u2=4), (u1=1, u2=3), (u1=2, u2=2), (u1=3, u2=1), (u1=4, u2=0), (u1=5, u2=-1), (u1=6, u2=-2) 9
3VDC (u1=-3, u2=6), (u1=-2, u2=5), (u1=-1, u2=4), (u1=0, u2=3), (u1=1, u2=2), (u1=2, u2=1), (u1=3, u2=0), (u1=4, u2=-1), (u1=5, u2=-2), (u1=6, u2=-3) 10
2VDC (u1=-4, u2=6), (u1=-3, u2=5), (u1=-2, u2=4), (u1=-1, u2=3), (u1=0, u2=2), (u1=1, u2=1), (u1=2, u2=0), (u1=3, u2=-1), (u1=4, u2=-2), (u1=5, u2=-3), (u1=6, u2=-4) 11
1VDC (u1=-5, u2=6), (u1=-4, u2=5), (u1=-3, u2=4), (u1=-2, u2=3), (u1=-1, u2=2), (u1=0, u2=1), (u1=1, u2=0), (u1=2, u2=-1), (u1=3, u2=-2), (u1=4, u2=-3), (u1=5, u2=-4), (u1=6, u2=-5) 12
0VDC (u1=-6, u2=6), (u1=-5, u2=5), (u1=-4, u2=4), (u1=-3, u2=3), (u1=-2, u2=2), (u1=-1, u2=1), (u1=0, u2=0) 7
-1VDC (u1=-6, u2=5), (u1=-5, u2=4), (u1=-4, u2=3), (u1=-3, u2=2), (u1=-2, u2=1), (u1=-1, u2=0), (u1=0, u2=-1), (u1=1, u2=-2), (u1=2, u2=-3), (u1=3, u2=-4), (u1=4, u2=-5), (u1=5, u2=-6) 12
-2VDC (u1=-6, u2=4), (u1=-5, u2=3), (u1=-4, u2=2), (u1=-3, u2=1), (u1=-2, u2=0), (u1=-1, u2=-1), (u1=0, u2=-2), (u1=1, u2=-3), (u1=2, u2=-4), (u1=3, u2=-5), (u1=4, u2=-6) 11
-3VDC (u1=-6, u2=3), (u1=-5, u2=2), (u1=-4, u2=1), (u1=-3, u2=0), (u1=-2, u2=-1), (u1=-1, u2=-2), (u1=0, u2=-3), (u1=1, u2=-4), (u1=2, u2=-5), (u1=3, u2=-6) 10
-4VDC (u1=-6, u2=2), (u1=-5, u2=1), (u1=-4, u2=0), (u1=-3, u2=-1), (u1=-2, u2=-2), (u1=-1, u2=-3), (u1=0, u2=-4), (u1=1, u2=-5), (u1=2, u2=-6) 9
-5VDC (u1=-6, u2=1), (u1=-5, u2=0), (u1=-4, u2=-1), (u1=-3, u2=-2), (u1=-2, u2=-3), (u1=-1, u2=-4), (u1=0, u2=-5), (u1=1, u2=-6) 8
-6VDC (u1=-6, u2=0), (u1=-5, u2=-1), (u1=-4, u2=-2), (u1=-3, u2=-3), (u1=-2, u2=-4), (u1=-1, u2=-5), (u1=0, u2=-6) 7
-7VDC (u1=-6, u2=-1), (u1=-5, u2=-2), (u1=-4, u2=-3), (u1=-3, u2=-4), (u1=-2, u2=-5), (u1=-1, u2=-6) 6
-8VDC (u1=-6, u2=-2), (u1=-5, u2=-3), (u1=-4, u2=-4), (u1=-3, u2=-5), (u1=-2, u2=-6) 5
-9VDC (u1=-6, u2=-3), (u1=-5, u2=-4), (u1=-4, u2=-5), (u1=-3, u2=-6) 4
-10VDC (u1=-6, u2=-4), (u1=-5, u2=-5), (u1=-4, u2=-6) 3
-11VDC (u1=-6, u2=-5), (u1=-5, u2=-6) 2
-12VDC (u1=-6, u2=-6) 1
*u1=𝑉𝑉𝐴1𝐵1, u2=𝑉𝑉𝐴2𝐵2
𝐷𝐶 𝐷𝐶
A1
(MLDCL) [11], two capacitor links H-bridge (2CLHB) [12],
S1 S2 crossing switch MLI (CSMLI) [14], U-cell [15] and 2DCLML
2VDC 2VDC
[19]. According to Table IV, the number of semiconductors
(switches and diodes), number of DC links and TSV are
5(𝑁 −1) (N −1) 10(𝑁 −1)
S3 S7 S4
reduced down to 𝐿 , L and 𝐿
VDC respectively
1VDC 1VDC 6 3 6
which are lower than other topologies. Fig.6 shows the
S8
S5 S6 comparisons the number of switches, DC links and TSV in
B1
terms of number of levels in statistics which illustrates
predominance of proposed module in all comparisons. Note
A2
that this topology can generate negative voltage levels which
S1 S2 does not need any additional circuit. This ability along with
2VDC 2VDC lower components and stress on the devices confirms that the
proposed inverter can perform well in comparison with other
S3 S7 S4 existing ones.
1VDC 1VDC

S8
S5 S6

B2

Fig.5 The cascade arrangement of modular proposed multilevel

C. Comparative Study
As shown in Table IV, a comparative study between the
proposed topology and other famous ones is carried out
regarding the number of semiconductors, DC links, TSV,
capability to generate negative voltage level and the number of
switches and PIV in terms of DC links number. Among these
(a)
topologies are: NPC, FC, CHB, Multilevel DC Links

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(b) (c)
Fig.6 The number of switches (a), DC links (b) and TSV (c) in terms of number of levels
TABLE IV
COMPARISON OF SOME MODULAR MULTILEVEL INVERTER TOPOLOGY
MLDCL 2CLHB CSMLI U-cell 2DCLML PROPOESD
NPC FC CHB
[11] [12] [14] [15] [19] (E-Type)
Num. of Switches 2(NL -1) 2(NL -1) 2(NL -1) NL+3 NL +1 NL +1 NL+1 NL -1 5(NL-1)/6
Num. of Diodes NL +1 2(NL -1) 2(NL -1) NL+3 NL +1 NL +1 NL+1 7(NL -1)/3 5(NL-1)/6
Num. of DC links (NL-1)/2 ( NL-2) (NL-1)/2 (NL-1)/2 (NL-1)/2 (NL-1)/2 (NL-1)/2 (NL -1)/3 (NL-1)/3
TSV* (xVDC) 2(NL -1) 2(NL -1) 2(NL -1) 3(NL -1) 2(NL -1) 2(NL -1) 2(NL -1) 2(NL-1) 10(NL-1)/6
With at With at
With With With With With
Negative level least least inherent inherent
H-Bridge H-Bridge H-Bridge H-Bridge H-Bridge
Two arms Two arms
Num. of switches in 2+ 1/3+ 2+ 2+ 2+
4 4 3 5/2
terms of DC links 2/( NL-2) 4/3( NL-1) 4/( NL-1) 4/( NL-1) 4/( NL-1)
PIV** in terms of 2+
4 4 6 4 4 4 6 5
DC source 2/( NL-2)
* Total Standing Voltages **Peak Inverse Voltage
As 𝑓𝑛 (𝑡) is odd, the equation can be rewritten as:
III. SELECTIVE HARMONIC ELIMINATION MODULATION 2𝜋𝑛𝑡
𝑓𝑛 (𝑡) = ∑𝑛𝑛=1 (𝑏𝑛 sin ( )) (2)
METHOD 𝑇
Where bn as follows, v is step level voltage:
Selective harmonic elimination modulation (SHE-PWM) 4𝑉
𝑏𝑛 = ∑𝑖𝑖=1 sin(𝑛𝛼𝑖 ) (3)
method is utilized in this paper to create pulse pattern for the 𝑛𝜋
proposed inverter. In this method, as shown in Fig.7, different For proposed topology, as shown in Fig.7, there are 6
angles (𝛼1 , … , 𝛼6 ) are calculated to form a staircase multilevel voltage levels in a quarter-wave symmetry and therefore 6
waveform with the lowest possible THD. The method is switching angles (αi) have to be calculated. Third harmonic
implemented based on optimization techniques where each multiples are eliminated in three phase systems. Thus 9 th and
desired harmonic order can be eliminated. Selection of 15th harmonics are not considered in the equations. It helps to
switching angles for a multilevel converter is presented in [21- consider more harmonic components in equations for
22] using a phase-shift harmonic suppression approach. elimination (such as 17th and 19th instead of 9th and 15th). 3rd is
Generally, SHE-PWM is based on the Fourier series just considered for its higher amount in equations in single
decomposition of the periodic PWM voltage waveform and phase systems to reduce THD%. To eliminate 3th, 5th, 7th, 11th,
calculation of the switching angles (αi) in order to eliminate 13th, 17th and 19th harmonic orders, (4) have to be solved in
selected low harmonic orders. Fourier series of a periodic order to achieve α1 to α6 with the condition of 0 < 𝛼1 < 𝛼2 <
function can be written as: 𝜋
𝛼3 < 𝛼4 < 𝛼5 < 𝛼6 < . Fig.8 illustrates switching angles for
2
𝑎0 2𝜋𝑛𝑡 2𝜋𝑛𝑡 different modulation indexes (ma). Table V shows the results
𝑓𝑛 (𝑡) = + ∑𝑛𝑛=1 (𝑎𝑛 cos ( ) + 𝑏𝑛 sin ( )) (1) for the degree of each step level with ma= 0.98.
2 𝑇 𝑇

4𝑉
𝑏1 = [cos( 𝛼1 ) + cos( 𝛼2 ) + cos( 𝛼3 ) + cos( 𝛼4 ) + cos( 𝛼5 ) + cos( 𝛼6 )]
1𝜋
4𝑉
𝑏3 = [cos(3 𝛼1 ) + cos(3 𝛼2 ) + cos(3 𝛼3 ) + cos(3 𝛼4 ) + cos(3 𝛼5 ) + cos(3 𝛼6 )] = 0
3𝜋
4𝑉
𝑏5 = [cos(5 𝛼1 ) + cos(5 𝛼2 ) + cos(5 𝛼3 ) + cos(5 𝛼4 ) + cos(5 𝛼5 ) + cos(5 𝛼6 )] = 0
5𝜋
4𝑉
𝑏7 = [cos(7 𝛼1 ) + cos(7 𝛼2 ) + cos(7 𝛼3 ) + cos(7 𝛼4 ) + cos(7 𝛼5 ) + cos(7 𝛼6 )] = 0
7𝜋
4𝑉 (4)
𝑏11 = [cos(11𝛼1 ) + cos(11𝛼2 ) + cos(11𝛼3 ) + cos(11𝛼4 ) + cos(11𝛼5 ) + cos(11𝛼6 )] = 0
11𝜋
4𝑉
𝑏13 = [cos(13𝛼1 ) + cos(13𝛼2 ) + cos(13𝛼3 ) + cos(13𝛼4 ) + cos(13𝛼5 ) + cos(13𝛼6 )] = 0
13𝜋
4𝑉
𝑏17 = [cos(17𝛼1 ) + cos(17𝛼2 ) + cos(17𝛼3 ) + cos(17𝛼4 ) + cos(17𝛼5 ) + cos(17𝛼6 )] = 0
17𝜋
4𝑉
{ 𝑏19 = 19𝜋 [cos(19𝛼1 ) + cos(19𝛼2 ) + cos(19𝛼3 ) + cos(19𝛼4 ) + cos(19𝛼5 ) + cos(19𝛼6 )] = 0

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2016.2520913, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 6

calculated for switch and the antiparallel diode which is highly

6VDC proportional to the switching frequency (fs). Turn-on and turn-
5VDC off energy loss (Eon, Eoff) can be obtained as follows:
4VDC 𝑡 𝑡 𝑣𝑠𝑤,𝑘 𝐼
𝐸𝑜𝑓𝑓,𝑘 = ∫0 𝑜𝑓𝑓 𝑣(𝑡)𝑖(𝑡)𝑑𝑡 = ∫0 𝑜𝑓𝑓 [( 𝑡) (− (𝑡 −
3VDC 𝑡𝑜𝑓𝑓 𝑡𝑜𝑓𝑓

2VDC 1
𝑡𝑜𝑓𝑓 ))] 𝑑𝑡 = 𝑣𝑠𝑤,𝑘 𝐼 𝑡𝑜𝑓𝑓 (7)
1VDC 6

𝑡 𝑡 𝑣𝑠𝑤,𝑘 𝐼′
α1 α2 α3 α4 α5 α6 π-α6 π-α5 π-α4 π-α3 π-α2 π-α1 π 𝐸𝑜𝑛,𝑘 = ∫0 𝑜𝑛 𝑣(𝑡)𝑖(𝑡)𝑑𝑡 = ∫0 𝑜𝑛 [( 𝑡) (− (𝑡 −
𝑡𝑜𝑛 𝑡𝑜𝑛
Fig.7 Shows the waveform of Selective harmonic elimination modulation to
find αi (Quarter wave symmetry) 1
𝑡𝑜𝑛 ))] 𝑑𝑡 = 𝑣𝑠𝑤,𝑘 𝐼 ′ 𝑡𝑜𝑛 (8)
6

Fig.8 Calculated switching angles for different modulation indexes (ma)
TABLE V
DEGREE OF EACH STEP LEVEL WITH Ma=0.98
αi α1 α2 α3 α4 α5
Degree 5.0790 16.0650 22.0270 33.4990 50.0570
IV. CALCULATION OF LOSSES
During the operation of power electronics switching devices,
two important types of power losses are considered: (1)
Conduction losses, (2) Switching losses. Fig.9 illustrates the
power losses on switch voltage and current curve. Loss
calculation in multilevel inverters is complicated. This is due
to a difference between currents of semiconductor devise
which leads to different losses behavior in multilevel inverters.
Fig.9 Power losses of power electronics switching devices
A. Conduction losses
Conduction losses (Pc) is defined in on-state of power
electronic devices. For this purpose, a typical power transistor
and diode are considered; then they will be extended to a
multilevel inverter. The instantaneous conduction losses of a
transistor (pc,T(t)) and diode (pc,D(t)) can be written as
follows:
pc,T(t) = [VT + RT iβ (t)] i(t) (5)
pc,D(t) = [VD + RD i(t)] i(t) (6)
Where VT and VD are the on-state voltage of the transistor
and diode, respectively. RT and RD are the equivalent
resistance of the transistor and diode, respectively, and β is a
constant related to the specification of the transistor. Losses of
each device is calculated based on (5) and (6) and add together
to reach conduction losses of proposed circuit.
B. Switching Losses
The switching loss (Psw) is dissipated power during the
switching turn-on and the turn-off of the power. This loss is
Where Eoff,k is the turn-off loss of the switch k, toff is the turn
off time of the switch, I (I’) is the current through the switch
before (after) turning off (on), and V sw,k is the off-state voltage
on the switch. Eon,k is the turn-on loss of the switch k, ton is the
turn-on time of the switch. Thus:
𝑁𝑠𝑤𝑖𝑡𝑐ℎ 𝑁𝑜𝑛,𝑘 𝑁𝑜𝑓𝑓,𝑘
𝑃𝑠𝑤 = 𝑓 [∑𝑘=1 (∑𝑖=1 𝐸𝑜𝑛,𝑘𝑖 + ∑𝑖=1 𝐸𝑜𝑓𝑓,𝑘𝑖 )] (9)
Where f is the fundamental frequency, Non,k and Noff,k are the
number of turning on and off the switch k during a period.
Also, Eon,ki is the energy loss of the switch k during the ith
turning on and Eoff,ki is the energy loss of the switch k during
α6
the ith turning OFF. The total losses of the multilevel inverter
63.0570 will be:
𝑃𝐿𝑜𝑠𝑠 = 𝑃𝐶 + 𝑃𝑠𝑤 (10)
In this paper, following parameters are considered to
calculate power loss of proposed module:
RT =0.15Ω, VT =2.5 V, RD =0.1Ω, VD =1.5 V, β =1,
ton=toff=1 μs, f =50 Hz. Each dc voltage source has the value of
50 V. The resistance of the load is 150 Ω.
The calculation is curried out for each switch for one period
by Eqs. (5) to (10) and total losses (P sw) for 1 second are
evaluated 2.9218 mW. Also load consumes 85 mW (𝑃𝐿𝑜𝑎𝑑 =
𝑉𝑜𝑢𝑡,𝑅𝑀𝑆 2
for 1 second). Therefore the efficiency of proposed
𝑅×3600
inverter is 96.56% which is due to low switching frequency
for each switch (see Fig.4).
V. SIMULATIONS RESULTS
The proposed multilevel module is simulated by MATLAB
to examine the performance of proposed module. Fig.10
shows the output voltage of 13-levels (Each level is 50 volts)
for the proposed multilevel with SHE modulation switching
method with THD% of 3.46%. It satisfied IEEE 519 (i.e. max.
of THD%: 8%, max. of THD for each order: 5%).
Fig.10 Output voltage and FFT analysis of proposed multilevel

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2016.2520913, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 7

VI. EXPERIMENTAL RESULTS

Experimental results are carried out to verify the
results of simulation and analysis in order to achieve a 13-
level sinusoidal waveform. Each level is considered 50 volts,
and thus there are two 50 volts and two 100 volts DC sources.
IGBT12N60A4, Diode RHRP15120 are used in the laboratory
model.
As mentioned in section III, angles are calculated
offline by solving (4). Therefore, calculated angles are
programmed in microcontroller to generate pulses for different
switches. Based on the diagram of Fig.11, the Microcontroller
(b)
ATMEGA16 provides on/off pulses for all switches. These
pulses are needed to be amplified in order to drive IGBTs.
Isolation from control and power sections of the circuit is also
required. These tasks are done by an optocoupler-driver
(HCPL3120). Output pulses of HCPL driver are applied
between gate and emitter legs of IGBT. Fig.12 shows
Experimental setup picture in laboratory.
HCPL3120
V in1 Vout1

Vout1
ATM16 BUFFER
Vout2

V in2 Vout2
(c)
IGBT/DIODE
Fig.11 Schematic of configuration in laboratory

(d)
Fig.13 Experimental results for output voltage (a) 10 HZ (b) 50HZ (c) 100HZ
(d) FFT analysis for one cycle

Different resistive - inductive load are used to show the

Fig.12 Experimental setup picture in laboratory
Fig.13 depicts voltage waveform of the proposed E-Type
module for 10 Hz (Fig.13.a), 50 Hz (Fig.13.b) and 100 Hz
(Fig.13.c). FFT analysis for one cycle is illustrated in Fig.13.d
where THD of experimental waveform is 4.54%.
performance of the proposed module. Fig.14 demonstrates
voltage and current 50 Hz sinusoidal waveforms of the
proposed module under resistive load with PF=1 (Fig.14.a)
and under resistive- inductive loads with PF=0.9 and PF=0.8
(Fig.14.b, c)

(a) (a)

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2016.2520913, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
(b)
(c)
Fig.14 Experimental results on R-L loads (a) R=150Ω, L=0, PF=1 (b)
R=150Ω, L=240mH, PF=0.9 (c) R=150Ω, L=400mH, PF=0.8
VII. CONCLUSION
This paper presented a new multilevel inverter topology
named as Envelope Type (E-Type) module which can
generate 13 levels with reduced components. It can be used in
high voltage high power applications with unequal DC
sources. As E-Type module can be easily modularized, it can
be used in cascade arrangements to form high voltage outputs
with low stress on semiconductors and lowering the number of
devices. Modular connection of these modules leads to
achieve more voltage levels with different possible paths. It
causes an improvement in the reliability of the modular
inverter which enables it to use different paths in case of
malfunction for a switch or a driver. The main advantage of
proposed module is its ability to generate both positive and
negative output voltage without any H-bridge circuit at the
output of the inverter. THDv% is obtained 3.46% and 4.54%
in simulation and experimental results, respectively that
satisfy harmonics standard (IEEE519). Also module is tested
in three frequency and under different resistive – inductive
loads which results shows good performance.
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Emad Samadaei was born in Q'aemshahr, Iran. He
received his B.Sc. degree from the College of
Engineering, Mazandaran University, Babol, Iran in
2008. He received the M.Sc. degree from the faculty
of Electrical and Computer Engineering, Babol
University of technology, Babol, Iran in 2010. He is
currently a Ph.D. Student at Power Electronics,
Renewable Energy in power electronics laboratory at
the Electrical and Computer Engineering Department,
Babol University of technology.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2016.2520913, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 9

Sayyed Asghar Gholamian was born in Babolsar,

Iran, in 1976. He received a B.Sc. degree in electrical
engineering from K.N.Toosi University of
Technology, Tehran, Iran in 1999 and a M.Sc. degree
in electric power engineering (electrical machines)
from university of Mazandaran, Babol, Iran in 2001.
He also received the Ph.D degree in electrical
engineering from K.N.Toosi University of
Technology, Tehran, Iran in 2008. He is currently an
assistant professor in the department of Electrical
Engineering at the Babol University of Technology, Iran. His research
interests include power electronic and design, simulation, modeling and
control of electrical machines.

Abdolreza Sheikholeslami was born in Iran. He

received the B.Sc. (Hons.) degree from Mazandaran
University, Iran, and the M.Sc. and Ph.D. degrees
from the University of Strathclyde, Glasgow, U.K., in
1978 and 1989, respectively. He has been an
Associate Professor with the Department of Electrical
and Computer Engineering, Noshirvani University,
Babol, Iran, since 2009. His current research interests
include power electronic, power quality, harmonics,
smart grids, and renewable energy.

Jafar Adabi was born in 1981. He received his BEng

and MEng degrees from Mazandaran University,
Babol, Iran, in 2004 and 2006, respectively. He
finished his PhD degree in the School of Engineering
Systems at the Queensland University of Technology,
Brisbane, Queensland, Australia at 2010. Currently, he
is an assistant professor at Noshirvani University of
Technology, Babol, Iran. His research interests are the
optimal design and high frequency modelling of power
electronics and motor drive systems for EMI analysis.

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