IET Power Electronics

Research Article

ISSN 1755-4535
Modelling and control of a novel zero-current- Received on 28th April 2015
Revised on 2nd May 2016
switching inverter with sinusoidal current Accepted on 17th May 2016
doi: 10.1049/iet-pel.2015.0296
output www.ietdl.org

Wei Liu ✉, Jiasheng Zhang, Rong Chen

College of Information and Control Engineering, China University of Petroleum, No. 66, Changjiang West Road, Huangdao District,
Qingdao, People’s Republic of China
✉ E-mail: liuwei_upc@163.com

Abstract: This study presents a novel topology of charge-transferring zero-current-switching (CT-ZCS) inverter to improve
the efficiency. Its operating principle, optimal zero-current-switching (ZCS) frequency and design guidelines are
elucidated in detail. A reduced-order modelling method of time-charge discretisation, which treats a set of two separate
ZCS as one combined switch cell, is put forward and the topology can be simplified to dual-buck half-bridge
inverter (DBHBI) topology. Since the DBHBI-derived CT-ZCS inverter permits higher comparison frequency of hysteresis
control than traditional hard-switching inverters, the three-level relay control with high-frequency pulse modulation
is recommended. Compared with two-level and three-level hysteresis control, the proposed control can
achieve effective output harmonic reduction, decreasing from 2.335 to 1.66%, and minimise the size of inverter
under the same output condition. In addition, a current controller is designed to optimise the system and enhance
its anti-disturbance performance. Finally, the experiment on a 35-V 2-A prototype verifies the validity of the
proposed method.

1 Introduction For analysis of soft-switching inverters, the major problems are

With the rapid development of power devices and integrated digital
signal processors, current-source inverters (CSIs) begin to attract
more attention and have been applied on some occasions,
including grid-connected generation system, uninterruptible power
supply and AC motor drives. However, most of CSIs are
implemented by hard-switching inverters [1, 2]. In recent years,
some drawbacks of traditional hard-switching CSIs were
overcome by employing soft-switching technology [3–5], such as
switching losses, capacitive turn-on, inductive turn-off, reverse
recovery of the intrinsic body diodes and electro-magnetic
interference (EMI) caused by hard-switching. To force the voltage
across switches or current through switches to be zero alternatively
during changing the switching state, series or parallel resonance
of inductors and capacitors is used in circuits [6, 7] and the
auxiliary circuit is also introduced [8] to achieve soft-switching
operation. Furthermore, the novel CT-ZCS inverters can also
achieve the sinusoidal current output by employing the AC-side
inductor and it is a dual-buck half-bridge inverter (DBHBI)-
derived inverter by improving the hard-switching DBHBI to
reduce the switching losses. It can replace the DBHBI as an AC
power supply or a single-phase inductive motor drive for
low-power applications.
Pulse width modulation (PWM) and pulse density modulation
(PDM) have been widely applied to the control of soft-switching
converters and inverters [9, 10]. For most soft-switching
converters, hysteresis control is still the preferred method to
achieve PDM [11, 12] due to its attractive advantages, such as fast
dynamic response, simplicity, reliability and high stability. The
proposed three-level relay control in this paper is a specific
hysteresis control. Since the switching losses can be eliminated by
employing soft-switching technology, the soft-switching inverters
permit higher comparison frequency of hysteresis control than
traditional hard-switching inverters [13, 14]. Therefore, the better
output quality and effective harmonic reduction can be achieved
by using three-level relay control compared with hysteresis control
based on the same soft-switching inverter.
listed as follows. First, most schemes are developed for the
topologies and parameter design guidelines of soft-switching
converters and inverters but lack of available modelling methods
correspondingly [6, 7]. Second, topologies of resonant
soft-switching inverters are generally complicated, thus the
related modelling methods and theories are imperfect and
flawed. The state-space averaging method has been widely used
for modelling of switching inverters, but the linearised model
cannot predict the large-signal stability and it is only sufficient
to predict small-signal stability. The generalised state space
averaging method also takes the dead-time effect into
consideration and provides effective means for precise close-loop
controller design [15, 16]. However, the full-order modelling
approach will become tedious or even invalid to controller
design in inverters, especially in the discontinuous conduction
mode, when the number of power devices increases. The PWM
switching model provides an averaged-circuit representation of the
converter [17, 18], which is feasible for single PWM inverters or
small-scale PWM converter and inverter systems. However,
switching models for middle-scale, large-scale or PDM converter
and inverter systems are complicated [19, 20]. Signal flow graph
modelling [21] and switching flow-signal graph modelling [22] are
apt to derive and they provide a visual representation of the
converter and inverter system. Moreover, the large-signal,
steady-state and small-signal models for PWM converters and
inverters can also be obtained easily. Nevertheless, both
techniques mentioned above are less efficient for analysis of the
PDM inverters.
As for the complex topologies and PDM control of some
soft-switching inverters, it is inadvisable to establish the
large-signal or small-signal averaged model directly [23]. To
overcome the problems, a reduced-order modelling method of
soft-switching converters based on time-scale separation is
mentioned by eliminating the fast-changing resonant variables in
the modelling process [24]. Another potent reduced-order
modelling method is suggested to simplify the complex switching
topology to a typical topology in this paper. Furthermore, the

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small-signal and large-signal models can then be developed to
analyse its performance and accomplish controller design.
This paper proposes a novel CT-ZCS inverter with current output
by substituting the AC-side inductor for the DC-side inductor. It
mainly focuses on four aspects of the inverter in operating
principle, design guidelines of resonant parameters, modelling
method and control strategy. According to the characteristic that
the inverter transfers quantified charges to the load side in each
duty cycle of ZCS, the concept of discretising time and charges is
proposed to simplify topology. By replacing a set of soft switches
with one combined switch cell, the CT-ZCS inverter is simplified
to a more typical DBHBI. Inner voltage loop achieves output
voltage ripple reduction effectively under three-level relay voltage
control with high-frequency pulse modulation (HFPM), and the
non-linear system of equivalent DBHBI is stable without constant
amplitude oscillation. Besides, a current regulator is introduced to
enhance its anti-disturbance performance and guarantee output
waveform quality. The presented inverter has advantages of high
efficiency, low output harmonic, reducing the size and high power
density for low-power applications.
2 CT-ZCS inverter and its control system
2.1 Novel CT-ZCS inverter
To eliminate the disadvantages of conventional hard-switching
inverters, the topology of CT-ZCS inverter is recommended and
improved compared with the conventional topologies. The
series-resonant characteristic of inductors and capacitors is utilised
to ensure that the switching states change at zero-crossing point of
resonant currents directly, thus ZCS is achieved and the switching
losses of inverter can be reduced effectively by ZCS technology.
The topology and proposed control system of the CT-ZCS inverter
are presented in Fig. 1a. Each of switches S1–S4 is constructed by
using a series-connected IGBT and diode. Moreover, the structure
of CT-ZCS inverter is complementary symmetry. In addition to
small resonant inductors, a smoothing inductor LL is added to the
load side. This technique helps the output AC voltage across filter
capacitor CL (uCL ) convert to load current io in nature.
2.2 Proposed control strategy
Since the CT-ZCS inverter is under three-level relay control with
HFPM, each switch operates strictly at ZCS turn-on and ZCS
turn-off in each comparison period Ts, which means the switching
Fig. 1 Novel CT-ZCS inverter with proposed control
a CT-ZCS inverter system
b Control signals
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states change at the inductor-current zero crossing point. In
addition, it needs to delay appropriately turning off or turning on
to ensure ZCS at the end of Ts as before. Hence, variable time
delay is imperative as shown in Fig. 1. Event-Trigger Submodule
of TMS320F28335 can trigger an interrupt at the end of each
HFPM cycle. To implement variable time delay, TMS320F28335
does not process the generated comparison logic of three-level
relay control until interrupt arrival. Compared with hystersis
control, the three-level relay control performs better output
waveform quality and higher tracking accuracy. The inductors (L1
and L2), capacitors (C1 and CL) and switches (S1 and S2) constitute
the soft switching resonant circuit of positive group, meanwhile
the inductors (L3 and L4), capacitors (C2 and CL) and switches (S3
and S4) constitute the negative one, where uC1 and uC2 are the
voltages across C1 and C2, and iC1 are the current through C1. The
currents iL1 iL4 are currents through L1–L4, and the voltages
VS1 V S 4 , VS1 D V S 4 D , VD1 and VD2 are voltages across S1–S4,
series-connected diodes in S1–S4, D1 and D2, respectively.
Besides, uref is the voltage reference of inner loop, iref is the
current reference of outer loop and H is the hysteresis band.
3 CT-ZCS operation and design guidelines
3.1 Operation principle
In Fig. 1b, f1 and T1 are the frequency and period of high-frequency
pulse, respectively. Correspondingly, f and T are the resonant
frequency and period. The operation principle of proposed inverter
is analysed in detail and its operation modes and equivalent
circuits during a complete switching cycle are shown in Fig. 2.
To commence with the analysis, some assumptions are made as
follows:
(i) All the switches and diodes are ideal.
(ii) All the inductors and capacitors are ideal.
(iii) The filter capacitor CL is large enough, and the output voltage
uCL is constant in one switching period.


(iv) At the beginning of T1, the initial voltage uC1 0− is −Ud.
(v) L1 = L2 = L3 = L4 = L, C1 = C2 = C ≪ CL, iL1 = iL3 and iL2 = iL4 .
(vi) F is a symbol of real-time charge-transfer state. ‘1’ stands for
positive charge transfer of the CT-ZCS inverter, ‘−1’ for negative
charge transfer and ‘0’ for no charge transfer.
Under proposed control, the operation principle can fall into three
modes as follows. The series resonant frequency of equivalent
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Fig. 2 Operation modes and equivalent circuits during a complete switching cycle
a Mode 1 (Stage 1)
b Mode 2 (Stage 1)
c Mode 1 (Stage 3)
d Mode 2 (Stage 3)
e Mode 1 (Stage 4)
f Mode 2 (Stage 4)
g Mode 1 (Stage 2), Mode 2 (Stage 2) and Mode 3

circuits in Fig. 2 can be calculated as domain as follows

1 ⎧
f = √ (1) ⎪
⎪ (Ud /s) − (uC1 (0− )/s)
2p LC ⎪
⎨ iL1 (s) = R + L s + (1/C s)
1 1
1 (2)
where 1/(1/C1 + 1/CL) ≃ C1 = C. ⎪
⎪ Ud uC1 (0− ) 1/C1 s
⎪ uC (s) =
⎩ −
1 s s R1 + L1 s + (1/C1 s)

3.1.1 Mode 1 [uref . uCL + H] [refer to Figs. 2a, g, c and e]: Formula (2) can be solved as follows
In this mode, S1, S2 and D1 of the CT-ZCS inverter work alternately
⎧
from stage 1 to stage 4, and S1 and S2 work in ZCS condition. In ⎨ i (t) = Ud − uC1 (0− ) sin vt
Figs. 2a, g, c and e, the equivalent circuits transfer positive L1
L 1 v0 (3)
charges and energy from power supply to load side via ⎩
uC1 (t) = Ud − [Ud − uC1 (0− )] cos vt
intermediate capacitor C1.
Stage1 [0, T/2] [refer to Fig. 2a]: The series resonance of L1 and C1
happens. S1 is turned on and S2 is off. F = 0 and R1 is parasitic
resistor. According to the equivalent circuit in Fig. 3a, the
differential equations are transformed to complex frequency
 
where v = v0 1 − (a/v0 )2 , v0 = 1/ L1 C1 , α = R1/2L1. R1 ≃ 0,
then α = 0, ω = ω0.
According to the expressions (3), the current iL1 is sinusoidal as
shown in Fig. 3c. At t = 1/4T, the current peak value iL1m can be

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 Stage 2 [T/2, T1/2] [refer to Fig. 2g]: The series resonance of L1 and
C1 has finished. All switches are turned off and F = 0. The output
current io freewheels through CL, LL and load.
Stage 3 [T1/2, t1] [refer to Fig. 2c]: The series resonance of C1, L2
and CL happens. S2 is turned on and S1 is off. F = 1 and R2 is
parasitic resistor. The output voltage uCL ranges from −Ud to Ud.
At the beginning of this stage, the initial voltage uC1 (t− ) is uC1m1.
According to the equivalent circuit in Fig. 3b, the equations just as
expressions (3) in stage 1 are given as follows
⎧  
⎪ uC1 (t− ) − uCL T
⎪
⎨ iL2 (t) = sin v t − 1
L2 v0 2
  (8)
⎪
⎪ T
⎩ uC (t) = uC + [uC (t− ) − uC ] cos v t − 1
1 L 1 L 2
 
where v = v0 1 − (a/v0 )2 , v0 = 1/ L2 C , α = R2/2L2. 1/(1/C1 +
1/CL) ≃ C1 = C. R2 = 0, then α = 0, ω = ω0.
The current iL2 is also sinusoidal and the current peak value iL2m
can be expressed as

C
iL2m = [uC1 (t− ) − uCL ] (9)
L2

where iL1m ≤ iL2m ≤ 3/2iL1m.

At t = T1/2 + T/2, the minimum value of uC1 (uC1m2) can be
calculated as

uC1m2 = 2uCL − uC1 (t− ) ≤ −Ud (10)

However, uC1 can be clamped to –Ud by the diode D1 at t = t1, and t1

can be derived as

T1 1 1+D
t1 = + arccos (11)
2 v D−3

where D = uCL /Ud . The energy Em2 stored in C1 can be expressed as

1
Em2 = C1 Ud2 (12)
2
Fig. 3 Equivalent circuits in the complex frequency domain and transient
The transient current iL2 (t1) can be calculated as
analysis of the CT-ZCS inverter
a Stage 1 (t ≤ T/2) 
b Stage 3 (T1/2 < t ≤ t1)  C
c Transient waveforms iL2 (t1 ) = 2 2Ud (Ud − uCL ) (13)
L2

expressed as Part of energy stored in L2 is transferred to load side and the partial
energy Em3 is derived as

C1
iL1m = [Ud − uC1 (0− )] (4) 4CDUd (Ud − uCL )
L1 Em3 = (14)
1 + sgn(F)D
At t = T/2, the maximum value of uC1 (uC1m1) can be expressed as
where sgn(.) is the signum function. At t = t1, iS2 decreases to zero.
uC1m1 = 2Ud − uC1 (0− ) (5) The average current IS2 through S2 is equal to IS1 based on charge
balance of C1.
Stage 4 [t1, T1] [refer to Fig. 2e]: The series resonance of C1, L2 and
The capacitor C1 can store maximum energy Em1 which is CL has finished. All switches are turned off. First, iL2 freewheels
calculated as through D1, and F = 1. The moment t2 that iL2 decreases to zero
can be calculated as
1
Em1 = C1 [2Ud − uC1 (0− )]2 (6) √
2 2 2(1 − D)
t2 = t1 + (15)
During the whole period T1, the average current through S1 (IS1 ) is v[1 + sgn(F)D]
equal to the average value of iL1 (IL1 ) which can be calculated as
Second, if t2 < T1, it has the same condition with Stage 2 when t2 ≤
2C1 [Ud − uC1 (0− )] t ≤ T1. However, if t2 ≥ T1, there is no final condition.
IL1 = (7) At t = T1, uC1 decreases to –Ud and the total energy (Em1–Em2 +
T1 Em3) is transferred from power supply to load side. Although

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uC1 (0 ) = 0 and uC1 (t ) = 2Ud at the beginning of first T1, there is
certainly uC1 (0 ) = −Ud and uC1 (t ) = 3Ud at the beginning of
each next T1. Finally, all stages mentioned above would be
repeated alternately in mode 1.

3.1.2 Mode 2 [uref , uCL − H] [refer to Figs. 2b, g, d and f]: In

this mode, the series resonance of L3 and C2 happens in stage 1,
and then the series resonance of C2, L4 and CL happens in stage 3.
Power devices S3, S4 and D2 of the CT-ZCS inverter work
alternately from stage 1 to stage 4 just as S1, S2 and D1 do,
respectively, in aforementioned mode 1. In Figs. 2b, g, d and f, the
equivalent circuits transfer negative charges and energy from
power supply to load side via intermediate capacitor C2. Due to
Fig. 4 Curve of D and f1
the negative charge transfer, F is substituted ‘–1’ for ‘1’ of mode
1. Considering the symmetry operation principle between modes 1
and 2, the resonant currents iL3 and iL4 , resonant voltage uC2 and
3.3 Parameter design guidelines
currents through S3, S4 and D2 are similar to the resonant currents
√
iL1 and iL1 , resonant voltage uC1 and currents iS1 , iS2 and iD1 in If the expected f is determined, the values of LC and f1 can also be
mode 1. fixed. According to the analysis mentioned above, the average
currents through semiconductors and average power are
3.1.3 Mode 3 [uCL − H ≤ uref ≤ uCL + H] [refer to Fig. 2g]: proportional to C, which will increase by decreasing L and
All switches are turned off and F = 0 just like stage 2 in increasing C. However, according to expressions (4) and √ (9),
 the
aforementioned mode 1 or 2. peak currents through semiconductors
√ are proportional to C and
It can be observed from Figs. 2 and 3c, the voltage stresses and inversely proportional to L, which means the peak currents will
current stress of switches S1, S2, S3 and S4 can be obtained directly as increase in the aforementioned situation. Therefore, considering
the current capacity of semiconductors and output power
⎧ maximisation, rational design of resonant parameters can make the
⎨ VS1 ,max = VS3 ,max = 2Ud , VS2 ,max = VS4 ,max = 3Ud
⎪
  inverter operate in optimal mode.
⎪ C C (16)
⎩ iS1 ,max = iS3 ,max = 2Ud , iS2 ,max = iS4 ,max = 3Ud
L L

The voltage stresses and current stress of diodes D1 and D2 can be 4 Modelling and control strategy
derived directly as
4.1 Time-charge discretisation
⎧
⎨ VD1 ,max = VD2 ,max = 4Ud
⎪
As for switching states, ‘1’ stands for ZCS turn-on and ‘0’ for

2C (17) turn-off. The relationship between switching symbol mapping and
⎪
⎩ iD1 ,max = iD2 ,max = 2Ud
L charge transfer is shown in Fig. 5, and F can be expressed as F =
(S12 + D1)−(S34 + D2). In the discrete time domain, the CT-ZCS
The resonance remains unaffected by the difference of power factor inverter transfers quantified charges Q(k) to CL in each T1, which
in stage 1. In stage 3, the load side can be treated as a constant results in voltage variation of CL. The total charges Q(k) includes
current source during each T1 with inductive load, and the vast inductor-transferring charges QL(k) and capacitor-transferring
majority of resonant current iL2 or iL4 flows into CL instead of the charges QC(k). They can be calculated as follows
equivalent constant current source, thus the resonance remains
unaffected with inductive load. It can also remain unaffected with ⎧
capacitive load because C is far less than the parallel capacitance ⎨ QC (k) = 4CUd
of capacitive load and CL. Hence, the ZCS operation remains 4C(1 − D) (19)
⎩ QL (k) =
uninfluenced by the difference of power factor, even under Ud [1 + sgn(F)D]
non-unity power factor.

3.2 ZCS operation limitation Time and charges can be quantified by taking T1 as the time-scale
unit and Q as the charge-scale unit. As the switching symbol
To ensure ZCS, iL2 must reset before next Stage 3. Thus the mapping shows in Fig. 5, the turn-off of S1 and S2 or S3 and S4 in
constraint is obtained as the CT-ZCS inverter correspond to that of S12 or S34 in the
√ DBHBI, while switching states of S1 and S2 or S3 and S4 changing
2 2(1 − D) 1 1+D f from 1 and 0 to 0 and 1 correspond to the turn-on of S12 or S34.
Dt = + arccos ≤ 2p (18)
[1 + sgn(F)D] v D−3 f1 Switching states of D1 and D2 in the CT-ZCS inverter correspond
to that of D1 and D2 in the DBHBI. When ignoring the
In Fig. 4, when D ranges from 0 to 1, the theoretical maximum of intermediate resonance for model reduction, the output
ZCS frequency f1 should be lower than f1min to achieve ZCS. characteristics of DBHBI-derived CT-ZCS inverter with hysteresis
Hence, there is no any practical limitation of D for actualising control can be analysed analogically by substituting one combined
ZCS as shown in Fig. 4 as long as f1 < f1min under ideal switch cell S12 or S34 for a set of separate soft-switching S1 and S2
conditions. Nonetheless, if resonant inductors mismatch between or S3 and S4. Either S12 and D1 or S34 and D2 operate during each
L1 and L2 or L3 and L4 is more than 25% or so and considering T1 when uCL , uref − H or uCL . uref + H. Hence, an equivalent
some measurement error for inductance, the series resonance DBHBI with HFPM can be obtained based on time-charge
cannot accomplish completely in stages 1 and 3, which will lead discretisation as shown in Fig. 6a. Furthermore, the higher
to the ZCS condition broken. To assure that series resonance and switching frequency of ZCS operation means the smaller scale
ZCS can be completed in stages 1 and 3, the optimal f1 should be interval of time-charge discretisation, and the operation
further lower than the theoretical maximum of ZCS frequency characteristics between the DBHBI-derived CT-ZCS inverter and
appropriately. DBHBI are more approximate.

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Fig. 5 Discretised charges and switching symbol mapping

4.2 Controller comparison Since the switching losses can be eliminated completely by
employing ZCS technology, the ZCS inverters permit higher
In Fig. 6b, GI(s) is the current regulator, GV(s) is the open-loop comparison frequency and m is permitted to approach 1.
voltage transfer function, and kuf and kif are the feedback One intersection point X1 exists on the two curves of GV( jω) and
coefficients of uCL and io, respectively. The outer-current loop −1/N1(A) when A = H under two-level hysteresis control. At the
achieves voltage pre-estimate which is used as the voltage reference. point X1, the curve of −1/N1(A) completes a transition from
Only when the stability of inner-voltage loop is considered but the unstable region to stable region along with the direction of
ripple of io with resistive load R is neglected, is the power supply of increasing A. Therefore, the non-linear system performs a stable
equivalent DBHBI a voltage pulse sequence with ±Ud and zero periodic motion containing an oscillation with constant amplitude
potential, hence the reduced-order small-signal state equations of H. Similarly, there are also one intersection point X2 and constant
equivalent DBHBI can be obtained as oscillation under three-level hysteresis control, but the output
⎛ ⎞ ⎛ ⎞ fluctuation of three-level hysteresis control is smaller than that of
  1
dîL (t) 1 two-level hysteresis control with the same H. However, there is no
− 
⎜ dt ⎟ ⎜ 0 L ⎟ intersection point on the curves of GV( jω) and −1/N3(A) under
⎜ ⎟ ⎜ ⎟ îL (t) + − L ûd (t)
⎝ dûC (t) ⎠ = ⎝ 1 1 ⎠ ûC (t) (20) three-level relay control, and −1/N3(A) is not surrounded by the
L − L 0 curve of GV( jω). The non-linear system is stable without constant
dt CL RCL
amplitude oscillation. Furthermore, the output voltage fluctuation
of three-level relay control is smaller than that of both hysteresis
Then the small-signal model of voltage loop can be derived as control.
R
GV (s) = (21)
RLCL s2 + sL + R 4.3 Current regulator design
GV(s) is linear transfer function of open-loop system whose poles are Through large-signal analysis under three-level relay control, uCL is
located in the left-half s plane. constrained near uref + H or uref−H as shown in Fig. 8. Since the
To analyse and contrast the control performance, N(A) adopts comparison frequency fs is much higher than the fundamental
three-level relay controller, two-level and three-level hysteresis frequency of uCL , the large-signal model of voltage loop is a stable
controllers with hysteresis band H, respectively. The amplitude non-linear system.
and phase curves are obtained as shown in Fig. 7. The reason why In Fig. 8b, uref (k−1), uref (k) and uref (k + 1) represent the voltage
three-level relay control is a specific hysteresis control is given as references of previous, current and next moments, respectively, and
follows k uCL l for average output voltage which k uCL l = uref − H. Assuming
⎡   ⎤ k uCL l has tracked uref (k−1)−H at (k−1)Ts, it will take one
   2 comparison period Ts to make k uCL l increase from uref (k−1)−H to
2Ud ⎣ mH 2 H ⎦
lim 1− + 1− uref (k)−H or from uref (k)−H to uref (k + 1)−H. When fs is high
m1 pA A A enough, the voltage closed-loop can be equivalent to a voltage
follower with the output lagging reference one Ts. Regarding inner
2Ud H loop as a one-order inertia link with the time constant Ts, there is
+j (m − 1) = N3 (A) (22)
p A2 Ks/(sTs + 1) where Ks = 1/kuf.

Fig. 6 Equivalent DBHBI system

a Equivalent DBHBI
b Control block diagram

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Fig. 7 Amplitude and phase curves of N(A) and GV(s)

To improve anti-disturbance performance, the system is changed where h is the logarithmic bandwidth of middle-frequency band
into a typical type-II system by designing current regulator with where the slope is −20 dB/dec. Moreover, the closed-loop transfer
amplitude-limited output. The current regulator is given as function is obtained as

k pi (ti s + 1) io (s) ti s + 1
GI∗ (s) = (23) = (26)
ti s iref (s) (LL Ts ti /Ks k pi )s + (LL ti /Ks k pi )s2 + kif ti s + kif
3

The open-loop transfer function of the whole system is shown as
(Ks kif k pi /LL ti )(ti s + 1)
G(s) =
s2 (sTs + 1)
Then the PI parameters can be calculated as follows
Generally, h ranges from 3 to 10. When h decreases, the
anti-disturbance performance will be enhanced. However, the
overshoot will increase. Furthermore, the recovery time will
(24) decrease first, and then increase in the aforementioned situation.
Considering various indicators of tracking and anti-disturbance
performance, it is better to fix h = 5.

ti = hTs 5 Simulation and experiment

(h + 1)LL (25)
k pi = To verify the validity and feasibility of theoretical analysis, a 35-V
2hkif Ks Ts 2-A prototype based on TMS320F28335 is constructed as shown

Fig. 8 Transient waveforms of uCL and its enlargement under three-level relay control
a Voltage uCL
b Partial enlargement

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 parameters of current regulator can be calculated and the
amplitude-limited output ranges from −1.2 to 1.2.

5.1 Simulation results

Fig. 10 shows the simulation results including resonant voltage,

resonant currents and driving signals. In Fig. 10a, iS1 and iS2
increase from zero slowly after S1 and S2 turn on, and they have
decayed to zero before S1 and S2 turn off. The switches S3 and S4
operate in the same ZCS condition. All switches are proved to be
ZCS turn-on and turn-off. Moreover, in charging state of C1, iL1 is
active, and in discharging state, iL2 is active as shown in Fig. 10b.
Fig. 10c shows the simulation waveforms of uCL and io at load
step change ranging from 20 to 40 Ω. Only when load changing,
Fig. 9 Prototype circuit of the proposed inverter does io have slight fluctuation and then restore quickly. It
demonstrates the whole system has a good anti-disturbance
performance.
in Fig. 9. Furthermore, the PSIM simulation and prototype When the load R is 40 Ω, compared with hysteresis control with
experiment are conducted. The main parameters are listed as m = 0.3H, the ripple of uCL and io is reduced effectively under
Table 1 in both simulation and experiment. When H is fixed as proposed control. Moreover, the total harmonic distortion (THD)
0.05, fs ranges from 10 to 50 kHz. In the case of LL = 5 mH and of io is decreased from 0.85 to 0.32%.
CL = 40 μF, fs is chosen as 15 and 20 kHz under three-level
hysteresis control and relay control, respectively. Then the optimal 5.2 Experimental results
control effect can be achieved. According to (25), the PI
The experimental waveforms of iS1 , iS2 and driving signals are shown
in Fig. 11a, which demonstrates S1 and S2 work in ZCS condition.
Since the operating principle is symmetrical, it can be ratiocinated
Table 1 Design specifications and circuit parameters all switches work in the same ZCS condition. The experimental
Item Symbol Value
waveforms of iL1 , iL2 and uC1 are shown in Fig. 11b. In charging
state of C1, iL1 is active, and in discharging state, iL2 is active.
DC input voltage 2Ud 120 V Moreover, uC1 ranges from −Ud to 3Ud.
output current io 1A When R = 40 Ω, the experimental waveforms of uCL , io and
output frequency fo 5–50 Hz driving signals are shown in Figs. 12a and b under three-level
resonant capacitors C1, C2 0.15 μF hysteresis control (m = 0.3) and relay control. The positive group
resonant inductors L1, L2, L3, L4 45 μH
filter capacitor CL 40 μF of the CT-ZCS inverter operates dominantly in the positive
smoothing inductor LL 5 mH half-cycle of io, and the negative group operates dominantly in the
current feedback coefficient kif 1 negative half-cycle. Figs. 12c and d provide transient current
voltage feedback coefficient kuf 0.02 tracking waveforms under both control strategies. The output
hysteresis band H 0.05
comparison frequency fs 10–50 kHz ripple is reduced availably under three-level relay control
compared with three-level hysteresis control, which can certify that

Fig. 10 Simulation waveforms of the CT-ZCS inverter system

a ZCS
b Resonant voltage and currents
c Dynamic responses at load step change

IET Power Electron., pp. 1–11

8 & The Institution of Engineering and Technology 2016
Fig. 11 Experimental waveforms of driving signals and resonance
a ZCS
b Resonance

the relay control has higher tracking accuracy. The output current and less output fluctuation can be acquired during each T1 because
demonstrates that effective harmonic reduction, decreasing from of the smaller resonant parameters. TMS320F28335 can process
2.335 to 1.66%, has been achieved. If the inverter operates at the generated comparison logic more timely and obtain higher
higher average switching frequency, the less transferred energy regulation accuracy of current tracking under three-level relay

Fig. 12 Experimental results under different control strategies

a Output waveforms under three-level hysteresis control
b Output waveforms under three-level relay control
c Transient current tracking under three-level hysteresis control
d Transient current tracking under three-level relay control
e THD of output current

IET Power Electron., pp. 1–11

& The Institution of Engineering and Technology 2016 9
Fig. 13 Dynamic responses and experimental efficiency of the proposed inverter
a Load step decrease
b Load step increase
c Experimental efficiency
control, thus the lower THD will be achieved. The THD of io with
different CL and LL under different control strategies is shown in
Fig. 12e. The PI parameters have been adjusted appropriately with
LL and fs to achieve optimal control according to expression (25).
The THD decreases as the CL or LL increases under both control
methods. Moreover, the THD is reduced availably by adopting
relay control with the same CL and LL, which validates the relay
control can permit smaller parameters and size of filter capacitor
and inductor than the hysteresis control, and minimise the size of
inverter further.
When the three-level relay control is adopted, Figs. 13a and b
show the experimental waveforms of uCL and io at load step
change mutating from 40 to 20 Ω and from 20 to 40 Ω. The slight
fluctuation of io validates the CT-ZCS inverter system has strong
robustness against the load mutation. The efficiency of CT-ZCS
inverter, flyback inverter [25], half-bridge inverter and DBHBI
[26] are shown in Fig. 13c. Although the efficiency of flyback
inverter is a little higher than that of CT-ZCS inverter at low
output power, the efficiency of flyback inverter is the lowest with
the increase of output power. It is mainly caused by isolation
transformer and full load-cycle operating mode in flyback inverter.
It can be observed from Fig. 13c that the CT-ZCS inverter
possesses higher efficiency than DBHBI and half-bridge inverter
by ZCS strategy. Moreover, it should be noted that the proposed
inverter system eliminates the contradiction between hysteresis
band and switching frequency existing in hard-switching inverters.
6 Conclusions
The validity and feasibility of proposed method are verified by
simulation and experiment. This paper has the following characteristics.
(i) A novel topology of ZCS inverter, which improves the
efficiency for low-power applications, is presented.
(ii) The reduced-order modelling method of time-charge
discretisation is applied in simplification of the inverter topology.
The simplification scheme provides some certain reference value
to the analysis of other complex topologies which the switches
work synergistically.
10
(iii) The three-level relay control with HFPM is implemented based
on the CT-ZCS inverter. Compared with three-level hysteresis
control, the recommended method achieves effective harmonic
reduction, reduces the size and improves power density.
(iv) The anti-disturbance performance is enhanced by designing the
current regulator.
Finally, the proposed modelling and control methods can be applied
to other ZCS inverters. To achieve optimal steady and transient
performance, the regulator parameters should be adjusted
appropriately with the circuit parameters and comparison frequency.
The proposed inverter can achieve ZCS operation by utilising series
resonance, but the voltage stress and current stress of power devices
increase to some degree. Further effort is needed to explore optimal
ZCS strategy with less voltage stress and current stress.
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