Advantx-E Operator Console Schematics SM 2123272-100 8

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GE MEDICAL SYSTEMS ADVANTX-E OPERATOR CONSOLE SCHEMATICS
REV 8 DIRECTION 2123272-100

IMPORTANT! . . . XĆRAY PROTECTION

XĆray equipment if not properly design compel the operator to take tion, and take adequate steps to
used may cause injury. AccordĆ adequate precautions to prevent protect against injury.
ingly, the instructions herein the possibility of any persons
contained should be thoroughly carelessly exposing themselves or The equipment is sold with the
read and understood by everyĆ others to radiation. understanding that the General
one who will use the equipment Electric Company, Medical SysĆ
before you attempt to place this tems Group, its agents, and
equipment in operation. The It is important that everyone having representatives have no responsiĆ
General Electric Company, MediĆ anything to do with xĆradiation be bility for injury or damage which
cal Systems Group, will be glad properly trained and fully acĆ may result from improper use of the
to assist and cooperate in placing quainted with the recommendaĆ equipment.
this equipment in use. tions of the National Council on Various protective material and
Radiation Protection and MeasureĆ devices are available. It is urged
Although this apparatus incorpoĆ ments as published in NCRP that such materials or devices be
rates a high degree of protection Reports available from NCRP PubliĆ used.
against xĆradiation other than the cations, 7910 Woodmont Avenue,
useful beam, no practical design of Room 1016, Bethesda, Maryland CAUTION: United States Federal
equipment can provide complete 20814, and of the International law restricts this device to use by or
protection. Nor can any practical Commission on Radiation ProtecĆ on the order of a physician.

iv
REV 8 DIRECTION 2123272-100
If you have any comments, suggestions or corrections to the information in this document,
please write them down, include the document title and document number, and send them to:
GENERAL ELECTRIC COMPANY MEDICAL SYSTEMS

MANAGER – INFORMATION INTEGRATION,
AMERICAS W–622
P.O. BOX 414
MILWAUKEE, WI 53201–0414
CERTIFIED ELECTRICAL CONTRACTOR STATEMENT

All electrical installations that are performed by qualified GE Medical requirements of the applicable elecĆ
preliminary to positioning of the personnel. The products involved trical codes.
equipment at the site prepared for (and the accompanying electrical
the equipment shall be performed by installations) are highly sophistiĆ
licensed electrical contractors. In cated, and special engineering The purchaser of GE equipment
addition, electrical feeds into the competence is required. In performĆ shall only utilize qualified personnel
Power Distribution Unit shall be ing all electrical work on these (i.e., GE's field engineers, personnel
performed by licensed electrical products, GE will use its own of thirdĆparty service companies with
contractors. Other connections beĆ specially trained field engineers. All equivalent training, or licensed elecĆ
tween pieces of electrical equipment, of GE's electrical work on these tricians) to perform electrical servicĆ
calibrations, and testing shall be products will comply with the ing on the equipment.
DAMAGE IN TRANSPORTATION
All packages should be closely upon discovery, or in any event, 8*285-3449 immediately after
examined at time of delivery. If within 14 days after receipt, and the damage is found. At this time be
damage is apparent, have notation contents and containers held for ready to supply name of carrier,
damage in shipment" written on inspection by the carrier. A transĆ delivery date, consignee name,
all copies of the freight or express portation company will not pay a freight or express bill number, item
bill before delivery is accepted or claim for damage if an inspection is damaged and extent of damage.
signed for" by a General Electric not requested within this 14 day
representative or a hospital receivĆ period. Complete instructions regarding
ing agent. Whether noted or claim procedure are found in
concealed, damage MUST be Call Traffic and Transportation, Section S" of the Policy &
reported to the carrier immediately Milwaukee, WI (414) 827-3449Ă/ Procedure Bulletins.
6/17/94
v

vi

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć1
Signal Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć2
SCC1 Advantx-E Console - Forward Production
2183000 & 2106684 & 2224559 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć1
SCC1 Advantx-E Console - Backward Compatible . . . . . 2183001 & 2121197 3Ć1
A1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-276309P1 & 2109380 4Ć1
A2 Control Bd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2106682-2 & 2106682 5Ć1
A3 Plasma Display . . . . . . . . . . . . . . . . . . . . . . . . . . . 2183003 & 46-276310P1 6Ć1
A1 Plasma Display Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . 46-276310P2 6Ć1
A4 Touch Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2183004 & 46-276290P1 7Ć1
A6 Handswitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-270800G4 8Ć1
A7 Console Fibre to Coax Arcnet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2120138 9Ć1
vii

viii

0 Jan. 27, 1995 Initial production release.
1 Feb. 15, 1995 Added schematic 2120138.
2 Mar. 24, 1995 Eliminated signal list and added wiring diagram.
3 Oct. 31, 1995 Revised fiber optic cable connection to system cabinet.
4 Dec. 6, 1996 Revised schematic 2121197SCH.
5 June 23, 1997 Added new console model numbers 2183000 and 2183001.
6 Sept. 2, 1997 Added schematic 2183000sch and 2183001sch.
7 Nov. 6, 1997 Added a third sheet to schematic 2121197SCH showing x-ray indicator button.
8 Nov. 12, 1998 Added schematic 2224559sch.

Title Page 8
i thru x 8
1-1 and 1-2 8
2-1 thru 2-8 8
3-1 thru 3-8 8
4-1 and 4-2 8
5-1 thru 5-16 8
6-1 and 6-2 8
7-1 and 7-2 8
8-1 and 8-2 8
9-1 thru 9-6 8
Back Page -
ix

x

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SCC1
ADVANTX II CONSOLE - FORWARD PRODUCTION
2106684
and
2183000

1 2
2183000SCH
SYSTEM CONNECTOR
CIRCUIT BREAKER
SCC1–J1 SCC1–CB1
120_VAC 26 BLK 1 120_VAC 120VAC_BREAKER 2 BLK
POWER SUPPLY CONSOLE CONTROL PWA

SCC1–A1 SCC1–A2
EMI LINE FILTER TB1–1 120VAC_FILTER (TB1–3) 12VP TB2–2 YEL J5–1
SCC1_FL1 12VP
TB1–3 120RTN_FILTER (TB1–2) 12VN TB2–4 BRN J5–2 12VN
1 120VAC_BREAKER 120VAC_FILTER 4 BLK
TB1–5 TB2–7 GRN J5–4
120_RTN 25 WHT 2 120_RTN CHASSIS_GND (TB1–1) LGND TB2–8 GRN J5–6
LGND
3 CHASSIS_GND 5 WHT LGND LGND
120RTN_FILTER TB2–9 RED J5–7
VCC VCC
VCC TB2–10 RED J5–8 VCC
TB2–6 GND HARNESS CHASSIS_GND
12VP (PWA MOUNTING SCREW)
GRN/YEL
GRN/YEL
CHASSIS_GND 42 GRN/YEL
CHASSIS_GND SHELL GRN/YEL

(CONNECTOR
MOUNTING
SCREW)
EL DISPLAY
SCC1–A3
GRN J2–3 LGND_DISPLAY
PUR J2–1 VCC_DISPLAY
GND HARNESS CHASSIS_GND

(ESD SHIELD)
SCC1–STUD2
SCC1–STUD1
/user/xr_pwa/console_ASM/documents/gems_engineering_docu.drw/2183000sch.doc 1 2
R. Cronce 10–JUL–1997 CONSOLE ASSEMBLY – TITAN VERSION
LOMBARDI
2183000SCH
1 2

2 –
2183000SCH
SYSTEM CONNECTOR CONSOLE CONTROL PWA HANDSWITCH CRADLE HANDSWITCH

SCC1–J1 SCC1–A2 SCC1–A6–A1 SCC1–A6
24VL 1 ORN J3–1 24VL 12VP J2–2 12VP 12VP J1–1 J1–1 12VP
VL_RTN_FRT 16 PUR J3–4 VL_RTN_FRT TRIAL J2–5 TRIAL TRIAL J1–2 J1–2 TRIAL
SYS_ON*_FRT 34 BLU J3–5 SYS_ON*_FRT PREP J2–3 PREP PREP J1–3 J1–3 PREP
VL_RTN_LAT 11 GRY J3–6 VL_RTN_LAT EXPOSE J2–4 EXPOSE EXPOSE J1–4 J1–4 EXPOSE
SYS_ON*_LAT 29 BRN J3–7 SYS_ON*_LAT LGND J2–6 C
LGND
RESET_SW_FRT 23 ORN J3–11 RESET_SW_FRT CRADLE* J2–7 NO
CRADLE*
RESET_SW_LAT 18 PUR J3–12 RESET_SW_LAT
FRT_EXPOSE 4 RED J3–13 FRT_EXPOSE GND_HARNESS CHASSIS_GND
FRT_PREP 19 YEL J3–14 FRT_PREP
FRT_24V 37 ORN J3–15 FRT_24V
LAT_EXPOSE 13 PUR J3–16 LAT_EXPOSE SCC1–STUD3 INFARED TOUCH FRAME
LAT_24V 31 BLU J3–17 LAT_24V SCC1–A4
LAT_PREP 20 GRY J3–18 LAT_PREP LGND J10–1 J5–1 LGND
RESET_P 12 BRN J3–19 RESET_P LGND J10–2 J5–2 LGND
RESET_N 30 RED J3–20 RESET_N TXDA* J10–3 J5–3 TXDA*
LGND J10–4 J5–4 LGND
RXDA* J10–5 J5–5 RXDA*
VCC_ISO J10–6 J5–6 VCC_ISO
CTSA* J10–7 J5–7 CTSA*
DTRA* J10–9 J5–9 DTRA*
FLAT CABLE
J8 GE_BUS_RXD
J6 GE_BUS_TXD
SYSTEM ON/STAND–BY
SWITCH/LAMP
SCC1–SW1
22 FIBER OPTIC ON_SWITCH J1–3 RED ON–POLE2–4 ON_SWITCH SW_TO_LMP ON–POLE1–4 BLU
GE_BUS_RXD J1–4 YEL ON–POLE2–3
VL_RTN_FRT VL_RTN_FRT
21 FIBER OPTIC J1–9 GRY ON–POLE1–3
GE_BUS_TXD 12VP_ISO 12VP_ISO
SYS_ON* J1–7 BLU ON–POLE1–A SYS_ON* SW_TO_LMP ON–POLE1–B
(THIS SWITCH IS LABELED
“ON” INSIDE OF CASE.)
SYSTEM RESET SWITCH

SCC1–SW2
AUDIO JACK J1–14 PUR OFF–3
RESET_SWITCH RESET_SWITCH
SCC1–J2 J1–13 ORN OFF–4
1 GRY J3–21 PEXT1 VL_RTN_FRT VL_RTN_FRT
PEXT1 (THIS SWITCH IS LABELED
PEXT2 2 BLU J3–22 PEXT2 “OFF” INSIDE OF CASE.)
XRAY ON LAMP
SCC1–IND1
12VP_ISO J1–10 BLK IND–B 12VP_ISO
XRAY_ON* J1–8 BRN IND–A XRAY_ON*
SELFTEST J1–26 J9–5 LGND (THIS SWITCH IS LABELED
LGND J1–3 J9–6 “IND” INSIDE OF CASE.)
LGND
VSYNC J1–24 J9–1 F_VSYNC
LGND J1–21 J9–2 LGND OPTICAL ENCODER
EL DISPLAY HSYNC J1–22 J9–3 F_HSYNC SCC1–V1
SCC1–A3 LGND J1–19 J9–4 LGND VCC J4–1 RED 1 VCC
D0 J1–2 J9–7 F_D0 CLAR_CHB J4–3 ORN 3 CLAR_CHB
LGND J1–5 J9–8 LGND CLAR_CHA J4–4 YEL 4 CLAR_CHA
D1 J1–4 J9–9 F_D1 LGND J4–5 GRN 5 LGND
PCLK J1–18 J9–11 F_PCLK
D2 J1–6
J1–8
D3
R. Cronce 10–July–1997 CONSOLE ASSEMBLY – TITAN VERSION
LOMBARDI
2183000SCH 2 –
2-6

1 2
2224559SCH
SYSTEM CONNECTOR
CIRCUIT BREAKER
SCC1-J1 SCC1-CB1

SCC1-A1 SCC1-A2
EMI LINE FILTER TB1-1 120VAC_FILTER(TB1-3) TB2-2 YEL J5-1
SCC1_FL1 12VP 12VP
TB1-3 120RTN_FILTER (TB1-2) 12VN TB2-4 BRN J5-2 12VN
TB1-5 LGND TB2-7 GRN J5-4 LGND
120_RTN 25 WHT 2 120_RTN CHASSIS_GND(TB1-1)
LGND TB2-8 GRN J5-6 LGND
3 CHASSIS_GND 120RTN_FILTER 5 WHT
VCC TB2-9 RED J5-7 VCC
VCC TB2-10 RED J5-8 VCC
TB2-6 GND HARNESS CHASSIS_GND
12VP (PWA MOUNTING SCREW)
GRN/YEL
GRN/YEL
CHASSIS_GND 42 GRN/YEL

(CONNECTOR
MOUNTING
SCREW)
EL DISPLAY
SCC1-A3
GRN J2-3 LGND_DISPLAY
GRN J2-2 LGND_DISPLAY
PUR J2-1 VCC_DISPLAY

(ESD SHIELD)
SCC1-STUD2
SCC1-STUD1
J. Dwyer 28–Sept–1998 CONSOLE ASSEMBLY - TITAN VERSION
EAGLE
2224559SCH
1 2
2-7

2 -
2224559SCH

SCC1-J1 SCC1-A2 SCC1-A6-A1 SCC1-A6
24VL 1 ORN J3-1 24VL 12VP J2-2 12VP 12VP J1-1 J1-1 12VP
VL_RTN_FRT 16 PUR J3-4 VL_RTN_FRT TRIAL J2-5 TRIAL TRIAL J1-2 J1-2 TRIAL
SYS_ON*_FRT 34 BLU J3-5 SYS_ON*_FRT PREP J2-3 PREP PREP J1-3 J1-3 PREP
VL_RTN_LAT 11 GRY J3-6 VL_RTN_LAT EXPOSE J2-4 EXPOSE EXPOSE J1-4 J1-4 EXPOSE
SYS_ON*_LAT 29 BRN J3-7 SYS_ON*_LAT LGND J2-6 C
LGND
RESET_SW_FRT 23 ORN J3-11 RESET_SW_FRT CRADLE* J2-7 NO
CRADLE*
RESET_SW_LAT 18 PUR J3-12 RESET_SW_LAT
FRT_EXPOSE 4 RED J3-13 FRT_EXPOSE GND_HARNESS CHASSIS_GND
FRT_PREP 19 YEL J3-14 FRT_PREP
FRT_24V 37 ORN J3-15 FRT_24V
LAT_EXPOSE 13 PUR J3-16 LAT_EXPOSE SCC1-STUD3 INFARED TOUCH FRAME
LAT_24V 31 BLU J3-17 LAT_24V SCC1-A4
LAT_PREP 20 GRY J3-18 LAT_PREP LGND J10-1 J5-1 LGND
RESET_P 12 BRN J3-19 RESET_P LGND J10-2 J5-2 LGND
RESET_N 30 RED J3-20 RESET_N TXDA* J10-3 J5-3 TXDA*
LGND J10-4 J5-4 LGND
RXDA* J10-5 J5-5 RXDA*
VCC_ISO J10-6 J5-6 VCC_ISO
CTSA* J10-7 J5-7 CTSA*
DTRA* J10-9 J5-9 DTRA*
FLAT CABLE
J8 GE_BUS_RXD
J6 GE_BUS_TXD
SYSTEM ON/STAND-BY
SWITCH/LAMP
SCC1-SW1
22 FIBER OPTIC ON_SWITCH J1-3 RED ON-POLE2-4 ON_SWITCH SW_TO_LMP ON-POLE1-4 BLU
GE_BUS_RXD J1-4 YEL ON-POLE2-3 VL_RTN_FRT
VL_RTN_FRT
21 FIBER OPTIC J1-9 GRY ON-POLE1-3 12VP_ISO
GE_BUS_TXD 12VP_ISO
SYS_ON* J1-7 BLU ON-POLE1-A SYS_ON* SW_TO_LMP ON-POLE1-B
"ON" INSIDE OF CASE.)
SYSTEM RESET SWITCH

SCC1-SW2
AUDIO JACK J1-14 PUR OFF-3
SCC1-J2 J1-13 ORN OFF-4
1 GRY J3-21 VL_RTN_FRT VL_RTN_FRT
PEXT1 PEXT1 (THIS SWITCH IS LABELED
PEXT2 2 BLU J3-22 PEXT2 "OFF" INSIDE OF CASE.)
XRAY ON LAMP
SCC1-IND1
12VP_ISO J1-10 BLK IND-B 12VP_ISO
XRAY_ON* J1-8 BRN IND-A XRAY_ON*
SELFTEST J1-26 J9-5 LGND (THIS SWITCH IS LABELED
LGND J1-3 J9-6 "IND" INSIDE OF CASE.)
LGND
VSYNC J1-24 J9-1 F_VSYNC
LGND J1-21 J9-2 LGND OPTICAL ENCODER
EL DISPLAY HSYNC J1-22 J9-3 F_HSYNC SCC1-V1
SCC1-A3 LGND J1-19 J9-4 LGND VCC J4-1 RED 1 VCC
D0 J1-2 J9-7 F_D0 CLAR_CHB J4-3 ORN 3 CLAR_CHB
LGND J1-5 J9-8 LGND CLAR_CHA J4-4 YEL 4 CLAR_CHA
D1 J1-4 J9-9 F_D1 LGND J4-5 GRN 5 LGND
PCLK J1-18 J9-11 F_PCLK
D2 J1-6
J1-8
D3
J. Dwyer 28–Sept–1998 CONSOLE ASSEMBLY - TITAN VERSION
EAGLE
2224559SCH 2 -
2-8

SCC1
ADVANTX II CONSOLE - BACKWARD COMPATIBLE
2121197
and
2183001

ALT.
ALT.
PUSH–ON
PUSH–OFF
– SW_TO_LAMP
SW_TO_LAMP BLU
+
MOMENTARY
N.O.
+
–

C123
+
R125 ON–POLE1–1 ON–POLE1–2

ALT.
ALT. Note: This sheet is a copy of

PUSH–ON
PUSH–OFF sheet 2 of 2121197SCH.
– SW_TO_LAMP ON–POLE1–4 BLU
The X–ray ON pushbuttons,
SW_TO_LAMP
+ components and wiring in
ON–POLE1–B
this dotted line box were
modified starting July 1997
to generate a system reset if
the console is turned OFF
N.O. MOMENTARY with system in STANDBY.
R124 RESET is bypassed if X–ray
OFF–2
ON pushbutton is held in
while console is turned OFF.
IND–1
IND–2
+
–

1 2
2183001SCH
SYSTEM CONNECTOR
CIRCUIT BREAKER
SCC1–J1 SCC1–CB1

SCC1–A1 SCC1–A2
EMI LINE FILTER TB1–1 120VAC_FILTER (TB1–3) 12VP TB2–2 YEL J5–1
SCC1_FL1 12VP
TB1–3 120RTN_FILTER (TB1–2) 12VN TB2–4 BRN J5–2 12VN
TB1–5 TB2–7 GRN J5–4
120_RTN 33 WHT 2 120_RTN CHASSIS_GND (TB1–1) LGND TB2–8 GRN J5–6
LGND
3 CHASSIS_GND 5 WHT LGND LGND
120RTN_FILTER TB2–9 RED J5–7
VCC VCC
VCC TB2–10 RED J5–8 VCC
12VP TB2–6 (PWA MOUNTING SCREW)
GRN/YEL
GRN/YEL
FIBER TO COAX ARCNET
SCC1–A7
12VN TB2–TERM–2 BRN J7–3
12VN
VCC TB2–TERM–5 RED J7–1
42 GRN/YEL VCC
CHASSIS_GND LGND TB2–TERM–4 GRN J7–2
LGND

(CONNECTOR
MOUNTING
SCREW)
EL DISPLAY
SCC1–A3
PUR J2–1 VCC_DISPLAY

(ESD SHIELD)
SCC1–STUD2
SCC1–STUD1
R. Cronce 10–July–1997 CONSOLE ASSEMBLY – BACKWARDS COMPATIBLE
LOMBARDI
2183001SCH 1 2

2 –
2183001SCH

SCC1–J1 SCC1–A2 SCC1–A6–A1 SCC1–A6
24VL 1 ORN J3–1 24VL 12VP J2–2 12VP 12VP J1–1 J1–1 12VP
VL_RTN_FRT 16 PUR J3–4 VL_RTN_FRT TRIAL J2–5 TRIAL TRIAL J1–2 J1–2 TRIAL
SYS_ON*_FRT 34 BLU J3–5 SYS_ON*_FRT PREP J2–3 PREP PREP J1–3 J1–3 PREP
VL_RTN_LAT 11 GRY J3–6 VL_RTN_LAT EXPOSE J2–4 EXPOSE EXPOSE J1–4 J1–4 EXPOSE
SYS_ON*_LAT 29 BRN J3–7 SYS_ON*_LAT LGND J2–6 C
LGND
RESET_SW_FRT 23 ORN J3–11 RESET_SW_FRT CRADLE* J2–7 NO
CRADLE*
RESET_SW_LAT 24 PUR J3–12 RESET_SW_LAT
FRT_EXPOSE 4 RED J3–13 FRT_EXPOSE GND_HARNESS CHASSIS_GND
FRT_PREP 19 YEL J3–14 FRT_PREP
FRT_24V 37 ORN J3–15 FRT_24V
LAT_EXPOSE 13 PUR J3–16 LAT_EXPOSE SCC1–STUD3 INFARED TOUCH FRAME
LAT_24V 31 BLU J3–17 LAT_24V SCC1–A4
LAT_PREP 20 GRY J3–18 LAT_PREP LGND J10–1 J5–1 LGND
RESET_P 21 BRN J3–19 RESET_P LGND J10–2 J5–2 LGND
RESET_N 22 RED J3–20 RESET_N TXDA* J10–3 J5–3 TXDA*
RXDA* J10–5 J5–5 RXDA*
CTSA* J10–7 J5–7 CTSA*
DTRA* J10–9 J5–9 DTRA*
FIBER TO COAX ARCNET
FLAT CABLE
SCC1–A7 C123
39–CENTER J5–CENTER U2 FIBER OPTIC J8
ARCNET_COAX ARCNET_COAXGE_BUS_RXD GE_BUS_RXD
39–SHELL J5–SHELL U1 FIBER OPTIC J6
ARCNET_SHLD ARCNET_SHLDGE_BUS_TXD GE_BUS_TXD R125
ON–POLE1–1 SYSTEM ON/STAND–BY ON–POLE1–2
SWITCH/LAMP
SCC1–SW1
ON_SWITCH J1–3 RED ON–POLE2–4 ON_SWITCH SW_TO_LMP ON–POLE1–4 BLU
VL_RTN_FRT J1–4 YEL ON–POLE2–3 VL_RTN_FRT
12VP_ISO J1–9 GRY ON–POLE1–3 12VP_ISO
SYS_ON* J1–7 BLU ON–POLE1–A SYS_ON* SW_TO_LMP ON–POLE1–B
“ON” INSIDE OF CASE.)
SYSTEM RESET SWITCH

SCC1–SW2
AUDIO JACK J1–14 PUR OFF–3
SCC1–J2 J1–13 ORN R124 OFF–4
1 GRY J3–21 PEXT1 VL_RTN_FRT VL_RTN_FRT
PEXT1 OFF–2 (THIS SWITCH IS LABELED
PEXT2 2 BLU J3–22 PEXT2 “OFF” INSIDE OF CASE.)
IND–1 XRAY ON LAMP IND–2

SCC1–IND1
12VP_ISO J1–10 BLK IND–B 12VP_ISO
XRAY_ON* J1–8 BRN IND–A XRAY_ON*
SELFTEST J1–26 J9–5 LGND (THIS SWITCH IS LABELED
J1–3 J9–6 LGND “IND” INSIDE OF CASE.)
LGND
VSYNC J1–24 J9–1 F_VSYNC

LGND J1–21 J9–2 LGND OPTICAL ENCODER
EL DISPLAY HSYNC J1–22 J9–3 F_HSYNC SCC1–V1
SCC1–A3 LGND J1–19 J9–4 LGND VCC J4–1 RED 1 VCC
D0 J1–2 J9–7 F_D0 CLAR_CHB J4–3 ORN 3 CLAR_CHB
LGND J1–5 J9–8 LGND CLAR_CHA J4–4 YEL 4 CLAR_CHA
D1 J1–4 J9–9 F_D1 LGND J4–5 GRN 5 LGND
PCLK J1–18 J9–11 F_PCLK
D2 J1–6
J1–8
D3
R. Cronce 10–July–1997 CONSOLE ASSEMBLY – BACKWARDS COMPATIBLE
LOMBARDI
2183001SCH 2 –


SCC1 A1
POWER SUPPLY
2109380
and
46-276309P1
NOTE: Schematic not available.

SCC1 A2
CONTROL BOARD
2106682sch
and
2106682-2

1 2 3 4 5 6 7 8 9 10 SHT. 1 CONT. 2
2106682SCH
A A
SHT NOTE: ANY CHANGE TO THIS PWB EFFECTING ITS 21XXXXX#, G# or REV#
SHEET_NAME REV
NUM MUST BE ACCOMPANIED BY A CORRESPONDING CHANGE IN THE
B BOARD_ID PROGRAMMING CONTAINED WITH U38. SEE SHEET 7. B
COVER_SHEET 1 2
BLOCK_DIAGRAM 2 0
SIGN
CPU_CONTROL 3 0 REVISION PCN NUMBER DATE
OFF
CPU_80C186 4 0
A –––––– 14–MAR–94 SAB
MEMORY_IF 5 0
0 –––––– 1–SEP–94 SAB
IO_IF 6 0
1 196437 16APR96 JWW
ARCNET_RS232_IF 7 0
2 196966 11NOV96
C SWITCH_RELAY_IF 8 0 C
ENCODER_PIEZO_IF 9 0
PLASMA_DISPLAY_IF 10 0
DISPLAY_CONTROL 11 2
VIDEO_MEMORY 12 0
DISPLAY_DRIVE 13 0
POWER_DECOUPLING 14 0
D D
NOTES:
1.THE GROUP NUMBER AND GROUP REVISION
FOR THIS PWA IS 2106682 E.
E 2.THIS SCHEMATIC MEETS THE SPECIFICA– E
TIONS OF GE SCHEMATIC STANDARDS
46–017486.
3.UNLESS OTHERWISE SPECIFIED:
RESISTORS ARE IN OHMS, 0.1W, 1%.
CAPACITORS ARE IN FARADS.
INDUCTORS ARE IN HENRIES.
F 4.ACTIVE LOW SIGNALS ARE INDICATED F
WITH ”*” AFTER THE SIGNAL NAME
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/cover_sheet BLOCK SHT 1 OF 1 H

REV 1 PCN 196437 DESCRIPTION MADE Scott Bielski DATE 1–SEP–94 DESIGN TITLE ADVANTX–II_CONSOLE_CONTROL_PWA
MADE BY Glenn Teske DATE 16APR96 APPR BY JWW DATE 22APR96 CHECK DATE GE MEDICAL SYSTEMS FIRST MADE FOR ADVANTX–II_CONSOLE_ASM
REV 2 PCN 196966 DESCRIPTION APPR Scott Bielski DATE 14SEP94 Milwaukee, WI USA DRAWING NO. REV SIZE SHT./CONT. ON
MADE BY Glenn Teske DATE 11NOV96 APPR BY DATE OTHER Potter–Hummer DATE 14SEP94 2106682SCH 2 B 1/2
1 2 3 4 5 6 7 8 9 10 11

1 2 3 4 5 6 7 8 9 10 SHT. 2 CONT. 3
2106682SCH
A A
ARCNET_RS232_IF
CHIP_SELECTS(10:0)
MISC_IO(8:0)
RES_CONTROL(9:0)
RES_ADDRESS(20:0)
B RES_DATA(15:0) B
INTERRUPTS(3:0)
RESETS(4:0)
CPU_CONTROL SHEET 7
CHIP_SELECTS(10:0)
C CHIP_SELECTS(10:0) C
RES_CONTROL(9:0)
MISC_IO(8:0) RES_CONTROL(9:0)
RES_ADDRESS(20:0)
INTERRUPTS(3:0) RES_ADDRESS(20:0)
RES_DATA(15:0)
RES_DATA(15:0)
RESETS(4:0)
SHEETS 3–6
RESETS(4:0)
D D
INTERRUPTS(3:0)
MISC_IO(8:0)
E E
VCC SWITCH_RELAY_IF ENCODER_PIEZO_IF PLASMA_DISPLAY_IF

POWER_DECOUPLING
CHIP_SELECTS(10:0) CHIP_SELECTS(10:0)
VCC 12VP
RES_CONTROL(9:0) RES_CONTROL(9:0)
MISC_IO(8:0) MISC_IO(8:0) MISC_IO(8:0)
12VP LED5V RES_ADDRESS(20:0) RES_ADDRESS(20:0)
RES_DATA(15:0) RES_DATA(15:0) RES_DATA(15:0)

LED5V
INTERRUPTS(3:0) INTERRUPTS(3:0)
F LGND RESETS(4:0) RESETS(4:0) F
L
SHEET 8 SHEET 9 SHEETS 10–13
12VN
SHEET 14
12VN
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa BLOCK SHT 1 OF 1 H

REV 1 PCN DESCRIPTION MADE Scott Bielski DATE 1–SEP–94 D E S I G N T I T L E ADVANTX–II_CONSOLE_CONTROL_PWA
MADE BY DATE APPR BY DATE CHECK Jim Woods DATE 1–SEP–94 GE MEDICAL SYSTEMS F I R S T M A D E F O R ADVANTX–II_CONSOLE_ASM
REV 2 PCN DESCRIPTION APPR Scott Bielski DATE 1–SEP–94 Milwaukee, WI USA DRAWING NO. REV SIZE SHT./CONT. ON
MADE BY DATE APPR BY DATE OTHER Potter–Hummer DATE 1–SEP–94 2106682SCH 0 B 2 /3
1 2 3 4 5 6 7 8 9 10 11

1 2 3 4 5 6 7 8 9 10 SHT. 3 CONT. 4
2106682SCH
A A
MISC_IO(8:0)
MEMORY_IF
CPU_STATUS(3:0)
B B
CHIP_SELECTS(10:0)
RES_CONTROL(9:0)
RES_ADDRESS(20:0) IO_IF
RES_DATA(15:0)
RESETS(4:0)
SHEET 5 MISC_IO(8:0)
C RESETS(4:0) C
RES_DATA(15:0)
CPU_80C186
CPU_STATUS(3:0) SHEET 6
CHIP_SELECTS(10:0)
CHIP_SELECTS(10:0)
RESETS(4:0)
RESETS(4:0)
D RES_CONTROL(9:0) D
RES_CONTROL(9:0)
RES_ADDRESS(20:0)
RES_ADDRESS(20:0)
INTERRUPTS(3:0)
INTERRUPTS(3:0)
RES_DATA(15:0)
RES_DATA(15:0)
E SHEET 4 E
F F
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/cpu_control BLOCK SHT 1 OF 1 H

1 2 3 4 5 6 7 8 9 10 11

1 2 3 4 5 6 7 8 9 10 SHT. 4 CONT. 5
2106682SCH
CHIP_SELECTS(10:0)
A 7 PCS5* PCS4* 6 A
INTERRUPTS(3:0) 8 PCS6* PCS3* 5
9 MCS0* PCS2* 4 RES_CONTROL(9:0)
10 MCS1* PCS1* 3
PCS0* 2
UCS* 1 U22
LCS* 0 SN74ABT841_UTF
35
36
37
38
32
31
30
29
28
27
25
34
33
VCC 0 2 1D 1Q 23 RADDR0 0
MCS3
MCS2
MCS1
MCS0
PCS6/A2
PCS5/A1
PCS4
PCS3
PCS2
PCS1
PCS0
UCS
LCS
VCC 1 3 2D 2Q 22 1
2 4 3D 3Q 21 2
3 5 4D 4Q 20 3
4 6 5D 5Q 19 4
0 52 S0 5 7 6D 6Q 18 5
1 53 6 8 17 6
R48 Y2 S1 7D 7Q
2K 8 2 54 S2 AD0 17 AD0 0 7 9 8D 8Q 16 7
B VCC AD1 15 1 8 10 9D 9Q 15 8 B
OSC_TRI–S 20 TMRIN0 AD2 13 2 9 11 10D 10Q 14 RADDR9 9
1 OE OUT 5
CPU_CLK 22 TMROUT0 AD3 11 3
AD4 8 4 1 OC
16.000MHz RALE
21 TMRIN1 AD5 6 5 1 13 C
GND 23 4 6
TMROUT1 AD6
4 AD7 2 7
18 DRQ0 AD8 16 8 U23
19 DRQ1 U24 AD9 14 9 SN74ABT841_UTF
L L N80C186XL_UTF 12 10
AD10
AD11 10 11 10 2 1D 1Q 23 RADDR10 10
0 VSYNC_INT 45 INT0 AD12 7 12 11 3 2D 2Q 22 11
1 DUART_INT 44 5 13 12 4 21 12
INT1 AD13 3D 3Q
2 ENCODER_INT 42 INT2/INTA0– AD14 3 14 13 5 4D 4Q 20 13
3 ARC_INT 41 INT3/INTA1– AD15 1 AD15 15 14 6 5D 5Q 19 14
C NMI 46 15 7 18 15 C
NMI 6D 6Q
A16/S3 68 A16_S3 1 6 16 8 7D 7Q 17 16
ADDR_DATA(19:0)
59 X1 A17/S4 67 A17_S4 1 7 17 9 8D 8Q 16 17
58 X2 A18/S5 66 A18_S5 1 8 18 10 9D 9Q 15 RADDR18 18
A19/S6 65 A19_S6 1 9 11 10D 10Q 14 RBHE* 20
57
R36 RESET
100 24 RES 1 OC
56 CLKOUT 13 C RES_ADDRESS(20:0)
1 RALE
BHE–/S7
DT/R–
LOCK
SRDY
ARDY
TEST
HOLD
HLDA
L
DEN
ALE
R44
WR
RD
100
39
48
40
61
63
62
64
49
55
47
50
51
L
CPU_HOLD 7
D BHE* D
CPU_ARDY
VCC
RES_DATA(15:0)
L
R35
R34
2K
3 DT_R 100
L U20
U21 74ABT16245–1
RESETS(4:0) 74ALS244A 3 RDTR* 1 DIR1
1 _1G RRD* 5 24 DIR2
3 4 0 1 19 RWR* 4 RDEN* 48
SELF_RST VCC _2G _G1
RALE 1 25
E VCC
2 18
_G2 E
1A1 1Y1
R28 4 16 RDEN* 2 0 47 2 RDAT0 0
R29 6
1A2 1Y2
14 1 46
1A1 1Y1
3 1
2K 1A3 1Y3 1A2 1Y2
8 12 2 44 5 2
R26 4.75K
CLKOUT
1A4 1Y4 R41 RCLK 0
1A3 1Y3
4.75K 11 2A1 2Y1 9 3 43 1A4 1Y4 6 3
U11 13 2A2 2Y2 7 33.2 4 41 2A1 2Y1 8 4
LTC1232 15 5 LWR* 8 5 40 9 5
PB_SYS_RST* 2A3 2Y3 2A2 2Y2
1 _PBRST _RST 6 PWA_RST* 17 2A4 2Y4 3 LRD* 9 6 38 2A3 2Y3 11 6
2 TD 7 37 2A4 2Y4 12 7
3 5 PWA_RST 8 36 13 8
TOL RST 3A1 3Y1
2 C 7 9 35 14 9
_ST 3A2 3Y2
S3 L 10 33 16 10
3A3 3Y3
PUSHSW B Q1 11 32 3A4 3Y4 17 11
MMBT3904L TOL_10 12 30 19 12
C40 4A1 4Y1
F 1
VCC 13 29 4A2 4Y2 20 13 F
E 14 27 22 14
RESET R27 0.01U 4A3 4Y3
4.75K R31 15 26 4A4 4Y4 23 RDAT15 15
2K
L
CPU_STATUS(3:0)
L L
WATCH_DOG 6
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/cpu_control/cpu_80c186 BLOCK SHT 1 OF 1 H

1 2 3 4 5 6 7 8 9 10 11

1 2 3 4 5 6 7 8 9 10 SHT. 5 CONT. 6
2106682SCH
RES_DATA(15:0)
A RES_ADDRESS(20:0) A
U14
U26 HM628128LP–8
27/28/29X010–120
1 RADDR1 1 2 A0
1 RADDR1 1 2 A0 2 11 A1
2 11 A1 3 10 A2
3 10 A2 4 9 A3
4 9 A3 5 8 A4 IO0 13 RDAT0 0
5 8 A4 DQ0 13 RDAT0 0 6 7 A5 IO1 14 1
6 7 A5 DQ1 14 1 7 6 A6 IO2 15 2
7 6 A6 DQ2 15 2 VCC 8 5 A7 IO3 17 3
8 5 17 3 1 9 27 18 4
A7 DQ3 A8 IO4
9 27 A8 DQ4 18 4 10 26 A9 IO5 19 5
VCC 10 26 A9 DQ5 19 5 11 23 A10 IO6 20 6
11 23 A10 DQ6 20 6
Positions U26 and U27 accommodate 12 25 A11 IO7 21 RDAT7 7
B 12 25 A11 DQ7 21 RDAT7 7
R33 13 4 A12 B
13 4 A12 either 27C010 EPROMS, or 28F010/29F010 2K 14 28 A13
14 28 A13 15 3 A14
15 29 type FLASH EEPROMS. See BOM for 16 31
R42 RADDR16
A14 A15
2K 16 3 A15 17 RADDR17 2 A16
17 RADDR17 2 A16 exact component installed onto PWA.
NC/GND 30 29 WE
1 VPP/N C 22 CS1
EEWRLO* 3 1 PGM/W E 30 CS2
UCS* 22 CE 24 OE
LRD* 24 OE
2116931
C U15 C
HM628128LP–8
U27
27/28/29X010–120 1 RADDR1 1 2 A0
2 11 A1
1 RADDR1 1 2 A0 1 3 10 A2
2 11 A1 4 9 A3
3 10 A2 5 8 A4 IO0 13 RDAT8 8
4 9 A3 6 7 A5 IO1 14 9
5 8 A4 DQ0 13 RDAT8 8 7 6 A6 IO2 15 10
6 7 A5 DQ1 14 9 8 5 A7 IO3 17 11
7 6 A6 DQ2 15 10 9 27 A8 IO4 18 12
8 5 A7 DQ3 17 11 10 26 A9 IO5 19 13
9 27 A8 DQ4 18 12 11 23 A10 IO6 20 14
10 26 A9 DQ5 19 13 12 25 A11 IO7 21 RDAT15 15
11 23 A10 DQ6 20 14 13 4 A12
12 25 A11 DQ7 21 RDAT15 15 14 28 A13
D 13 4 A12 15 3 A14 D
14 28 A13 16 31 A15
15 29 A14 17 RADDR17 2 A16
16 RADDR16 3 A15
17 RADDR17 2 29
A16
30
R43 LCS* 22
WE
NC/GND CS1
1 VPP/N C 100 30 CS2
EEWRHI* 31 PGM/W E
L RRD* 24 OE
UCS* 22 CE
LRD* 24 OE
2116931
E E
U19
PAL22V10–15_UTF
CPU_STATUS(3:0)
3 DT_R 3 IN I/O 27 RAMWRLO*
0 S0* 4 IN I/O 26 RAMWRHI*
1 S1* 5 IN I/O 25 EEWRLO*
2 S2* 6 IN I/O 24 EEWRHI*
0 RADDR0 7 IN I/O 23
20 RBHE* 9 IN I/O 21
0 LCS* 10 IN I/O 20 LED5V
1 UCS* 11 IN I/O 19 DTR_DELAYED HALT DS9
4 RWR* 12 IN I/O 18 RDTR*
0 PWA_RST* 13 IN I/O 17 HALT*
MPAL_OE1 6
VCC IN
F 555–3007 F
RESETS(4:0) 2 RED
R40 IN/CK
2K
0 RCLK 2106792
9 3 5
RES_CONTROL(9:0)
1 0
CHIP_SELECTS(10:0)
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/cpu_control/memory_if BLOCK SHT 1 OF 1 H

1 2 3 4 5 6 7 8 9 10 11

1 2 3 4 5 6 7 8 9 10 SHT. 6 CONT. 7
2106682SCH
VCC
A A
U9
16 16 16 16 16 16 16 16 R19 74HC244
10K 1
S2 _1G
180H *
DIPSW8 19 _2G
1 2 3 4 8 7 6 5
1 16 8 1A1 1Y1 12 RDAT0 0 LED5V
13 1A2 1Y2 7 1
2 15 4 1A3 1Y3 16 2 * I/O ADDRESS DIAGNOSTIC STATUS
17 3 3
1A4 1Y4 *
L 3 14 2 2A1 2Y1 18 4 182H
15 2A2 2Y2 5 5
4 13 6 2A3 2Y3 14 6 U10 DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8
DIAGNOSTIC 11 2A4 2Y4 9 RDAT7 7 74HCT273 555–3007
5 12 PWA_RST* 1 RED RED RED RED RED RED RED RED
_CLR
B CONFIG 11 CLK B
6 11
0 RDAT0 1 8 1 D 1 Q 1 9
7 10 1 4 2D 2Q 5
2 14 3D 3Q 15
8 9 3 8 4D 4Q 9
4 13 5D 5Q 12
5 7 6D 6Q 6
VCC 6 17 7D 7Q 16
7 RDAT7 3 8D 8Q 2
U8 VCC
16 16 16 16 16 16 16 R19 74HC244
10K 1
C S1 _1G
1 8 1 H* C
19 _2G
DIPSW8
15 14 13 12 11 10 9
1 16 2 18 RDAT8 8 16
1A1 1Y1
4 1A2 1Y2 16 9 0 1
2 15 6 1A3 1Y3 14 10 1 2
8 1A4 1Y4 12 11 2 3
L 3 14 11 2A1 2Y1 9 12 3 4
13 2A2 2Y2 7 13 4 5
4 13 15 2A3 2Y3 5 14 5 6
17 3 RDAT15 15 6 7
ARCNET 5 12
2A4 2Y4
7 8
R54
8 9
NODE I.D. 6 11 9 10
10K
2%
VCC 10 11 0.08W
CPU DATA BUS PULL–UP TERMINATION
7 10 11 12
12 13
D 8 9
R18 13 14 D
10K 14 15
15 VCC
RES_DATA(15:0)
R50
10K
RESETS(4:0) 0
7 DIP_SW_RD*
E E
8 LED_WR*
MISC_IO(8:0)
F F
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/cpu_control/io_if BLOCK SHT 1 OF 1 H

1 2 3 4 5 6 7 8 9 10 11

1 2 3 4 5 6 7 8 9 10 SHT. 7 CONT. 8
2106682SCH
CR12
BAV70
U18 2
SN75454B
1 A1 _Y1 3 3
A RES_ADDRESS(20:0) U17 2 B1 A
6 A2 _Y2 5 1
COM20020
R37 7 B2 J6
100 HFBR1527
1 1 A0_MUX 1 AN
2 2 A1
RES_DATA(15:0) 3 3 A2_ALE
2 CAT
0 4
1 5
AD0
L L
A
2 6
AD1 R38 R39 F
AD2 VCC 82.5
1%
82.5
1%
VCC R
3 8 18 PULSE1* 0.500W 0.500W I
4 9
D3 _PULSE1
19 PULSE2*
C
RESETS(4:0) 5 10
D4 _PULSE2 B
6 11
D5
21
N
B 7 12
D6 _TXEN R30 C46 R B
RES_CONTROL(9:0) D7
24
1K
1%
E
0 PWA_RST* 23
_INTR
0.25W
0.1U 4 3 E
5 RRD* 27
_RST 50V
GND RL VCC
T
RWR*
_RD_DS U16
4 26 _WR–DIR 74HCT14 2
2 PCS0* 25 _CS U16 DATA_OUT 2 1
74HCT14
16 1 VO
VCC XTAL1
17 XTAL2 3 4 ARC_INT HFBR2521
20 RXIN
L J8
Y1 8
VCC
VCC
C R32 1 OE
OSC_TRI–S
ARCNET_CLK
3 INTERRUPTS(3:0) C
OUT 5
2K 20.000MHz VCC 1
GND VCC
4
R62 SERIAL_DATA U38
PCF8582E2N
2K
5 VCC
L SCLK R57 6
SDA
SCL
8
100
C 1
VDD
7
R60 J10 6 T
A0 PTC VCC
2
VCC R61 B Q3 3
A1 2K
FB3 J10 8 O I
A2 12VP
MMBT3904L 4 U29 1 2
10K VSS
SN75C1154 J10 10 U N
U31 R66 L
E 1
Y3 8 SCC2692
10 K VDD
RXDA* C T
VCC J10 5
D VCC 1 PWA_RST 38 RESET OP0 32 RXDA 19 _1RY 1RA 2
H E D
37 14 TXDA 18 3 TXDA*
R56 1 OE
OSC_TRI–S
DUART_CLK
X2 OP1
L
1DA _1DY J10 3
OUT 5 36 X1_CLK OP2 31 17 _2RY 2RA 4
R
15 DTRA 16 5 CTSA*
2K 3.6864MHz
1 2
OP3
30 RXDB 15
2DA _2DY
6
J10 7 S
GND 2 4
A0 OP4
16 TXDB 14
_3RY 3RA
7 DTRA* F
4 3 6
A1 OP5
29 13
3DA _3DY
8
J10 9 C
4 7
A2 OP6
17 DTRB 12
_4RY 4RA
9
A
A3 OP7 4DA _4DY R
L 0 28 35 10
J10 1 C
1 18
D0 RXDA
33
VSS E
2 27
D1 TXDA
L
J10 2 E
3 19
D2
11
E
D3 RXDB 12VN J10 4
4 26 13
E 5 20
D4 TXDB N E
D5
6 25 D6 IP0 8 CTSA
7 21 D7 IP1 5 CTSB
IP2 40 CRADLE_IN* 1
7 PCS5* 3 SYS_ON_UP 0
IP3 1 J7 6
CHIP_SELECTS(10:0) 39 43 TRIAL_POS 2
_CEN IP4 VCC
8 LWR* 9 42 DONE 6
9 LRD* 10
_WRN IP5
41
U16
FB2 J7 8 R
_RDN IP6 74HCT14
24 1 2
_INTRN
5 6 DUART_INT J7 10 S
RXDB* S 2
J7 5
TXDB* P 3
VCC J7 3
F A 2 F
CTSB*
MISC_IO(8:0) J7 7
DTRB* R
J7 9 P
R51 E
O
4.75K J7 1
R
J7 2
1 FB2 is not installed on L
T
J7 4
G1 assembly.
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/arcnet_rs232_if BLOCK SHT 1 OF 1 H

1 2 3 4 5 6 7 8 9 10 11

1 2 3 4 5 6 7 8 9 10 SHT. 8 CONT. 9
2106682SCH
MISC_IO(8:0)
3 PB_SYS_RST* 0 1 2
A A
4
U4 U7 U7 VCC
RESETS(4:0) 74HCT273 U2
0 12VP 74HC14 74HC14
PWA_RST* 1 _CLR
RELAY_WR* 11 CLK
184H ULN2003A 3 4 9 8 CRADLE_IN*
PWR 9
0 RDAT0 4 1D 1Q 5 1 I1 O1 16 FRONTAL_EN* 0 RELAY_DRIVE(3:0) R21
1 18 2D 2Q 19 2 I2 O2 15 LATERAL_EN* 1
U5 4.75K U7
2 3 3D 3Q 2 3 I3 O3 14 TRIAL_EN* 2 MCT6 74HC14
3 17 16 4 13 24V_CNTL
4 14
4D 4Q
15 5
I4 O4
12 SPARE*
R 2 0 TRIAL_AN 1 AN COL 7 1 2 TRIAL_POS
5D 5Q I5 O5
5 RDAT5 7 6D 6Q 6 6 I6 O6 11 XRAY_ON* 1.21K
6 13 7D 7Q 12 7 I7 O7 10 SYS_ON* 1%
7 RDAT7 8 8D 8Q 9 8 GND 0.25W 2 8
CAT EMIT
RES_DATA(15:0) VCC VCC
L
B R68 B
Pull–Up on sheet 4.
100 L
SYS_ON_UP R3 12VP
4.75K
K6
U5 RELAY_2P
MCT6 U7 U7 CRADLE*
VCC 12VDC
RESET_P R23 R22 4 AN COL 6
74HC14 74HC14
9
J3 19
5 6 STANDBY 1 1 10 C6 C9
1.21K 1.21K R6
1% 1%
0.25W 0.25W 3 5 4.75K 16 11
0.001U 0.1U
CAT EMIT C13 13
C25 50V 25V
10% 10%
J3 2
L PMLL4150 8
C 0.1U
0.1U L CR10 1
J3 3 C
25V L
1 FB1 not installed J3 8
RESET_N 10% J3 9
6
J3 20
4
on G1 assembly. J3 10
2 TRIAL_EN*
SYSTEM_UP K2 FB1
RELAY_2P 1 2
RESET_SW_FRT J3 23
12VP 12VDC
J3 11
9 L
RESET_SW_LAT J3 24
J3 12 J3 25
K5 J3 26
16 11
RELAY_2P J1 12
13
C4
24VDC PMLL4150
J1 11 LAT_24V
9
0.001U 1 CR3 8
J3 17
50V LATERAL_EN* 1
D J3 1
24VL RESET_SWITCH
J1 14
10% D
16 11 6
LAT_24V VL_RTN_FRT L
13 4
J1 13
PMLL4 150
CR6 8
1 J2
12VP
K3 CR11
1 RELAY_2P LAT_PREP
6
FRT_24V 2 J3 18
4 12VDC
3
9 PMLL4150
R2 4 TRIAL
0 5
VL_RTN_LAT 6 CR7
16 11
J3 6 J1 10 7 LAT_EXPOSE
13
E SYS_ON*_LAT J1 9 8
PMLL4150
J3 16 E
J3 7 G1
XRAY_ON* G2 CR4 8 PMLL4150
VL_RTN_FRT 1
J3 4 J1 8
L Jack L
SYS_ON*_FRT SYS_ON* Top_Entry
CR9
6
J3 5 J1 7 8–Pos EXPOSE FRT_EXPOSE
L 4
K4 J3 13
RELAY_2P PREP
24VDC
J1 6 SHIELDED PMLL4150
9 PHONE JACK K1
U1 J1 5 RELAY_2P CR8
MCT2201 C5 C7 C8 FRT_PREP
12VDC
J3 14
1 A C 5 16 11 0.001U 0.001U 0.001U 9
13 VL_RTN_FRT
C21 J1 4 50V 50V 50V PMLL4150
F PMLL4 150
ON_SWITCH
10% 10% 10% F
0.001U 2 K B E 4 CR5 8 16 11
J1 3
50V 1 13
10% 6 L PMLL4150
6 CR2 8 FRT_24V
0 FRONTAL_EN* J3 15
L 4 1
J1 2
6
R5 4
J1 1
2.49K
1%
0.500W
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/switch_relay_if BLOCK SHT 1 OF 1 H

1 2 3 4 5 6 7 8 9 10 11
5-10

1 2 3 4 5 6 7 8 9 10 SHT. 9 CONT. 10
2106682SCH
C16
A A
100P
RES_DATA(15:0) 50V
10%
0 RDAT0
1
R13 R12
2 10K 20.0K
3
4 3 R7 PEXT1
PIEZO 0.5W 12VP J3 21
5 10% 499
6 100K
VOLUME 2
7 RDAT7 R8 C20
1 R4 PEXT2
J3 22
UP (CW) = 1 499
0.1U L
5 PCS3* DOWN (CCW) = 0 L 25V
B CHIP_SELECTS(10:0) 10% B
TP5
23
22
21
19
18
17
15
14
13
12
11
10
9
8
7
6
5
4
YELLOW 2 8 AR1
I– TLE2062CD
IO37
IO36
IO35
IO34
IO33
IO21
IO20
IO19
IO18
IO17
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
U6 V+ PIEZO_H
1
74HCT14 OUT
C17 TL072_IN
RESETS(4:0) PIEZO* PIEZOAMP_IN 3 V–
IO49 24 5 6 I+
IO50 25 BUZ_EN 4
IO51 26 WATCH_DOG 0.1U C22
RES_ADDRESS(20:0) 27 25V
IO52 10% R14 R17
4 PCS2* 2 I1 IO53 28 1M 20.0K
0 PWA_RST* 32 29 CLK_DN 100P
PKM44EP–0901 2 MT1
RES_CONTROL(9:0) I2 IO54
1 RADDR1 34 I3 U12 IO55 30 CLK_UP 12VN
50V
4 RWR* 68 31 UP1_DOWN0 10%
I4 EPM5128–2 IO56
5 RRD* 66 38
C PHASE_A* 36
I5 IO65
39 CNT_DN* L
R16 1 C
VCC I6 IO66
PHASE_B* 35 I7 2106793 IO67 40 CNT_UP* 20.0K
41 U6
R24 IO68
42
12VP
IO69 74HCT14 VCC
2K IO70 43
IO71 44 13 12
0 RCLK 1 45 ENCODER_INT 2
U6 I/CLK IO72
6 8 AR1
74HCT14 U6 MEB12–5 2 DS10 I– TLE2062CD
IO120
IO119
IO118
IO117
IO116
IO115
IO114
IO113
IO101
IO100
R10 74HCT14 V+
IO99
IO98
IO97
IO85
IO84
IO83
IO82
IO81
CLAR_CHB 11 10 7 PIEZO_L
J4 3 VCC POS OUT
1 2
100
NEG R15 5 V–
PH_A 65
I+
64
63
62
61
60
59
58
57
56
55
53
52
51
49
48
47
46
1 4
VCC U6 10K
R25 74HCT14
L C19
2K
3 4 BUZ_EN*
D VCC R9 D
J4 1 EPM_OE
2K 0.1U L
25V
U6 12VN 10%
74HCT14
3 SELF_RST XC_RST* 4
CLAR_CHA R11 9 8
J4 4
100 XC_PROG 5
PH_B 2 RADDR2
DIP_SW_RD* 7
LGND 3 RADDR3 INTERRUPTS(3:0)
J4 5 LED_WR* 8
L 4 RADDR4
RELAY_WR* 3
E J4 2 E
MISC_IO(8:0)
6 WATCH_DOG
F F
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/encoder_piezo_if BLOCK SHT 1 OF 1 H

MADE BY DATE APPR BY DATE OTHER Potter–Hummer DATE 1–SEP–94 2106682SCH 0 B 9 /1 0
1 2 3 4 5 6 7 8 9 10 11

1 2 3 4 5 6 7 8 9 10 SHT. 10 CONT. 11
2106682SCH
A A
VIDEO_MEMORY
B B
BANK0_ADDR(11:0) BANK0_DATA(15:0)
BANK0_CNTL(2:0) BANK1_DATA(15:0)
BANK1_ADDR(11:0) FONT_DATA(7:0)
BANK1_CNTL(2:0)
DISPLAY_CONTROL FONT_ADDR(16:0)
BANK0_ADDR(11:0) FONT_CNTL(1:0)
SHEET 12
C BANK0_DATA(15:0) BANK0_CNTL(2:0) C
BANK1_DATA(15:0) BANK1_ADDR(11:0)
FONT_DATA(7:0) BANK1_CNTL(2:0)
FONT_ADDR(16:0)
CHIP_SELECTS(10:0)
CHIP_SELECTS(10:0) FONT_CNTL(1:0)
RES_CONTROL(9:0)
RES_CONTROL(9:0) DISPLAY_DRIVE
RES_ADDRESS(20:0)
RES_ADDRESS(20:0) DISP_DATA(3:0)
RES_DATA(15:0)
RES_DATA(15:0) DISP_SYNC(3:0)
D DISP_DATA(3:0) D
MISC_IO(8:0)
MISC_IO(8:0) INTERRUPTS(3:0)
SHEET 11 DISP_SYNC(3:0)
SHEET 13
E E
INTERRUPTS(3:0)
F F
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/plasma_display_if BLOCK SHT 1 OF 1 H

MADE BY DATE APPR BY DATE OTHER Potter–Hummer DATE 1–SEP–94 2106682SCH 0 B 1 0 /1 1
1 2 3 4 5 6 7 8 9 10 11
5-12

1 2 3 4 5 6 7 8 9 10 SHT. 11 CONT. 12
2106682SCH
BANK0_DATA(15:0)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BANK1_DATA(15:0)
A10
C10
A11
D11
A12
C12
A13
C13
D10
B10
B11
C11
B12
D12
B13
B5
C6
B6
B7
D7
A8
C8
B9
C5
A5
D6
A6
C7
A7
B8
C9
A9
BANK0_ADDR(11:0)
B0_D0
B0_D1
B0_D2
B0_D3
B0_D4
B0_D5
B0_D6
B0_D7
B0_D8
B0_D9
B0_D10
B0_D11
B0_D12
B0_D13
B0_D14
B0_D15
B1_D0
B1_D1
B1_D2
B1_D3
B1_D4
B1_D5
B1_D6
B1_D7
B1_D8
B1_D9
B1_D10
B1_D11
B1_D12
B1_D13
B1_D14
B1_D15
FONT_DATA(7:0)
0 F14 N5 0 2 M2 R52
F_D0 B0_A0
1 D15 B3 1
F_D1 B0_A1 4.75K
2 F16 C15 2 L
F_D2 B0_A2
3 C16 E14 3
F_D3 B0_A3
4 E16 G2 4
RES_ADDRESS(20:0) F_D4 B0_A4
5 B16 R16 5
F_D5 B0_A5
6 F15 D2 6
F_D6 B0_A6
B 7 E15 F_D7 B0_A7 G3 7 B
K2 8 BANK0_CNTL(2:0)
RES_CONTROL(9:0) B0_A8
0 M16 D4 9
CPU_A0 B0_A9
1 R12 E1 10
7 CPU_A1 B0_A10
2 R13 J1 11
CPU_A2 B0_A11
3 T14
CHIP_SELECTS(10:0) CPU_A3
4 K16 CPU_A4 BANK0_OE* H 1 6 BANK0_OE* 0
5 U35 CHAR0_WE* 1
T7 CPU_A5 CHAR0_WE* L 1 6
6 R11 CPU_A6 ATTR0_WE* K 1 5 ATTR0_WE* 2
7 R10 XC3090 BANK1_ADDR(11:0)
VCC U16 8
CPU_A7
0
74HCT14 N10 CPU_A8 B1_A0 T9
9 R8 B4 1
R58 CPU_HOLD CPU_A9 B1_A1
9 8 10 N6 H2 2
CPU_A10 B1_A2 BANK1_CNTL(2:0)
11 P5 D13 3
2K CPU_A11 B1_A3
12 T5 F1 4
C MISC_IO(8:0) CPU_A12 B1_A4 C
13 R4 N12 5
XC_RST* CPU_A13 B1_A5
14 T6 C1 6
5 6 4 CPU_A14 B1_A6
15 P7 G1 7
XC_PROG CPU_A15 B1_A7
16 T4 K3 8
R55 CPU_A16 B1_A8
D16 9
2K B1_A9
R53 U37 20 RBHE* N15 RBHE* B1_A10 E2 10
4.75K XC1765 2 RDEN* P15 RDEN* B1_A11 H1 11
3 RDTR* M14 RDTR*
DONE 8 LWR* BANK1_OE* 0
4 CE CEO 6 L15 RWR* BANK1_OE* J 1 6
3 R/OE D 1 DIN 9 LRD* M15 RRD* CHAR1_WE* J 1 5 CHAR1_WE* 1
C CCLK 2 CLK ATTR1_WE* N 1 6 ATTR1_WE* 2
3 PCS1* N13 FONT_ADDR(16:0)
PCS*
B Q2 9 MCS0* P16 MCS0* F_A0 K14 0
MMBT3904L 10 MCS1* L14 MCS1* F_A1 A14 1
2101183–2 G14 2
F_A2 FONT_CNTL(1:0)
E R15 P9 3
RESET* F_A3
D R59 F_A4 A4 4 D
R3 C4 5
DIN F_A5
H15 6
10K F_A6
R2 D5 7
CCLK F_A7
L R14 F2 8
DONE F_A8
J2 9
VCC F_A9
C2 10
VCC C93 F_A10
D1 11
F_A11
K1 12
VCC F_A12
F3 13
F_A13
0.01U E3 14
R63 F_A14
XC3090_OE B2 P4 15
R67 PWRDWN* F_A15
P11 16
2K 2K F_A16
DOUT N4 DOUT F_OE* G15 FONT_OE* 0
E Y4 8
R47 M0 G16 FONT_WE* 1 E
F_WE* DISP_DATA(3:0)
VCC 100 B15 M0
B14 M1 PIX_B0 N1 PIX_D0 0
1 OE
OSC_TRI–S
PIXEL_CLK L
R46 M1 N2 PIX_D1 1
OUT 5 PIX_B1
100 PIX_B2 P1 PIX_D2 2
20.000MHz DISP_SYNC(3:0)
PIX_B3 P2 PIX_D3 3
GND B1 M3 VSYNC 0
PIX_CLK VSYNC
4
VCC HSYNC M1 HSYNC 1
BLANK M2 BLANK 2
0 L1 IS_D0 PCLK R1 PCLK 3
L 1 L2 IS_D1 VINT L3 VSYNC_INT
CPU_D10
CPU_D11
CPU_D12
CPU_D13
CPU_D14
CPU_D15
0 INTERRUPTS(3:0)
CPU_D0
CPU_D1
CPU_D2
CPU_D3
CPU_D4
CPU_D5
CPU_D6
CPU_D7
CPU_D8
CPU_D9
R65 R64
2K 2K
INTENSITY(1:0)
F S4 F
R5
P6
R6
R7
N7
T8
P8
R9
T10
P10
T11
N11
T12
P12
T13
P13
DIPSW 4
1 8 0
10
11
12
13
14
15
2 7 1
0
1
2
3
4
5
6
7
8
9
L RES_DATA(15:0)
3 6
4 5
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/plasma_display_if/display_control BLOCK SHT 1 OF 1 H

REV 2 P C N 196966 DESCRIPTION APPR Scott Bielski DATE 1–SEP–94 Milwaukee, WI USA DRAWING NO. REV SIZE SHT./CONT. ON
MADE B Y Glenn Teske D A T E 11NOV96 APPR BY DATE OTHER Potter–Hummer DATE 1–SEP–94 2106682SCH 2 B 1 1 /1 2
1 2 3 4 5 6 7 8 9 10 11
5-13

1 2 3 4 5 6 7 8 9 10 SHT. 12 CONT. 13
2106682SCH
A FONT_ADDR(16:0)
A
FONT / GRAPHICS
MEMORY
FONT_CNTL(1:0)
U25
HM628128LP–8
0 12 A0
BANK1_ADDR(11:0) 1 11 A1
2 10 A2
3 9 A3
BANK1_CNTL(2:0) 4 8 13 0
A4 IO0
5 7 A5 IO1 14 1
6 6 A6 IO2 15 2
B 7 5 A7 IO3 17 3 B
U32 U34 8 27 A8 IO4 18 4
CY7C185–35 CY7C185–35 9 26 A9 IO5 19 5
BANK0_ADDR(11:0) 10 23 20 6
A10 IO6
0 21 0 21 11 25 21 7
A0 A0 A11 IO7
1 23 A1 1 23 A1 12 4 A12
BANK0_CNTL(2:0) 2 24 11 0 2 24 11 0 13 28
A2 IO0 A2 IO0 A13
3 25 12 1 3 25 12 1 14 3
A3 IO1 A3 IO1 A14
4 2 A4 IO2 13 2 4 2 A4 IO2 13 2 15 31 A15
5 3 15 3 5 3 15 3 16 2
A5 IO3 A5 IO3 A16
6 4 16 4 6 4 16 4
A6 IO4 A6 IO4
7 5 A7 IO5 17 5 7 5 A7 IO5 17 5 1 FONT_WE* 29 WE
8 6 18 6 8 6 18 6 22
A8 IO6 A8 IO6 CS1
9 7 19 7 9 7 19 7 30
A9 IO7 A9 IO7 VCC CS2
10 8 10 8 L 24
C A10 A10 OE C
11 9 11 9
A11 A11
10 A12 10 A12
FONT_LOGO
1 CHAR0_WE* 27 WE
1 CHAR1_WE* 27 WE VCC 0 FONT_OE*
VCC 20 CE1 20 CE1
26 CE2 26 CE2
0 BANK0_OE* 22 OE 0 BANK1_OE* 22 OE
R49
R45 2K
2K L CHARACTER L CHARACTER
U28 U30 FONT_DATA(7:0)

CY7C185–35 CY7C185–35
D D
0 21 A0 0 21 A0
1 23 1 23
A1 A1
2 24 11 8 2 24 11 8
A2 IO0 A2 IO0
3 25 A3 IO1 12 9 3 25 A3 IO1 12 9
4 2 13 10 4 2 13 10
A4 IO2 A4 IO2
5 3 15 11 5 3 15 11
A5 IO3 A5 IO3
6 4 16 12 6 4 16 12
A6 IO4 A6 IO4
7 5 17 13 7 5 17 13
A7 IO5 A7 IO5
8 6 A8 IO6 18 14 8 6 A8 IO6 18 14
9 7 19 15 9 7 19 15
A9 IO7 A9 IO7
10 8 10 8
A10 A10
11 9 A11 11 9 A11
10 10
E A12 A12 E
2 ATTR0_WE* 27 WE
2 ATTR1_WE* 27 WE
20 CE1 20 CE1
26 CE2 26 CE2
0 BANK0_OE* 22 OE
0 BANK1_OE* 22 OE
L ATTRIBUTE L ATTRIBUTE
BANK1_DATA(15:0)
F BANK0_DATA(15:0) F
DISPLAY MEMORY DISPLAY MEMORY

BANK 0 BANK 1
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/plasma_display_if/video_memory BLOCK SHT 1 OF 1 H

1 2 3 4 5 6 7 8 9 10 11
5-14

1 2 3 4 5 6 7 8 9 10 SHT. 13 CONT. 14
2106682SCH
A A
FUJITSU
PLASMA DISPLAY
B INTERFACE B
J9
F_VSYNC
1 2
U36
74ALS244A F_HSYNC
DISP_SYNC(3:0) 3 4
L 1 _1G
19 _2G 5 6 E
0 VSYNC 2 1A1 1Y1 18 F_D0
7 8
1 HSYNC 4 1A2 1Y2 16
C 2 BLANK 6 14 SPARE_BLANK F_D1 C
1A3 1Y3 9 10
8 1A4 1Y4 12
DISP_DATA(3:0) 11 9 F_PCLK
2A1 2Y1 11 12
2 PIX_D2 13 2A2 2Y2 7
3 PIX_D3 15 2A3 2Y3 5
13 14
17 3 L
2A4 2Y4
3 PCLK Rec–Pin
Rt–Angle
14–Pos_Ribbon
L
D D
E E
F F
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/plasma_display_if/display_drive BLOCK SHT 1 OF 1 H

1 2 3 4 5 6 7 8 9 10 11

1 2 3 4 5 6 7 8 9 10 SHT. 14 CONT. –––

2106682SCH
12VP TP3 VCC

A A
WHITE
J5 1
12VP
C28 C2 C43 C11 C26 C37 C36 C38 C59 C51 C62 C34 C83 C76 C77 C64 C65 C55
+ C41 + C78 + C1 + C29
J5 3 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
33U 22U 22U 22U 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V
16V 20V 20V 20V 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
J5 4
LGND
J5 7
VCC
L
VCC
J5 8
J5 9
VCC
B B
C79 C50 C86 C87 C68 C75 C82 C81 C88 C74 C69 C63
+ C35 + C24 + C91 + C84 + C67 + C73 + C95 + C54 + C53
TP1 TP6 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
47U 47U 47U 47U 22U 22U 22U 22U 22U 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V
BLACK BLACK 10V 10V 10V 10V 20V 20V 20V 20V 20V 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
J5 5
LGND
BLACK
L
TP7 VCC
J5 6
LGND
C C71 C42 C56 C60 C61 C89 C52 C57 C58 C47 C49 C48 C18 C30 C31 C32 C
+ C66 + C44 + C39
TP4 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
33U 22U 22U 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V
WHITE 16V 20V 20V 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
J5 2
12VN
L
12VN VCC
VCC TP2
C72 C80 C96 C15 C10 C14 C70 C90 C92 C23 C94 C85 C33 C45 C27
RED U7
R1
74HC14 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
2K 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 50V 50V 50V
D 13 12 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% D
U16
74HCT14
L
11 10
CHASSIS GROUND CONNECT
U16 U39 U40
74HCT14
12VP
13 12
12VP
L L
E L E
VCC
VCC
PGA / PLCC / SSOP POWER PIN–OUT
–––––––––––––––––––––––––––––––– CR1
VCC VCC 12VP VCC VCC VCC VCC VCC DEVICE VCC LGND PRLL5817
–––––––– –––––––––––– ––––––––––––
1 14 1 20 1 20 1 24 1 28 1 32 1 8 EPM5128 3,20,37,54 16,33,50,67 LED5V
XC3090A D9,D14,H14,D3, D8,C14,J14,C3,
P14,N9,P3,H3 N14,N8,N3,J3 C3
80C186XL 9, 43 26, 60 0.1U
F 7 8 10 11 10 11 12 13 14 15 16 17 4 5
25V F
SCC2692 44 22 10%
LGND
L L L L L L
COM20020 15, 28 7, 14, 22
12VN
L
74ABT162245/ 7,18,31,42 4,10,15,21,
74HC14 74XX273 SN75C1154N 74ABT841 CY7C185 HM628128 XC1765 74ABT16245–1 28,34,39,45 12VN
74HCT14 74XX244
PAL22V10 28 14
29F010 32 16 12VN
H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/power_decoupling BLOCK SHT 1 OF 1 H

MADE BY DATE APPR BY DATE OTHER Potter–Hummer DATE 1–SEP–94 2106682SCH 0 B 1 4 /– – –
1 2 3 4 5 6 7 8 9 10 11
5-16

SCC1 A3
PLASMA DISPLAY
NEC: 46Ć276310P1
DISPLAY: 2183003
SCC1 A3 A1
PLASMA DISPLAY POWER SUPPLY
DIXY: 46Ć276310P2
NOTE: Schematic not available. Refer to

NEC or Dixy Display Manuals for
schematics.


SCC1 A4
TOUCH FRAME
46Ć267290P1
and
2183004
NOTE: Schematic not available.


SCC1 A6
HANDSWITCH
46-270800G4
NOTE: See 46-276420-S for schematic.

SCC1 A7
CONSOLE FIBRE TO COAX ARCNET
2120138ADW

1 2 3 4 5 6 7 8 9 10 SHT . 1 CONT . 2
2 1 2 0 1 3 8 SCH
A A
N OT E S :
1 . T H E GR O U P N U MB E R A N D G R OU P R E V I S I O N
F O R T H I S P WA I S 2120138 A
2 . T H I S S C H E MA T I C ME E T S T H E S P E C I F I C A –
B T I ON S O F GE S C H E MA T I C S T A N D A R D S B
46–017486.
3 . U N L E S S O T H E R WI S E S P E C I F I E D :
R E S I S T O R S A R E I N O H MS , 0 . 2 5 W, 1 %.
C A P A C I T OR S A R E I N F A R A D S .
I N D U C T OR S A R E I N H E N R I E S .
S HT
S H E E T _ N A ME REV 4 . A C T I V E L OW S I GN A L S A RE I NDI CA T E D
NUM
WI T H ” * ” A F T E R T H E S I GN A L N A ME
C COA X _ F I B RE _ CONV 2 0 C
COA X _ F I B RE _ CONV 3 0
S I GN
R E V I S I ON P C N N U MB E R DA T E
n
OF F
D n
A –––––– 2 6 SEPT9 4 J WW D
n
0 –––––– 2 4 OC T 9 4 CJ P
E E
F F
H BL OCK PAT HNAME / us er / adv ant x _i i / f i br e_opt i c s / c ons ol e_f i br e_c oax _c onv er t er BL OCK SHT 1 OF 3 H
REV 1 PCN DESCRI PT I ON MADE Pa r k _ C DAT E 2 6 SEPT 9 4 DESI GN T I T L E CONSOL E_ F I BRE_ COAX_ CONVERT ER
MADE BY DAT E APPR BY DAT E CHECK DAT E GE ME D I CA L S Y S T E MS F I RST MADE F OR Ad v a n t x _ I I
REV 2 PCN DESCRI PT I ON APPR DAT E M i l wa u k e e , WI US A DRAWI NG NO. REV SI Z E SHT . / CONT . ON
MADE BY DAT E APPR BY DAT E OT HER DAT E 2 1 2 0 1 3 8 SCH 0 B 1/ 2
1 2 3 4 5 6 7 8 9 10 11

1 2 3 4 5 6 7 8 9 10 SHT . 2 CONT . 3
2 1 2 0 1 3 8 SCH
A A
P5 V
U4
7 4 HCT1 4
1 2
R1 R2 C2
84. 5 84. 5
T RA NS M I T D I S A B L E P UL S E E X T E NDE R 1%
0. 5W
1%
0. 5W
0. 33U
50V
20%
B P5 V B
L
DL 2 U7
U7 DS1 0 0 5 – 2 5 0 7 4 AL S0 8 U7 U3 U2
U4 SN7 5 4 5 4 B
CR3 CR2 CR1 HF BR1 5 2 7
7 4 AL S0 8 8 VCC T1 7 4 7 4 AL S0 8 7 4 HCT 1 4
9 2 6 12 TX_DATA 1 3 1 AN
T2 A1 _ Y1
8 1 I N T3 6 5 11 13 12 TX_EN* 2 B1
10 T4 3 13 6 A2 _ Y2 5
1 N5 8 1 9 1 N5 8 1 9 1 N5 8 1 9
4 GND OUT 5 7 B2 2 CAT
L
L L
C C
P5 V P5 V
P5 V P5 V
U6 R4
10
7 4 AL S7 4 A 1. 00K
D U5 1% D
DL 1 U4
_ PRE
71–0961 9 Q D 12 7 4 HCT 1 4
0. 25W U1
6 DS1 0 0 0 – 1 2 5 HF BR2 5 2 1
5 V+
7 T1 VCC 8 CL K 11 4 3 1 VO
7 RX PWS1 20 2 T2
_ CL R
J5 11 OUTS PWS2 18 6 T3 I N 1 8 _Q
12 OUTC DI SABL 19 3 T4 2
T PA 16 5 OUT GND 4 P5 V GND RL VCC P5 V
13
T PB 15 4 3
10
T PC R6 L
9 100 N1 2 V
T PD C1
5 1%
C1 0 R5 T PE
0. 25W
10. 0K T PF 8
1%
E 0. 01U 0. 5W 2 0. 1U
E
1000V 1 2 V– R3 100V
20% 1 2 RET– 1
U4 U4 33. 2K 1 N5 8 1 9 20%
5 V– 3 7 4 HCT1 4 7 4 HCT1 4 1%
0. 25W CR4 L
L 4 6 5 10 11
GND
GND1 13
GND2 14 C4
GND3 17
0. 33U
DI P UL S E GE NE RA T OR 50V
L 20%
F F
P OWER UP P RE S E T
REV 2 PCN DESCRI PT I ON APPR DAT E M i l wa u k e e , WI US A DRAWI NG NO. REV SI Z E SHT . / CONT . ON
MADE BY DAT E APPR BY DAT E OT HER DAT E 2 1 2 0 1 3 8 SCH 0 B 2/ 3
1 2 3 4 5 6 7 8 9 10 11
9-4

1 2 3 4 5 6 7 8 9 10 SHT . 3 CONT . –
2 1 2 0 1 3 8 SCH
A A
B B
P5 V N1 2 V
U6
7 4 AL S7 4 A
4
J7 U7
C U4 C
_ PRE
7 4 AL S0 8 7 4 HCT 1 4 2 D Q 5
1
2
3 9 8 3 CL K
2
1
_ CL R
_Q 6
3
1
L L
5
Hd r – Pi n
Rt _ An g l e
5 – Po s _ w– p e g s L
L
D D
S P A RE S
E P5 V E
P5 V P1 2 V N1 2 V
J1 J3 J6 J4
C1 1 C1 3 C1 2 C6 C7 C9
2 2
C3 C5
0. 1U
100V
0. 1U
100V
0. 1U
100V
0. 1U
100V
0. 1U
100V
0. 1U
100V
+ 10U + 1. 0U 3 1
35V 35V 20%
20% 20% 20% 20% 20% 20% 20% 20% 35V
3 1 3 1 1. 0U
+2 C8
F F
L L L L
B UL K DE COUP L I NG
REV 2 PCN DESCRI PT I ON APPR DAT E Mi l wa u k e e , WI US A DRAWI NG NO. REV SI Z E SHT . / CONT . ON
MADE BY DAT E APPR BY DAT E OT HER DAT E 2 1 2 0 1 3 8 SCH 0 B 3/ –
1 2 3 4 5 6 7 8 9 10 11

#"&! ( 3./#). #(#2

+2

&(1 0'## &.!+*.&*
.& !&$&! /&* )#-&! +-/% )#-&!
#"&! ( 3./#). 5 0-+,# #(#2
-0# "# ( &*&4-#
0! #"#2
- *!#

Advantx-E Operator Console Schematics SM 2123272-100 8

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Advantx-E Operator Console Schematics SM 2123272-100 8

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IMPORTANT! . . . XĆRAY PROTECTION

GENERAL ELECTRIC COMPANY MEDICAL SYSTEMS

CERTIFIED ELECTRICAL CONTRACTOR STATEMENT

    

1-1 and 1-2 8

2-1 thru 2-8 8

3-1 thru 3-8 8

4-1 and 4-2 8

5-1 thru 5-16 8

6-1 and 6-2 8

7-1 and 7-2 8

8-1 and 8-2 8

9-1 thru 9-6 8

03 */%*7*%6"- 4*(/"- $0//&$5*0/4 " 4*.*-"3 4$)&."5*$ 4536$563*/( 5&$)/*26& *4

POWER SUPPLY CONSOLE CONTROL PWA

CHASSIS_GND SHELL GRN/YEL

GND HARNESS CHASSIS_GND

SYSTEM CONNECTOR CONSOLE CONTROL PWA HANDSWITCH CRADLE HANDSWITCH

SYSTEM RESET SWITCH

POWER SUPPLY CONSOLE CONTROL PWA

CHASSIS_GND SHELL GRN/YEL

GND HARNESS CHASSIS_GND

SYSTEM CONNECTOR CONSOLE CONTROL PWA HANDSWITCH CRADLE HANDSWITCH

SYSTEM RESET SWITCH

R125 ON–POLE1–1 ON–POLE1–2

ALT. Note: This sheet is a copy of

POWER SUPPLY CONSOLE CONTROL PWA

CHASSIS_GND SHELL GRN/YEL

GND HARNESS CHASSIS_GND

SYSTEM CONNECTOR CONSOLE CONTROL PWA HANDSWITCH CRADLE HANDSWITCH

SYSTEM RESET SWITCH

IND–1 XRAY ON LAMP IND–2

VSYNC J1–24 J9–1 F_VSYNC

NOTE: Schematic not available.

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/cover_sheet BLOCK SHT 1 OF 1 H

VCC SWITCH_RELAY_IF ENCODER_PIEZO_IF PLASMA_DISPLAY_IF

RES_DATA(15:0) RES_DATA(15:0) RES_DATA(15:0)

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa BLOCK SHT 1 OF 1 H

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/cpu_control BLOCK SHT 1 OF 1 H

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/cpu_control/cpu_80c186 BLOCK SHT 1 OF 1 H

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/cpu_control/memory_if BLOCK SHT 1 OF 1 H

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/cpu_control/io_if BLOCK SHT 1 OF 1 H

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/arcnet_rs232_if BLOCK SHT 1 OF 1 H

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/switch_relay_if BLOCK SHT 1 OF 1 H

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/encoder_piezo_if BLOCK SHT 1 OF 1 H

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/plasma_display_if BLOCK SHT 1 OF 1 H

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/plasma_display_if/display_control BLOCK SHT 1 OF 1 H

U28 U30 FONT_DATA(7:0)

DISPLAY MEMORY DISPLAY MEMORY

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/plasma_display_if/video_memory BLOCK SHT 1 OF 1 H

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/plasma_display_if/display_drive BLOCK SHT 1 OF 1 H

1 2 3 4 5 6 7 8 9 10 SHT. 14 CONT. –––

12VP TP3 VCC

H BLOCK PATHNAME /user/advantx_ii/console_ASM/console_control_pwa/power_decoupling BLOCK SHT 1 OF 1 H

NOTE: Schematic not available. Refer to

NOTE: Schematic not available.

NOTE: See 46-276420-S for schematic.

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