Solid State Electronics xxx (xxxx) xxx–xxx

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Solid State Electronics

journal homepage: www.elsevier.com/locate/sse

Lithography for now and the future

M.A. van de Kerkhof, J.P.H. Benschop, V.Y. Banine
⁎

ASML, Veldhoven, the Netherlands

ARTICLE INFO

The review of this paper was arranged by Profs.

S. Luryi, J. M. Xu, and A. Zaslavsky

1. Introduction “Moore’s Law”.

Optical lithography has supported multiple generations of scaling of
integrated chip production, known as Moore’s law: doubling of the
amount of transistors on the chip about every 1.5–2 years.
While state-of-art immersion lithography tools with a numerical
aperture of 1.35 and throughput of > 200 wafers per hour are the main
working horse of the semiconductor industry, multiple patterning is
required to obtain ∼10–16 nm half-pitch.
Extreme Ultraviolet (EUV, corresponding to 13.5 nm light) scanners
are being introduced in high volume manufacturing and will extend
Moore’s Law for the foreseeable future.
After a short introduction of IC making in the past, we will discuss
the present and future of lithography. This includes a demonstration of
the EUV state-of–art systems capabilities, discussion of critical EUV
technologies as well as a view of further extension in the future.
2. A bit of history
In his 1975 IEEE article [8], Gordon Moore predicted the compo-
nents per chip would double every two years rather than every year, as
observed from 1959 until 1975.
Though it is not a physical law, and at best can be called an eco-
nomic law or a conjecture based on a couple of points over a period of
6 years (see Fig. 2), the prediction of Moore has become the guiding
principal for the semiconductor industry for the last 50 years.
It is worth mentioning that, in a much later investigation, Ray
Kurzweil [9,10], extended the Moore’s exponential trend retro-
spectively back to 1900 (see Fig. 3).
As illustrated in [11] a number of paradigm shifts have happened in
the field of technological employment over the last 60 years:
• connecting different locations e.g. land line telephones, to
• connecting individuals e.g. mobile phones and to
• connecting smart things and devices in the near future e.g. auto-
motive, home appliances, medical etc.

Lithography in the form of the carved type printing can be dated as
far back as the 3rd century CE [1].
As can be seen from Fig. 1, lithography has always played a major
role in information technology. While from the16th to the 19th century
it was used for printed books, maps, newspapers etc; in the mid-20th
century, with the invention of the micro- and nano-electronics, it took
on a new meaning and became a core process and the basis for the
patterning solutions of the modern day semiconductor industry.
For 50 years the progress of the semiconductor industry and thus
lithography was governed by the law named after one of the founders of
Fairchild Semiconductors and later co-founder of Intel, Gordon Moore.
In his 1965 publication [7], Gordon Moore mentioned that “the
complexity of the minimum component cost has increased roughly a
factor of two per year” and he predicted this trend would continue for
another decade. Later on this prediction was commonly referred to as
Until 2005, making transistors smaller and at the same time in-
creasing the clock speed (so-called Dennard scaling) went hand in hand.
This allowed a simultaneous decrease of the chip cost and a rather
straightforward increase of computer performance. The more compu-
tational technology is embedded in our society, the higher percentage
of power consumption that is dedicated to it.
Though evaluations differ, currently server farms alone already
account for at least a couple of percent the electrical power consump-
tion in the US [12,13]. The scalability of power efficiency of compu-
tations becomes a significant additional driver for Moore’s law. As has
been shown in [10] the dependence of computations per kWh as a
function of time also shows a Moore’s-law-like behavior, which is
sometimes called Koomey’s law, see Fig. 4.

⁎
Corresponding author.
E-mail address: vadim.banine@asml.com (V.Y. Banine).

https://doi.org/10.1016/j.sse.2019.03.006

0038-1101/ © 2019 Published by Elsevier Ltd.

Please cite this article as: M.A. van de Kerkhof, J.P.H. Benschop and V.Y. Banine, Solid State Electronics,
https://doi.org/10.1016/j.sse.2019.03.006
M.A. van de Kerkhof, et al. Solid State Electronics xxx (xxxx) xxx–xxx

Fig. 1. From carved printing [2] through rotary press [3] to Photolithography and EUVL [4–6].

2.1. Lithography for the semiconductor industry

Requirements for and thus the scaling of printable features by a li-

thographic apparatus is determined by the Abbe resolution criterium in
a form similar to the one in [14], as presented in Fig 5. As can be seen,
both the numerical aperture and the radiation wavelength play a major
role in the choice of and methods for scaling.
While the evolution of lithographic machines (see Fig. 6), happens
by the increase of the numerical aperture of the optical system at
constant wavelength, the revolution can be associated with a change of
the wavelength and with this choice of light emitters and optical ma-
terials. Nonetheless, evolutionary part of the scaling does not make the
challenge significantly smaller. An example of this is immersion litho-
graphy. A strong example of revolutionary change in lithography, on
the other hand, is the introduction of Extreme Ultraviolet lithography
(EUVL), where complete system had to be re-thought, starting from a
plasma-based source to a new type of reflective optics in the high va-
cuum environment.

2.2. Extreme Ultraviolet Lithography: technological and scientific revolution

Fig. 2. The famous publication of the graph, which later became known as
Moore’s law [7]. As was stated above lithography is one of the most important
technologies enabling the progress of semiconductor technology.

Fig. 3. Trend of the technological advances of computers according to R. Kurzweil in calculations per s per 1000$ (data are taken from [9]).

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unlike both X-ray and Ultraviolet which have a significantly long ab-
sorption length, EUV only is absorbed in nanometers of any solid ma-
terial and micrometers under normal conditions in gases. This means
that apparatus used in the investigations involving EUV have to use
special and expensive multilayer reflective optics, high vacuum, hot
20–50 eV plasma or accelerator technology for the production of EUV
radiation. Due to these characteristics, applications for EUV were rare
and limited to astrophysics.
This vicious circle of lack of technology leading to lack of interest
and vice versa was broken at the end of the 80 s when an opportunity
presented itself in the form of a new application: EUV lithography. It led
to an explosion of the number of publications at this point in history.
The first paper on the possible application of EUV, or as called at
that time soft X-ray, for lithography was published by Bell Labs [18] in
1985. Already in 1989 Kinoshiba et al. [19] demonstrated EUV imaging
in resist with critical dimensions of ∼0.5 μm, using Schwarzschild
projection optics and a synchrotron as a source. In 1991, EUV images
were shown by prof. Bijkerk’s group [20]. A laser produced plasma
(LPP) source was utilized in order to produce EUV radiation. CDs of
60–80 nm were demonstrated in Japan [21] and the US on the en-
gineering test stand (ETS) tool [22] in 2000 and 2001 respectively. The
EUV lithography program in ASML was launched in 1997. It resulted in
the 2006 shipment of two Alpha Demo Tools to R&D facilities at IMEC
(Belgium) and the University of Albany (NY, USA), which printed on
the critical dimension (CD) of 28 nm. This progressed further towards
Fig. 4. Koomey’s-Moore’s law for computation per kW [13].
the shipment preproduction systems NXE:3100, NXE:3300B, and finally
to the HVM-ready production system NXE:3400B, see e.g. Refs. [23,24].
New challenges for further scaling of semiconductor devices in the
21st century resulted in Extreme Ultraviolet Lithography (EUVL)
3. State-of-the-art EUV lithography
through close collaboration of both hi-tech companies and scientific
institutes.
With the introduction in 2017 of the NXE:3400B [25], with nu-
The number of publications devoted to a certain technological
merical aperture NA = 0.33, EUV lithography is now ready for large
problem by the scientific community can be considered as a sign of
scale production. Offering source power of > 200 W, and a corre-
interest from this community towards a particular problem, see Fig. 7.
sponding throughput of > 125 wph, as well as continuing improve-
As indicated in [15] EUV is one of the last regions of the electro-
ments in overlay, defectivity and availability, this tool is being inserted
magnetic spectrum to be developed and to find practical application. As
for production by leading-edge chip manufacturers worldwide. The
can be seen from the chart in the Fig. 7, the number of published ar-
benefits of the large shift in wavelength to 13.5 nm are multiple: im-
ticles mentioning this part of the spectrum remained relatively low till
proved imaging fidelity improves electrical properties; limiting multiple
the end of the 80 s of the last century. It can be explained by the high
exposures reduces patterning costs and faster cycles-to-yield.
threshold for this technology to be developed due to the fact that,
One of the key features of the NXE:3400B is its flexible illuminator

Fig. 5. Physical limit of optical projection lithography.

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Fig. 6. Lithography roadmap from past to future.

design. It allows setting an illumination mode fitting a particular ima-
ging pattern with the highest contrast achievable and without trans-
mission loss. In order to do this, a system of multilayer mirrors con-
sisting of several hundreds of facets is applied. This enables aggressive
resolution-enhancing techniques to achieve lower k1-factors (see Fig. 5)
and thus improved various printed features (see Fig. 8). It goes hand in
hand with the EUV Projection Optics Box (POB) improvement regarding
aberrations and distortions to support these low-k1 factors and corre-
sponding overlay requirements (see Fig. 9).
In parallel, EUV resists have been developed to take advantage of
the intrinsic resolution of EUV to push the thresholds of lines/spaces
and contact holes, resulting in a robust printing capability of N5-node-
compatible 13 nm Lines/Spaces (k1 = 0.3) and 20 nm Contact Holes,
with sufficient contrast for large-scale production. Also, work is on-
going to co-optimize lithography with etch to improve bottom-line
Local CDU (critical dimension uniformity), with promising results [26].
Although theoretically, EUV resolution can be stretched as low as
∼11 nm for the current NA = 0.33 (corresponding to a k1 = 0.27), in

Fig. 7. History of Extreme Ultraviolet Lithography (EUVL) [15–17].

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M.A. van de Kerkhof, et al.
Fig. 8. An example of available illumination setting in the NXE 3400B [25].
Fig. 9. Improvement in wave front error in the EUV projection optics [25].
practice, it is expected that EUV will also use spacer technology or
multiple patterning to go beyond 13 nm, down to 8 nm. Although this
will go at the expense of process complexity, this can be considered as a
viable path for resolution and LWR (line width roughness), similar to
current state-of-the-art ArFi applications, until possible future high-NA
EUV scanners with an NA > 0.33, e.g. NA = 0.55, become available
(see Fig. 10).
In the past few years, significant advances have been demonstrated
in EUV source power, from 10 W in 2011 to above 250 W today, re-
sulting in a record 147 wph. Further evolutionary improvements of
source power to beyond 300 W are ongoing, with > 400 W already
Fig. 10. State-of-the-art EUV imaging results; (a) 13 nm dense lines and spaces,
and (b) contact holes [26,27].
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Fig. 11. State-of-the-art overlay performance: (a) Single Machine Overlay
0.7 nm, and (b) Matched Machine Overlay at 1.1 nm, exceeding N5-node re-
quirements [25].
demonstrated in a lab setup. In parallel, availability has been con-
tinuously improving, although more work is still needed to bring EUV
to the same availability levels as ArFi.
It should be noted that today’s resists are not yet quite sensitive (or
“fast”) enough to support > 125 wph (even for 250 W source power),
without sacrificing LCDU (local critical dimension uniformity), a
parameter, which becomes increasingly important with current scaling
of critical dimensions to sub-10-nm level. So, while resolution and
overlay requirements are demonstrated by the NXE:3400B, the near
future will see the use of mixed DUV and EUV technologies due to the
economical consideration of the complete semiconductor process. For
some applications/layers the imaging resolution advantages of EUV will
be decisive, while for other applications/layers the throughput ad-
vantage of ArFi Multi-Patterning will be economically favorable.
To enable the best overall economic optimization per layer, the
NXE:3400B has been designed for < 2 nm matched-machine overlay
(MMO) with respect to state-of-the-art ArFi scanners, allowing mix-and-
match operation between these lithographic technologies, (see Fig. 11).
Another issue, which is coming up as EUV approaches HVM in-
troduction, is Reticle Defectivity: any particle of size > 50 nm reaching
the reticle frontside will result in imaging defects at the N5 node.
This has been the focus of much effort in recent years, resulting in a
dual-path approach: the NXE:3400B was designed and built for an ab-
solute minimum of particles reaching the sensitive mask surface; in
parallel, an EUV-compatible thin (< 50 nm) free standing membrane in
front of reticle, which is called pellicle has been developed [27]. It
protects the reticle from particles to reach it. At the same time particles
captured by the pellicle will not be imaged on the wafer due to the fact
that it is positioned out of focus of the projection system.
Although an EUV-pellicle gives a guaranteed yield as far as de-
fectivity is concerned, any EUV-pellicle will have a finite transmission
loss and a corresponding throughput loss of up to ∼20%. On the other
hand, running without a pellicle might give highest throughput but
M.A. van de Kerkhof, et al.
Fig. 12. Dual path approach to manage defectivity towards HVM requirements [27].
Fig. 13. Layout of NA 0.55 Extreme Ultraviolet (EUV) scanner.
with a finite risk of defectivity-related yield-loss (see Fig. 12).
For many applications, the low defectivity count of the NXE:3400B
means it will be economically favorable to run without a pellicle and to
rely on frequent wafer (or reticle) inspections to catch a yield-killing
defect in time.
For high-end and low-redundancy applications, using an EUV-pel-
licle will still be the preferred choice.
It might be worthwhile to note that there are other mask-related
defects that are not related to the scanner and thus not addressed by the
pellicle. It has been proposed to address these by split exposures [28],
taking advantage of the relatively large exposure latitude of EUV; early
results show such schemes indeed significantly reduce stochastic spread
of printed features and so might be an enabling technology to push the
resolution of NA = 0.33 EUV lithography for leading edge pilot pro-
duction [29].
For the foreseeable future shrink continues to have a positive effect
on cost and density, which more than compensates the increased pro-
cess complexity [30]. The latest International Technology Roadmaps
for Semiconductors predicts an ongoing shrink until 2029 [31]).
To enable another decade of cost effective shrink ASML is devel-
oping a high-NA EUV system. The increase of NA from 0.33 to 0.55 is
the largest step (1.7x) ever in the optical lithography roadmap. The
scanner will enable single exposure lithography for 3 nm logic node and
beyond, the reticle stage acceleration will quadruple compared to to-
day’s EUV scanners to ensure a productivity of 185 wafers/hour [32].
Fig. 13 below gives an indication of the size and layout of such a high-
NA scanner.
The fact that 3 leading IC makers ordered 4 of these system years
ahead of completion [33] is a testimony to the fact that rumors of the
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death of Moore’s Law are far from the truth.
4. Concluding remarks
Lithography, as a cornerstone piece of semiconductor manu-
facturing technology, successfully supported major changes in our way
of life for the last several decades. The evolution of lithography tech-
nology from the 90 s of the last century till now, from i-line to ArF
immersion systems was instrumental in this process.
EUV lithography is the next step in this direction. Based on a range
of revolutionary new technologies, it will support cost-effective solu-
tions for semiconductor manufacturing in the foreseeable future.
Pathways to advances in computer power in the further future are
multifold and how lithography will evolve further depends on the
outcome of research of the coming years.
References
[1] Banine VY. Eindhoven: Technische Universiteit Eindhoven. 32 p., 2014.
[2] China Culture. (n.d.). Retrieved from http://ww1.chinaculture.org/gb/en_about-
china/2003-09/24/content_26509.htm.
[3] “Rotary Printing Press.” Wikipedia. Wikimedia Foundation, Web. 20 July 2014.
[4] “CPU-World.com Forums:: View Topic – My First Attempts to Take Die Shots.” CPU-
World.com Forums:: View Topic – My First Attempts to Take Die Shots. Web. 20
July 2014.
[5] http://phys.org/news135270280/.
[6] “Advanced Search.” ASML: Products. Web. 20 July 2014.
[7] Moore GE. Cramming More Components onto Integrated Circuits. Electronics, pp.
114–117, April, 1965.
[8] Moore GE. Progress in Digital Integrated Electronics. © 1975 IEEE. Reprinted, with
permission, from Technical Digest 1975. International Electron Devices Meeting,
IEEE, pp. 11–13, 1975.
[9] http://www.singularity.com/charts/page67.html.
[10] http://content.time.com/time/magazine/article/0,9171,2048299,00.html.
[11] Ericson, Presentation, ISS Europe, Feb 2011.
[12] http://enduse.lbl.gov/projects/InfoTech.html.
[13] Koomey JG, Berard S, et al. Implications of historical trends in the electrical effi-
ciency of computing. IEEE Ann History Comput 2011;33(3):46–54.
[14] Born M, Wolf E. Principles of optics. 7th ed. Cambridge University Press; 2003. p.
466.
[15] Attwood DT. Soft X-rays and extreme ultraviolet radiation: principles and appli-
cations. Cambridge: Cambridge UP; 2000.
[16] Banine V. EUV lithography: today and tomorrow. In: Luryi Serge, Jimmy Xu,
Zaslavsky Alex, editors. Future trends in microelectronics: frontiers and innova-
tions. Wiley-IEEE Press; 2013.
[17] “Multiwavelength Sun.” Multiwavelength Sun. Web. 20 July 2014.
[18] Hoh K, Tanino H. Bell electrotech. Lab., 49, 1985.
[19] Kinoshota H, Kurihara K, et al. J Vac Sci Technol B 1989;7:1648.
[20] Bijkerk F, et al. Design of an extended image field soft X-ray projection system,
Monterey, CA, USA, OSA, 1991.
[21] Kinoshita H. Recent advances of 3-aspherical mirror system for EUVL. SPIE; 2000.
Vol. 3997.
[22] Tichenor DA. Initial results from the EUV engineering test stand. SPIE; 2001. Vol.
4506.
[23] Meiling H. et al. From performance validation to volume introduction of ASML’s
NXE platform. In: SPIE symposium on extreme ultraviolet (EUV) lithography, 2012.
[24] Proc. SPIE 9048, Extreme Ultraviolet (EUV) Lithography V, 90481J, 2014.
M.A. van de Kerkhof, et al.
[25] Proc. SPIE 10143, Extreme Ultraviolet (EUV) Lithography VIII, 101430D, 2017.
[26] Proc. SPIE 10143, Extreme Ultraviolet (EUV) Lithography VIII, 1014319, 2017.
[27] Proc. SPIE 9776, Extreme Ultraviolet (EUV) Lithography VII, 97761Y, 2016.
[28] Proc. SPIE 10143, Extreme Ultraviolet (EUV) Lithography VIII, 1014313, 2017.
[29] Bekaert J, et al. EUV vote-taking lithography for mitigation of printing mask de-
fects, CDU improvement, and stochastic failure reduction. J Micro/Nanolith MEMS
MOEMS 2018;17(4):041013.
[30] Holt B. Moore’s law: a path forward, ISSCC, 2016.
[31] https://www.semiconductors.org/main/2015_international_technology_roadmap_
for_semiconductors_itrs/.
[32] van Schoot J. et al. High-numerical aperture extreme ultraviolet scanner for 8-nm.
[33] https://www.asml.com/press/press-releases/strong-duv-demand-drives-solid-q1-
results-and-confirms-positive-outlook-for-2018-multiple-euv-orders-including-
highna-demonstrate-further-adoption-of-euv-technology/en/s5869?rid=56995.
Jos Benschop started his carrier at Philips Research and
joined ASML in 1997. He currently holds the position of
senior vice president technology and is, amongst others,
responsible for ASML research and system engineering. He
got a PhD in physics from Twente University, he is currently
a part-time professor at Twente University. He published 30
papers and is (co-) inventor of 20 USA patents. He is a
member of the Dutch Academy of Technology and
Innovation (AcTI) and a fellow of SPIE.
Solid State Electronics xxx (xxxx) xxx–xxx
Mark van de Kerkhof began his career at ODME, devel-
oping a novel DVD mastering process, and later worked on
deep-UV and immersion recording technologies for Blu-
Ray. In 1999 he joined ASML as senior designer, working on
miscellaneous sensors and imaging optics in both DUV and
EUV systems, and was responsible for the technical defini-
tion and integration of the NXE:3400B EUV scanner as
Product System Engineer. He is currently responsible for
EUV Defectivity and Scanner Plasma Technology. He (co-)
authored 25 papers and holds 65 USA patents.
Vadim Banine joined ASML Department of Metrology in
1996 and later in 1997 moved to newly organized Research
Department. Currently, after many years in Research, he
holds a position of director of defectivity department in
development and engineering. He received his PhD in
Eindhoven University of Technology. Next to his job at
ASML he is now a part-time professor at the same university
for a chair of Extreme Ultraviolet lithography. He has more
than 50 scientific publications and is (co-) inventor of more
than 170 USA patents. He is one of the winners of the
European Inventor Award of 2018.