DESIGN OF A SINGLE STAGE COMMON
GATE AMPLIFIER
Amninder Singh Gill
Student ID 006204328
Department of Electrical Engineering
San Jose State University
Abstract: The report explains the design of a
single stage common gate amplifier using the
90nm CMOS technology. The main objective of
the design is to meet the specified performance
in terms of gain, bandwidth, power and swing.
The power supply used is 1.2 V and the external
load capacitance that the amplifier drives is 1pF.
The Bandwidth required is more than 1GHz and
a voltage swing of value greater than 1V, a gain
of value more than 30 dB, and power dissipation
less than 1mW are aimed. The tool that has been
used is the Cadence schematic composer to
design the circuit and the SpectreS is used to
simulate the circuit. Dc and parametric analysis
are extensively performed to determine and plot
the relationships between various variables in
the circuit. Ac analysis is done to check the gain
and bandwidth whereas the output swing is
confirmed by the transient analysis.Then an
attempt has been made to maximize all the
circuit specifications.
INTRODUCTION
A common gate amplifier is one of the three
Single Stage Amplifier and is one of the most
basic amplifier which is characterized by high
bandwidth and gain. It is mainly used as a
current buffer or a voltage amplifier. In this
circuit, the input is given to the source terminal,
the output is taken from the drain terminal and
the gate is common to both these terminals.
This configuration is shown in Fig 1. A common
gate amplifier is usually used in High Frequency
Applications and has much higher bandwidth as
compared to other amplifiers, for example A
Common Source Amplifier.
Fig 1. Common Gate Amplifier
It is used less than Common Source
configuration but finds its application when the
circuit is being used close to the frequency
limitations of the Field Effect Transistor, for
instance in a CMOS RF receiver because in such
applications, Common Gate configurations is
more rugged to noise and it can be easily
impedance matched.
Another application of such a configuration is as
a first stage of an amplifier that is designed to
amplify the current rather than the voltage. In
this configuration, it is seen that a Current
Mirror has been used to create the current
biasing network. We could have used a single
transistor instead of the two transistors to create
the current biasing network but then we have to
use two different voltage sources but now we
need only one using Current mirror. A simple
current mirror circuit shown in Fig 2 below has
both the transistors operating in active region.
The two transistors can be of equal or different
sizes. When we consider the finite output
impedance, the transistor having a higher drain
to source voltage will have the higher current.
The gate to source voltages of both the
transistors is equal. Moreover, if we consider
them to be equal size, then the current flowing
through each of them is also equal.

Fig 2 A Simple Current Mirror Circuit
But this configuration has a drawback because if
we need to have more biasing current then we
need to use a bigger resistance and a bigger
voltage source which in turn results into more
power dissipation and hence degrades the circuit
performance. Thus in present days, active loads
such as transistors are used to provide the
desired biasing networks which do not have the
above mentioned problem with such intensity.
This type of configuration is shown below in Fig
3 impedance is found to be 1/gm. The small signal
This configuration is used as a gain stage when
relatively small input impedance is required.
Fig 3 Common Gate Amplifier with active load
that provides the biasing network
The use of current mirrors leads to higher
superiority of the amplifiers to the variation of
power supply and temperature Moreover current
mirrors are more economical in terms of die area
to provide the same biasing current as compared
to a resistance. When used as a load element in
transistor amplifiers, the high incremental
resistance of the current mirror results into high
voltage gains at low values of power supplies.
Now returning to the common gate amplifier as
shown above in Fig 3, to ensure its proper
operation, we have to make sure that all the
three transistors employed must operate in active
region to obtain the desired amplification.
Transistor Q3 provides the necessary bias
voltage to Transistor Q2 to keep it operating in
the active region. Q2 in turn acts as a current
source that provides the necessary bias current
to transistor to keep it in the active region and
provide the desired amplification. The current
and voltages provided by Q3 are themselves
controlled by a biasing resistance Rbias that
helps in maintaining the value of currents
following though both the transistors Q3 and Q2
and also maintains the power dissipation.
By doing the small signal analysis for the
circuit, the various parameters of the circuit can
be obtained. When a straight forward small
signal analysis is performed, the input
model of the above circuit can be shown as in
Fig 4
Fig4 Small Signal Model
The AC voltage gain defined as the ratio of
output voltage to the input voltage for the circuit
and is found by solving the above circuit and the
gain is given by the following expression
In case of our amplifier, the gain can be given by the amplifier will behave in an undesired
a more simple expression fashion.

Av = gm1(rds1 ǁ rds2)

The reference current is provided by transistor

Q3 and a corresponding current I bias flows to the
circuit that acts as the biasing current for Q1 to
provide the necessary amplication conditions.
This current can be controlled by controlling the
value of resistance Rbias. The circuit is as shown
in Fig 5

Fig 5 Common Gate Amplifier circuit used

Fig 6 Circuit Schematic for common gate
amplifier.
Circuit Schematic

The circuit schematic used to realize the

common gate amplifier is shown as under in Fig . The following are the conditions that should be
6 .As can be seen the input source is applied to fulfilled at all the times for our amplifier to work
the source terminal of the NMOS transistor. The properly and for the transistors to stay in active
drain of this transistor is used to provide the region
necessary biasing current that is provided by the
.
current mirror circuit. The two PMOS transistors
For Q0 Vgs0 > Vds0 – Vth0
together with the biasing resistance Rbias
comprise the biasing network. The necessary For Q2 Vsd2 > Vsg2 -|Vth2|
voltage is provided by the voltage source Vdd where Vsg2 = Vdd – I*Rbais
which in our case is 1.2 V. The external load
capacitance has a value of 1pF. For Q3 Always in saturation given
All these values have been changed to obtain the Vgs3 > Vth3
desired Amplifier characteristics. The main All the values are changed in a proper
condition for the operation of the amplifier is synchronization to with each other so that the
that all the three transistors that have been relationship between different circuit parameters
employed here should stay in active region for can be observed and later on these values can be
proper amplification of the input signal. So the changed iteratively to obtain the desired
values cannot be random as this may drive one Amplifier characteristics.
of the three transistors to linear region and then
Amplification Process:The amplification
process can be shown by the following figure
.Now , in order to meet the voltage swing
greater than 1V, the limitation imposed on the
biasing voltage is that it should be greater than
0.5 in order to avoid clipping.The upper limit on
the biasing dc voltage is imposed by Q2 which
goes out of saturation as Vbs increases.
Fig.7 Amplification process considering the dc
bias voltage
Performance Considerations
To keep the power dissipation in the amplifier
below 1mV we have
P = V *I , where V = 1.2 V
So rms current value calculated from this
equation is 833.33 mV. While designing the
amplifier it should be taken into consideration
that the total current drawn from the voltage
source should not be more than 833.33 or
approximately 800mv.
In order to ensure the output Voltage swing
greater than 1V, the Dc bias should be set
greater than 0.5 V to avoid clipping of the output
because if the DC voltage is less than 0.5V then
for 1V swing the AC output will be clipped at
0V. So while setting the biasing it should be
considered that the Vdc at the output node should
not be less than 0.5 V.
Supposing an ideal current source.
I1 = µ*Cox*(W/L) (Vgs1 – Vth)2(1+λ *Vds(Vgs1
-Vth))
So as can be seen from the equation the current
is directly proportional to Vgs1. So we can use the
biasing voltage at gate of Q1 to increase or
decrease the current in the branch considering
that it should always stay in saturation. It can be
easily observed that increasing V gs will decrease
the Vds for a given current and increasing current
will also increase Vds for a given Vgs.The biasing
current in basically controlled by the current
mirror circuit. As is known the relationship
between the currents in both the branches is
given by
I2 = I3 * (W/L)2 /(W/L)3 ,
Also I1 = I2, so current can also be controlled by
the controlling W/L ratio of Q3.
Increasing Rbais increases the voltage across it
which in turn increases the Voltage at the gate of
Q2 , and as
Vgs2 = (|Vg2| –| Vs2|)
It decreases the Vgs of Q2 which in turn
decreases the I2 or I1.So we can decrease the
current by increasing the Rbais and vice versa.
Another way to increase the current is to
increase the (W/L)1 , (W/L)2, (W/L)3 and it is
evident from the current equation.
Ids = µnCoxW/L*(Vgs – Vth)*(1 – ƛ(Vds- (Vgs-
Vth)))
So to summarize the different ways to increase
current in the circuit are
1)By Increasing the (W/L) 2 Ratio
2)By Increasing the (W/L) 3 Ratio
3)By Increasing the (W/L) 1 Ratio
4)By Increasing the gate source voltage V GS1
5)By Decreasing the Rbias
And the opposite holds true if we want to
decrease the current
Effects of Changing current

Here we consider the effects of increasing the

current and the opposite will hold good for the
decreasing the current.

1)Bandwidth - The 3db frequency of the

common gate amplifier is given by

gds 2 ( g m 1+ g ds1 + g+ gb 1 ) + g gds 1 .

c out ( g m 1+ g ds1 + g−gb 1 ) +c db 1 ( g ds2 + g ) + c gs 1(g ds1 + g ds2 )

An approximation can be given by the following

expression

2 g ds1 λ I ds 1
W3db = = =
c out c out
which shows that the 3dB frequency i.e.
Bandwidth is directly proportional to the
current. Hence the Bandwidth increases with the
increase of current. So while designing the
amplifier it should be taken care that if greater
bandwidth is needed the current through the
circuit should also be increased.
2) Gain - The DC gain of the common gate
amplifier is given by
( gm 1 )
Av0 =
( gds 1+ g ds2 )
gm is proportional to the square root of the
current but the denominator term i.e. gds is
proportional to the current. So overall the gain is
inversely proportional to the square root of the
current. Hence Gain decreases with increasing
current.
3) Power – Power consumed by the circuit is
given by P = V*I
So power consumed is directly proportional to
current in the circuit. Hence increasing current
will increase power consumption.
An initial estimation was done by performing
the following parametric analysis for which the
following graph was obtained as shown in Fig 9
Fig 8: Ids Vs Vgs and Vout Vs Vgs for different Rbias
In this analysis, we plotted Ids and Vds1 vs Vgs and
then Rbias is assigned a parametric value to
change the values of current.. From this analysis,
various values of Ids and Vgs are observed for
which Vds > 0.5V and it was seen that increasing
biasing current will decrease the value of V ds1.
Then, the plot of 20log(Vout/Vin) is obtained vs
Ids using the calculator and it is observed that the
gain increases with current and the values of
current for gain > 30dB are noted. So, these
plots provide us the minimum and maximum
range of current to achieve the desired
performance. The next step is to increase the
value of Ids1 to achieve maximum gain by
varying different circuit parameters like Rbias,
W/L of the transistors.
Trade of between Bandwidth and Gain
It is observed that on increasing the current, the
gain decreases with increasing current whereas
the Bandwidth increases with increasing
current.So there is a tradeoff between gain and
Bandwidth. High gain and bandwidth cannot be
attained at the same time there is a tradeoff
between both. So we had to come up with a
particular biasing current and transistor sizes
that gave us the desired gain and the Bandwidth.
This was done by iteratively changing the
biasing current and sizing to get the optimal
performance.
This relationship between gain and bandwidth The transient response showing the output
obtained using the SpectrS simulator is shown in swing compard to the input ac signal is shown
Fig 9. The Bandwidth is greater than 1Ghz. below.

Fig 10: Output voltage swing

Power Dissipation: The power dissipation is

Fig 9: Plot of Ac Gain and Bandwidth calculated by using the value of rms current
flowing through the power supply. The peak
Results value of currewnt obtained is -637.24uA which
gives out the power to be .54mW and it meets
Required performance of the Common Gate
our power requirements.
amplifier was attained by iteratively changing
the Widths and Lengths of the transistors, R bias
and biasing voltages. The final values that gave Conclusion
the desired performance are given in Table 1.
Finally by adjusting and changing different
parameters as shown in the table above, the
values of gain , bandwidth and power obtained
Component Value are as follows
Q1 L=470nm
W=40µm Gain – 30.234dB
Q2 L=315nm Bandwidth – 1.102Ghz
W=20µm Power dissipation - .54mW
Q3 L=210nm
W=3 µm
Rbias 7 KΩ References:-
Vbias 371mV
References
Table 1 – Component Values obtained that
provide the desired Amplifier Characteristics [1] “Analog Integrated Circuit Design” By
Behzad Razavi

[2] Wikipedia.com
The input AC signal has an Amplitude of 70mV,
magnitude of 140 mV and Frequency of 20MHz.