Computer Architecture

Lecture 4
 Memory
• Memory has many types

• No one individual memory can fulfil all the requirements of computer system

• Memory of computer system can be classified into two main categories

• Internal Memory
• External Memory
 Memory System
Characteristics

• Memory exhibit
• Widest Range of Technology
• Organization
• Performance
• Cost
 Memory System
Hierarchy

• How much (Capacity)

• How fast (Speed)
• How expensive (Cost)

• Trade off
• Faster access time = greater cost
• Greater capacity = smaller cost
• Greater capacity = slower access time

• Solution: Rely on more than one memory technology & employ memory hierarchy
 Memory System
Levels
• Cache memory is designed to combine
expensive memory (high speed) with
large size (less expensive)

• Sits between normal memory & CPU

• Commonly located on same chip as

CPU
 Memory System
Levels

• Cache contains copy of portions of main memory. When processor

attempts to read a word of memory, a check is made to determine
of the word is in cache
• If Yes, Word is delivered to processor
• If No, Block of main memory is read into cache & then word is delivered

• Locality of Reference: Block of data is fetched into cache to satisfy a

single reference, it is likely that there will be future reference from
same memory location in block
 Memory System
Cache/Main Memory Structure
• Main memory consists of 2n addressable
words, each with unique address
 Memory System
Cache/Main Memory Structure

Tag help identify

from where the data
is coming from
 Memory System
Cache Organization

• Cache connects to processor via data,

control and address lines.
Memory System
Cache Design Parameters
 Memory System
Cache Address

• Logical:
• Stores data in virtual address
• Processor access directly
• Faster cache
• Must be flush on each switch

• Physical:
• Stores data using Memory
Management Unit
 Memory System
Cache Size

• Cost
• More cache more expensive

• Speed
• More cache faster speed
• Cache searching takes time
 Memory System
Mapping Function

• Algorithm needed to determine which main block occupy which

cache line

Set
Direct Associative
Associative
• Simplest technique • Permits each main • Compromise between
• Maps each block of memory block to be previous two
main memory into loaded into any line of techniques
only one possible cache
cache line • To determine whether
a block is in cache or
not, cache control
logic must examine
every line
 Memory System
Example: Direct Mapping

Main Memory Size: 64 words

Cache can store: 16 words

Block Size: 4 Words

Number of Blocks in Main

memory = 64 / 4
= 16 blocks
Number of lines in Cache =
Number of words/number of
words in block
= 16/4
=4
Memory System
Example: Direct Mapping

Number of address bits: 6 bits

Address: 000101

Address: Block 0001 01 Block

Number Offset
Memory System
Example: Direct Mapping

Least two significant bits

 Memory System
Example: Direct Mapping

6-bit address

Tag Block Offset

Line Number of Cache

 Memory System
Direct Mapping

• Each block of main memory maps to

only one cache line

• Memory size: 1 byte

• Block = 4 words (32 bit)
• Cache size: 214 lines (16K lines)
• Memory address = 24 bits (224)
• No of blocks: 224/214 = 256
Memory System
Direct Mapping
Memory System
Direct Mapping
 Memory System
Direct Mapping

• Pros:
• Simple
• Inexpensive

• Cons
• Fixed location to given block
• If program access 2 blocks that map the same line repeatedly then
caches misses are very high
• Victim Cache
• Remembers what is fetch and use again
 Memory System
Associative Mapping

• Associative mapping allow each main memory block to be loaded

into any cache line
• Memory address interpreted as tag and word
• Tag uniquely identifies block of memory
Memory System
Associative Mapping
Memory System
Associative Mapping

Tag: 000000h

Address Binary:
0000 0000 0000 0000 0000 0000

Shift Left shift two place

0000 0000 0000 0000 0000 0000

Address in Main Memory:

000000h
 Memory System
Associative Mapping

Tag: 0140AAh

Address Binary:
0000 0001 0100 0000 1010 1010

Shift Left shift two place

0000 0101 0000 0010 1010 1000

Address in Main Memory:

0502A8h

• Too expensive
• Tag is too large
 Memory System
Set Associative Mapping

• Cache divided into a number of

sets of equal size
• Each set contains a number of
lines
• Main memory block maps to
any line in a given set
 Memory System
Set Associative Mapping

Main memory
divided into 0 TAG
blocks 0
1

Cache has a To identify what

number of lines each line save
per set we use tag
 Memory System
Set Associative Mapping

SET
Decode a memory address number TAG
0
1

First check the set number, to figure out

0 0
which cache I have to look

Tag: tag number tell me which line I have 1 1

to retrieve

Word: allows me to find the word I need

Cache has a To identify what

number of lines each line save
per set we use tag
 Memory System
K-Way Set Associative Mapping

0 Several parallel directly mapped caches

0 1
1
• If I want to look up memory address

• Simultaneously tag of all caches are checked

• When tag is matched only that cache line is retrieved

• Only useful if K is small

 Memory System
Replacement Algorithms

• Space needs to be created for a new data block in a filled cache

• Direct mapping: One possible line for any particular block
• Associative & Set Associative a replacement algorithm is needed
• Hardware implemented
• Least Recently Used (LRU)
• First In First Out (FIFO)
• Least Frequently Used (LFU)
• Random
Memory System
Write Policy
 Memory System
Write Policy

• Write through
• Simplest technique
• All write operations to be made in main memory & cache
• Generates substantial memory traffic & may cause bottleneck

• Write back
• Minimized memory writes
• Updates are made only in cache
• Requires complex circuitry
 Memory System
Line Size

• Block of data is retrieved & placed in cache (it contains required word
+ near by location data also)
• Large block size means more useful data
• Larger block size mean increase in hit ratio
• Even larger block size will decrease hit ratio due to less probability of
reusing information

• Two ways
• Larger block size with reduce number of blocks
• Block become bigger each additional word become farther
 Memory System
Multilevel Caches

• High logic density enable caches on chip

• Faster than bus access
• Frees bus for other transfer

• Common to use both on and off chip cache

• L1 on chip while L2 off chip in SRAM
• L2 access faster than DRAM or ROM
• L2 often uses separate path

• Design become complicated due to placement, size, algorithm and write

policy
 Memory System
Unified vs Split Caches

• Dedicated cache for both instructions and data (Split) or one cache shared by
both instruction and data (unified)

• Advantages of unified
• Higher hit rate
• Balances load of instructions and data
• Simple design (as only one cache)

• Advantages of Split cache

• Eliminates cache contention between instruction and data
(execution unit)
• Assists in pipelining
Memory System
Cache Evolution
 Memory System
Intel vs ARM

Intel ARM
 Memory System
Useful Links
• https://www.youtube.com/watch?v=B4P9UNoEwRQ&ab_channel=venkatesanramachandran

• https://www.youtube.com/watch?v=VePK5TNgQU8&ab_channel=GateLecturesbyRavindrababuR
avula

• https://www.youtube.com/watch?v=U6gf2PRBmQY&ab_channel=JacobSchrum

• https://www.youtube.com/watch?v=B-EMkzv2AHE&ab_channel=JacobSchrum

• https://www.youtube.com/watch?v=OGDEsD3hdbk&list=RDCMUCCKhH1p0tj1frvcD70tEyDg&ind
ex=2&ab_channel=JacobSchrum

• https://course.ccs.neu.edu/com3200/parent/NOTES/cache-
basics.html#:~:text=The%20tag%20is%20kept%20to,not%20need%20to%20access%20RAM.