UNIVERSITY OF LIMERICK
OLLSCOIL LUIMNIGH
COLLEGE OF INFORMATICS & ELECTRONICS
DEPARTMENT OF ELECTRONIC & COMPUTER ENGINEERING
MODULE CODE:
MODULE TITLE:
SEMESTER:
DURATION OF EXAM:
LECTURER:
INSTRUCTIONS TO CANDIDATES:
DETERMINATION OF FINAL MARK:
ED5532
Computer Systems Architecture
Spring 2003
2½ Hours
Dr. Karl Rinne
Use of a non-programmable pocket calculator is
permitted.
Exam is composed of two parts: Part A and Part B.
Both parts must be completed.
Part A is composed of 60 multiple choice questions
worth a total of 60 marks. One mark is given for each
correct answer. Do not tick any answers on the exam
paper. Write the answers on your script (for example
1d, 2a, 3c, and so on). Negative marking does not
apply to this section.
Part B: Answer two questions out of B1, B2 and B3.
Questions B1, B2 and B3 carry the same number of
marks (50 marks each). Attempt no more than two
questions from this section.
Examination: 80%
Assignment: 20%
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ED5532: Comp. Sys. Architecture Spring 2003 Dr. Karl Rinne

Part A Multiple Choice Exam Marks:

One mark is given for each correct answer. Do not tick any answers on the exam
paper. Write the answers on your script (for example 1d, 2a, 3c, and so on). Total: 60
1) Which company designed and sold the first a) Apple
“PC”? b) Intel
c) IBM
d) Dell
2) Which of the following buses would not be a) Address bus
commonly found in a microprocessor b) Interrupt bus
system? c) Data bus
d) Control bus
3) Which of the following functional blocks a) Address decoding
would not be found in a typical b) Registers
microprocessor? c) Status bits
d) ALU
4) Which of the following load/retrieve a) FIFO
methods best describes a microprocessor b) LILO
stack? c) LIFO
d) Ring buffer
5) How many memory locations can be a) 16k
addressed by a microprocessor with 16 b) 64k
address lines? c) 1M
d) 16M
6) Which of the following control signals a) Refresh
would be provided to a static RAM b) DMA request
component? c) Write Enable
d) Interrupt request
7) Which of the following is required to erase a) Write signal
EPROM cells? b) High voltage programming pulse
c) Block erase signal
d) UV light
8) Which of the following is supported by the a) Memory-mapped I/O
Intel microprocessor architecture? b) Separate memory and I/O mapping
c) I/O-mapped memory
d) Random access mapping
9) Which of the following is an advantage of a) Faster I/O access
memory-mapped I/O? b) Smaller processor instruction set
c) Separate memory and I/O RD/WR-pins
d) Faster interrupt response
10) Which of the following is required to prevent a) Address decoding and device selection
signal contention in a system with multiple b) Wait states
memory devices connected to a data bus? c) Pull-up resistors
d) Termination
11) Tristate buffers are often used to make sure a) High-impedance state
that unselected devices have their data b) Logic 1 state
outputs placed in the… c) Logic 0 state
d) Input state
12) The 27C4002 is a 4Mb EPROM device a) 8
organised as 256kb x 16. How many address b) 16
bus lines do you expect the device to have? c) 18
d) 32

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13) Integrated logic circuit 74HC138 is a 3-to-8 a) Tristate buffer

decoder. In computer systems what is the b) Clock generation
74HC138 commonly used for? c) Priority decoding
d) Address decoding
14) The time it takes a memory device to a) Access time
respond to valid address and chip-enable b) Set-up time
signals is called… c) Hold time
d) Acknowledge time
15) Which of the following is inserted by the a) Stop state
processor to allow the memory more time to b) Delay cycle
respond? c) Wait state
d) Burst cycle
16) Interrupts can be triggered by a) Address decoder
b) Tristate buffers
c) Hardware as well as software
d) Slow memory devices
17) How many bytes are in a 64kB? a) 64000
b) 64004
c) 65535
d) 65536
18) Which of the following techniques supports a) DMA
fast transfer of blocks of data? b) NMI
c) HDL
d) FIFO
19) Which of the following operating modes is a) Real mode
entered by Intel x86 processors after reset? b) Protected mode
c) Virtual real mode
d) RISC mode
20) The Intel 8086 is a… a) 8-bit microprocessor
b) 16-bit microprocessor
c) 20-bit microprocessor
d) 32-bit microprocessor
21) In native mode, the Intel 80386 is a… a) 8-bit microprocessor
b) 16-bit microprocessor
c) 20-bit microprocessor
d) 32-bit microprocessor
22) For integer data which data format is used by a) Big endian
Intel x86 microprocessors? b) Medium endian
c) Little endian
d) Floating point
23) The 8086 microprocessor uses an instruction a) Determine the priority of instructions
queue in order to… b) Increase processing performance
c) Implement a super-scalar architecture
d) Avoid data inter-dependency
24) Which of the following tasks is not a) Instruction fetch
performed by the 8086 BIU (Bus Interface b) Instruction decoding
Unit)? c) Operand fetch
d) Result write-back
25) How much memory can a standard 8086 a) 64kB
processor address in real mode? b) 1MB
c) 16MB
d) 4GB
26) Assume Intel 8086 real mode: The offset is a) 0B524h
24h. The segment register contains 0B500h. b) 0B5024h
What is the resulting physical address? c) 24B5h
d) 240B5h

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27) Which support circuits would you not find in a) Cache controller
a 8086 minimum system? b) Clock generator
c) Bus controller
d) Transparent latch
28) What purpose does the #BHE signal serve in a) Enables access to high byte of word
an 8086 system? b) Enables access to low byte or word
c) Enables access full word
d) Bus halt enable
29) Why does the 8086 have a multiplexed a) Multiplexing increases performance
address and data bus? b) Multiplexing allows for slower memory
c) Multiplexing simplifies external circuitry
d) Multiplexing saves processor pins
30) The 8086 has a multiplexed address and data a) Transparent latches
bus. De-multiplexing is typically achieved b) Bus transceivers
using… c) Bus controllers
d) Clock generators
31) An 8086 bus cycle takes at least 4 clock a) 4Mb/s
cycles to complete. If the processor is b) 4MB/s
clocked at 4MHz, what is the maximum data c) 2MB/s
rate of the data bus? d) 20MB/s
32) Which of the following is not a feature of the a) Fully 8086 backwards compatible
Intel 80286 processor? b) 16MB addressable physical memory
c) Support of real mode and protected mode
d) 32-bit general purpose registers
33) Protected mode in the 80286 was a) Multitasking operating systems
implemented to support… b) Overheating of the processor
c) Cache memories
d) Internet security
34) How much physical memory can be a) 64kB
addressed by an 80386 processor in the b) 1MB
native mode? c) 16MB
d) 4GB
35) What is the main purpose of an 80387 co- a) Control of cache memory
processor? b) Fast hard-disk access
c) Fast floating point operations
d) Increased physical memory
36) Which of the following techniques was a) RISC
extensively used to implement the 80386? b) Micro-encoding of machine instructions
c) Hard-wired machine instructions
d) Harvard architecture
37) Which of the following blocks would not be a) Microcode execution unit
found on a traditional RISC microprocessor? b) Instruction pipeline
c) Large register bank
d) ALU
38) What can be said about processors featuring a) offer on-chip networking support
a super-scalar architecture? They… b) support MMX instructions
c) have multiple instruction pipelines
d) support DDR memory
39) Which of the following problems is regularly a) Data and register dependency
encountered when dealing with instruction b) Large stack sizes
pipelines? c) Micro-encoded instructions
d) Hard-wired instructions
40) The Intel Pentium processor is a… a) 16-bit processor
b) 32-bit processor
c) 64-bit processor
d) 128-bit processor

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41) What is the width of the external data bus of a) 16-bit

a Pentium processor? b) 32-bit
c) 64-bit
d) 128-bit
42) Which of the following pipelines would not a) Integer pipeline u
be found in a Pentium processor? b) Integer pipeline v
c) Floating-point pipeline
d) Data pipeline
43) The integer instruction pipelines of a a) Pairing rules
Pentium processor are filled according to b) Twin rules
c) Instruction priority levels
d) Data dependency rules
44) Under best conditions how many instructions a) 1
can a Pentium processor complete in ten b) 5
clock cycles? c) 10
d) 20
45) The Pentium BTB predicts whether a branch a) Processor reset
will be taken or not. What’s the consequence b) Pipeline flush
of a wrong BTB prediction? c) Software exception
d) NMI
46) Pentium BTB branch predictions are based a) EAX register content
on what? b) Branch repetition rate
c) Status flags
d) Past branch history
47) Which of the following features does not a) In-circuit programmable
apply to flash memory devices? b) Electrically erasable
c) Volatile
d) Non-volatile
48) Which of the following buses would not be a) PCI bus
found in a recent standard PC? b) MCA bus
c) ISA bus
d) Front-side bus
49) Which of the following features does not a) Asynchronous transfer mode
apply to the PCI bus? b) Processor-independent
c) Can be used in multi-processor systems
d) Support of PnP
50) Where in the system are PCI agents typically a) Within the processor
located? b) In devices connected through USB
c) Within the PCI bridge
d) On the motherboard
51) What is the maximum single-read data rate a) 11MB/s
for a 32-bit PCI bus clocked at 33MHz? b) 33MB/s
c) 44MB/s
d) 66MB/s
52) Which of the following features applies to a) Tightly coupled to the PCI bus
the AGP bus? b) Intended exclusively for visual devices
c) Slower and lower cost than PCI
d) Serial data transmission
53) Which of the following chip-set architectures a) North/South bridge architecture
is used in recent PCs? b) Hub architecture
c) East/West bridge architecture
d) VESA architecture
54) In a Pentium processor the paging unit splits a) Page directory base address
up a linear address into three components. b) Page directory entry
Which of the following is not a component? c) Page table entry
d) Page offset address

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55) Which unit is used to increase the speed of a) Translation lookaside buffer
access to memory pages? b) Descriptor cache
c) Instruction pipeline
d) Page directory
56) For which of the following is the Pentium a) Highly reliable systems
data bus optimised? b) DDR memory devices
c) Low cost
d) Fast cache line fills
57) Which mode of data transfer from memory a) Burst mode
to cache is used by the Pentium processor? b) DDR mode
c) Synchronous transfer mode
d) Asynchronous transfer mode
58) What does MMX stand for? a) Memory management extensions
b) Multi-media extensions
c) Machine management extension
d) Mobile machine extension
59) What is the width of MMX registers? a) 16-bit
b) 32-bit
c) 64-bit
d) 128-bit
60) Which of the following units would not be a) Level-1 cache
found within a Pentium II processor? b) Level-2 cache
c) MMX
d) USB Hub

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Part B Marks:
Answer any two questions out of B1, B2 and B3 50 per
question

B1: Cache Memory

B1.1 How does a cache improve the performance of a Personal Computer?

B1.2 What type of memory component (DRAM or SRAM) is commonly used for the
implementation of cache memory? Why? What is the drawback of this type of
memory?

B1.3 What are advantages and disadvantages of unified cache for code and data?

B1.4 Approximately what cache hit-rate would you expect from a typical cached system
running typical software?

B1.5 What is a cache line? What’s a typical cache line size? How does this cache line size
correspond to the data bus width and data transfer mode of a Pentium processor?

B1.6 What is the purpose of the MESI protocol? Briefly explain each of the four states
used in the MESI protocol.

B1.7 Consider a dual-processor system with two processors, A and B. Each of the
processors has an on-chip cache. The processors share a common main memory.
After being modified a cache line in Processor A is in the M state as shown in Figure
1. What will happen if processor B attempts to read from an address in main
memory that corresponds to an address in the M-state cache line of Processor A?
Use sketches to illustrate the sequence of events that follows.

Processor A Processor B
CPU, Registers 3 CPU, Registers

Cache 2 3 Cache
Cache Line State: M Cache Line State: I

Shared Main 2
Memory

Figure 1: Dual Processor System with Multiple Cache Memories

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B2: Intel Segmentation and Paging

B2.1 Explain the relationship between logical addresses, linear addresses, and physical
addresses.

B2.2 Segmentation in real mode: Briefly discuss the difference between an 8086 and a
Pentium processor.

B2.3 Assume operation in protected mode. How much memory (in kB) is required for a
fully populated descriptor table? See Figure 2 for formats of segmentation registers
and descriptors.

B2.4 Consider instruction: MOV AL, DS:[BX]

Assume operation in protected mode. See the example system shown in Figure 3
with the selected descriptor table. Determine which data byte is moved into register
AL. Document every step of your solution.

B2.5 For the shown example system explain what would happen if BX contained 000Ch
when instruction MOV AL, DS:[BX] is encountered.

B2.6 Segmentation in protected mode could negatively impact processing performance.

What has been done in the Pentium processor to get around this problem?

Selector [12:0] TI RPL[1:0] 7 Base [31:24] G D O A Lim[19:16] 6

5 Access [7:0] Base [23:16] 4
3 Base [15:0] 2
1 Lim [15:0] 0

Figure 2: Segmentation - Segment register format and descriptor format

BX GDT Memory System

00h 04h 00h 00h 01h 0CAh Adr 100016h
Descriptor 2

92h 10h 22h 10h Adr 100014h

00h 04h 10h 02h Adr 100012h
DS 00h 0Bh 0FFh 0E0h Adr 100010h
00h 00h 0F1h 00h Adr 10000Eh
Descriptor 1

00h 08h
92h 10h 92h 8Fh Adr 10000Ch
00h 00h 1Eh 20h Adr 10000Ah
00h 05h 21h 47h Adr 100008h
00h 00h 43h 30h Adr 100006h
Descriptor 0

92h 10h 0A5h 41h Adr 100004h

00h 10h 13h 17h Adr 100002h
00h 07h 55h 0AAh Adr 100000h

GDT Base Address

Figure 3: Segmentation – Example System

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B3: PC Architecture and Buses

B3.1 Draw a block diagram of the north/south bridge chipset architecture. Describe the
circuit blocks in the architecture.

B3.2 What are the advantages of the hub architecture compared to the north/south bridge
architecture?

B3.3 What are the advantages of the USB bus compared to earlier serial buses?

B3.4 Discuss some of the major attributes of the physical link of the USB bus?

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