K. J.

Somaiya College of Engineering, Mumbai-77

(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics Engineering

Hardware Description Language Lab

Course Name: Semester: IV
(2UXL401)

Date of Performance: 11/02/2021 Batch No: A3

Faculty Name: Prof. Lekhadas Roll No: 2022011

Faculty Sign & Date: Grade/Marks: /25

Experiment No: 1
Title: Study of basic VHDL code: Adder (Dataflow)

Aim and Objective of the Experiment:

Write a VHDL code

a) To implement a half adder.
b) A full adder using half adder
c) A 4-bit adder using full adder.
Write a testbench to verify your results for half adder and four bit adder Implement the full adder on
CPLD.

To study basic structure of VHDL code and to understand use of test bench for simulation.
To know the process for implementation on CPLD.

COs to be achieved:

CO 1: Use basic Concurrent and Sequential statements in VHDL and write codes for simple
applications
CO 2: Test a VHDL code and verify the circuit model.
CO 3: Synthesize and Implement the designed circuits on CPLD/ FPGA.

Work to be done

Upload VHDL codes for half adder, full adder ( structural) and four-bit adder (structural) and test
bench for half adder and 4-bit adder.

HDL Laboratory Semester: IV Academic Year: 2020-21

Roll No:2022019
 K. J. Somaiya College of Engineering, Mumbai-77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics Engineering

VHDL codes-

Half Adder-

library ieee;
use ieee.std_logic_1164.all;

entity halfadd is
port (A,B: in std_logic;
S,C: out std_logic);
end halfadd;

architecture halfadd_arch of halfadd is

begin
S <=A xor B;
C <=A and B;
end halfadd_arch;

Roll No:2022019
 K. J. Somaiya College of Engineering, Mumbai-77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics Engineering

Full Adder-

library ieee;
use ieee.std_logic1164.all;

entity full_adder is
port (A, b,Cin: in std_logic;
Sum,Carry: out std_logic;
end full_adder;

architecture fa_arch of full_adder is

component half_adder is
port(A,B: in std_logic;
S,C: out std_logic);
end component;
signal S,C1,C2: std_logic;
begin
HA1: half_adder port map(A,B,S,C1);
HA2: half _adder port map(S,Cin,Sum,C2);
Carry<=C1 or C2;

end fa_arch;

HDL Laboratory Semester: IV Academic Year: 2020-21

Roll No:2022019
 K. J. Somaiya College of Engineering, Mumbai-77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics Engineering

4 bit Adder-

LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BIT_ADDER is
port( a, b, cin : in STD_LOGIC;
sum, cout : out STD_LOGIC );
end BIT_ADDER;

architecture BHV of BIT_ADDER is

begin

sum <= (not a and not b and cin) or

(not a and b and not cin) or
(a and not b and not cin) or
(a and b and cin);

cout <= (not a and b and cin) or

(a and not b and cin) or
(a and b and not cin) or
(a and b and cin);
end BHV;

LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity add4 is
port( a, b : in STD_LOGIC_VECTOR(3 downto 0);
ans : out STD_LOGIC_VECTOR(3 downto 0);
cout : out STD_LOGIC );
end add4;

architecture STRUCTURE of add4 is

component BIT_ADDER
port( a, b, cin : in STD_LOGIC;
sum, cout : out STD_LOGIC );
end component;

signal c0, c1, c2, c3 : STD_LOGIC;

begin
c0 <= '0';
b_adder0: BIT_ADDER port map (a(0), b(0), c0, ans(0), c1);
b_adder1: BIT_ADDER port map (a(1), b(1), c1, ans(1), c2);
b_adder2: BIT_ADDER port map (a(2), b(2), c2, ans(2), c3);
b_adder3: BIT_ADDER port map (a(3), b(3), c3, ans(3), cout);
END STRUCTURE;
Roll No:2022019
 K. J. Somaiya College of Engineering, Mumbai-77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics Engineering

Test-Bench-

Half Adder-

library ieee;
use ieee.std_logic_1164.all;

entity halfadd_tb is
end halfadd_tb;

architecture halfadd_tb_arch of halfadd_tb is

signal A : std_logic; signal B : std_logic; signal C : std_logic; signal S :

std_logic;

component halfadd is
port (A : in std_logic;B : in std_logic;
C : out std_logic;S : out std_logic);
end component;

begin
U1 : halfadd port map(A => A, B => B, C => C, S=> S);

process
Roll No:2022019
 K. J. Somaiya College of Engineering, Mumbai-77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics Engineering
begin
A<='0'; B<='0'; wait for 10 ns;
A<='0'; B<='1'; wait for 10 ns;
A<='1'; B<='0'; wait for 10 ns;
A<='1'; B<='1'; wait for 10ns;

end process
end halfadd_tb arch;

Full Adder-

library IEEE;
use IEEE.std_logic_1164.ALL;
entity fulladd_tb is

end fulladd_tb;
architecture fulladd_tb_arch of fulladd_tb is
component fulladd is
port(A,B,Cin:IN std_logic;
Sum,Carry : OUT std_logic);
end component;
signal A,B,Cin,Sum,Carry:std_logic;

Roll No:2022019
 K. J. Somaiya College of Engineering, Mumbai-77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics Engineering

begin
u1: fulladd port map(A=>A,B=>B,Cin=>Cin,Sum=>Sum,Carry=>Carry);
process
begin
A<='0';B<='0';Cin<='0';wait for 10ps;
A<='0';B<='0';Cin<='1';wait for 10ps;
A<='0';B<='1';Cin<='0';wait for 10ps;
A<='0';B<='1';Cin<='1';wait for 10ps;
A<='1';B<='0';Cin<='0';wait for 10ps;
A<='1';B<='0';Cin<='1';wait for 10ps;
A<='1';B<='1';Cin<='0';wait for 10ps;
A<='1';B<='1';Cin<='1';wait for 10ps;
end process;
end fulladd_tb_arch;

Roll No:2022019
 K. J. Somaiya College of Engineering, Mumbai-77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics Engineering

4 bit Adder-
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;

entity fourbitadder_tb isend

fourbitadder_tb;

architecture fourbitadder_tb_arch of fourbitadder_tb is

component fourbitadder

port(
A: in STD_LOGIC_VECTOR(3 downto 0); B: in
STD_LOGIC_VECTOR(3 downto 0); Carry: out
STD_LOGIC;
Sum: out STD_LOGIC_VECTOR(3 downto 0)
);
end component;

signal A,B,Sum:STD_LOGIC_VECTOR(3 downto 0):="0000"; signal

Carry:STD_LOGIC;
begin
ul: fourbitadder port map(A,B,Carry,Sum);
process
begin

for i in 0 to 15 loop
A<=A+1;

for j in 0 to 15 loop
B<=B+1;
wait for 10ns;end
loop;
end loop; end
process;
end fourbitadder_tb_arch;

Roll No:2022019
 K. J. Somaiya College of Engineering, Mumbai-77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics Engineering

Post Lab Subjective/Objective type Questions:

Upload Answer of following question before coming to next laboratory.

Q1. Analyze the following code and write its output.
library ieee;
use ieee.std_logic_1164.all;
entity xyz is
port ( x,y: in std_logic;
z : out std_logic);
end entity;
architecture arch_xyz of xyz is
begin
z <= '0' when (x=’1' and y='1') else
'0'when (x='0' and y='0')else

Roll No:2022019
 K. J. Somaiya College of Engineering, Mumbai-77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics Engineering

'1';
end arch_xyz;

Ans:
The given code is similar to XOR gate as the output ‘z’ is low (0) if both the inputs ‘x’ and ‘y’ are
same i.e. if both of them are high or if both of them are low at the same time. Output is high if ‘x’
and ‘y’ are different.

Q 2 Write a test bench for the above code

library ieee;
use ieee.std_logic_1164.all;

entity xyz_tb is
end xyz_tb;

architecture xyz_tb_arch of xyz_tb is

component xyz is
port(
x,y:in std_logic;
z: out std_logic);
end component;

signal x,y,z: std_logic;

begin
uut: xyz port map(x,y,z);
process begin

x <= '0';
y <= '0';
wait for 20ns;

x <= '0';
y <= '1';
wait for 20ns;

x <= '1';
y <= '0';

Roll No:2022019
 K. J. Somaiya College of Engineering, Mumbai-77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics Engineering

wait for 20ns;

x <= '1';
y <= '1';
wait for 20ns;
end process;
end;

Conclusion:
We learnt how to use Quartus and the basics of VHDL by performing simulations for Half adder,
Full adder and a 4 bit adder. Also, to simulate the waveform output by writing test bench and
using Modelsim.

Signature of faculty in-charge with Date:

Roll No:2022019