D2X533BW-X256

PDRB-29998-X117-01

DATA SHEET

Memory Module Part Number

D2X533BW-X256

BUFFALO INC.
(1/8)
 D2X533BW-X256
PDRB-29998-X117-01

1. Description

DDR2-533 144pin 32bit DIMM

EP2-2100/CL=4,tRCD=4,tRP=4

2. Module Specification

Item Specification
Capacity 256MByte
Physical Bank(s) 1
Module Organization 64M x 32bit
Module Type Unbuffered NonECC
EP2-2100/CL=4, tRCD=4, tRP=4 (266MHz Double Data Rate)
Speed Grade
EP2-1600/CL=3, tRCD=3, tRP=3 (200MHz Double Data Rate)
Interface SSTL_18
Power Supply Voltage 1.8V±0.1V
Burst Lengths 4,8
DRAM Organization 64M x 16bit DDR2 SDRAM
PCB Part No. 2DXA2GF-A
PCB Layer 6 Layers
144pin GOLD Flash Plating
Contact Tab
Ni : min 2.00µm / Au : min 0.05µm
Serial PD Support

3. Mechanical Design

Item Reference standard

Mechanical Design and Pinout DDR2 144Pin 32bit DIMM
(PDRB-29998-X086-**)
Mechanical Design
Y(PCB Height) : 30.00 ± 0.15mm
Z1 : 3.60mm
Z2 : Undefined

4. Block Diagram

Item Reference standard

Block Diagram
Block Diagram DDR2 Unbuffered 32bit DIMM(x16bitDRAM 1Bank)
(PDRB-29998-X082-**)

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5. Electrical Specifications
5.1 Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage VCC -1.0～2.3 V
Power supply voltage for Output VCCQ -0.5～2.3 V
Input and output voltage VIN,VOUT -0.5～2.3 V
Operating case surface temperature TC 0～85 °C
Storage temperature TSTG -55～100 °C

5.2 Recommended Operating Conditions

Parameter Symbol MIN MAX Unit
Power supply voltage VCC,VCCQ 1.7 1.9 V
Power supply voltage for SPD VCCSPD 1.7 3.6 V
Reference Voltage VREF 0.49x VCCQ 0.51x VCCQ V
Termination Voltage VTT VREF-0.04 VREF+0.04 V
DC input logic high voltage VIH(dc) VREF+0.125 VCCQ+0.3 V
DC input logic low voltage VIL(dc) -0.3 VREF-0.125 V
AC input logic high voltage VIH(ac) VREF+0.250 —— V
AC input logic low voltage VIL(ac) —— VREF-0.250 V
AC differential input voltage VID(ac) 0.5 VCCQ+0.6 V
AC differential cross point voltage (input) VIX(ac) 0.5*VCCQ-0.175 0.5*VCCQ+0.175 V
AC differential cross point voltage (output) VOX(ac) 0.5*VCCQ-0.125 0.5*VCCQ+0.125 V

5.3 Pin Capacitances

Maximum Pin
Parameter Symbol Unit
Capacitance
CK0, /CK0 CICK0 8 pF
CK Input Pin Capacitance
CK1, /CK1 CICK1 8 pF
/S0 CIS0 4 pF
/S Input Pin Capacitance
/S1 CIS1 —— pF
CKE0 CICKE0 4 pF
CKE Input Pin Capacitance
CKE1 CICKE1 —— pF
ODT0 CIODT0 4 pF
ODT Input Pin Capacitance
ODT1 CIODT1 —— pF
DQS0~DQS3 CIDQS 4 pF
DQS,/DQS Input,Output
/DQS0~/DQS3 CIDQSN 4 pF
Pin Capacitance
DM0~DM3 CIDQS 4 pF
DQ Input,Output Pin Capacitance DQ0~DQ31 COUT 4 pF
Other Input Pin Capacitance A,BA,/RAS,/CAS,/WE CIN 7 pF

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5.4 D.C. Characters

Parameter Symbol Value Unit Test Condition
Operating one bank active
Operationg Current for One Bank Active-precharge ICC0 MAX 520 * mA precharge current :
CKE=high
Operating one bank active
Operationg Current for One Bank Operation ICC1 MAX 680 * mA read-precharge current :
CKE=high, BL4, AL0
Precharge power-down current :
Precharge Power-down Standby Current ICC2P MAX 60 * mA All banks idle, CKE=low
Precharge quiet standby current :
Precharge Quiet Standby Current ICC2Q MAX 180 * mA All banks idle, CKE=high
Precharge standby current :
Precharge Standby Current ICC2N MAX 200 * mA All banks idle, CKE=high
Active power down current
ICC3P-F MAX 160 * mA (Fast PDN Exit) : All banks open,
CKE=low, MRS(12)=0
Active Power-down Standby Current
Active power down current
ICC3P-S MAX 100 * mA (Slow PDN Exit) : All banks open,
CKE=low, MRS(12)=1
Active standby current :
Active Standby Current ICC3N MAX 340 * mA All bank open, CKE=high
Operating burst write current :
Operating Current for Burst Write ICC4W MAX 1240 * mA All banks open, Continuous burst
writes, CKE=high, BL4, AL0
Operating burst read current :
Operating Current for Burst Read ICC4R MAX 1220 * mA All banks open, Continuous burst
reads, CKE=high, BL4, AL0
Auto Refresh Current ICC5 MAX 1280 * mA Burst refresh current : CKE=high
Self refresh current :
Self Refresh Current ICC6 MAX 60 * mA
CK=0V, /CK=0V, CKE ≤ 0.2V
Operating bank interleave
Operating Current for Four Bank Operation ICC7 MAX 2000 * mA read current : All bank interleaving
reads, BL4, AL=tRCD-1tCK
MIN -20 * µA
Input Leakage Current ILI VSS ≤ VIN ≤ VCC
MAX 20 * µA
Output High Current IOH MIN -13.4 * mA VOH = 1,420mV
Output Low Current IOL MIN 13.4 * mA VOL = 280mV

* : No guarantee against this value.

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5.5 A.C. Timing Characters

Parameter Symbol MIN MAX Unit
Clock cycle time /CAS Latency = 3 5,000 8,000
tCK ps
/CAS Latency = 4 3,750 8,000
Clock high level width tCH 0.45 0.55 ck
Clock low level width tCL 0.45 0.55 ck
DQ output access time from CK /CAS Latency = 3 -600 600
tAC ps
/CAS Latency = 4 -500 500
DQ DM input setup time relative to DQS tDS 100 —— ps
DQ DM input hold time relative to DQS tDH 225 —— ps
Data hold skew factor tQHS —— 400 ps
DQS output access time from CK , /CK tDQSCK -450 450 ps
DQS input high pulse width tDQSH 0.35 —— ck
DQS input low pulse width tDQSL 0.35 —— ck
DQS falling edge to CK setup time tDSS 0.2 —— ck
DQS falling edge to CK hold time tDSH 0.2 —— ck
DQS-DQ skew for DQS and associated DQ signals tDQSQ —— 300 ps
Read preamble tRPRE 0.9 1.1 ck
Read postamble tRPST 0.4 0.6 ck
Write preamble tWPRE 0.35 —— ck
Write postamble tWPST 0.4 0.6 ck
Write command to first DQS latching transition tDQSS WL-0.25 (*1) WL+0.25 (*1) ck
Address,command input setup time tIS 250 —— ps
Address,command input hold time tIH 375 —— ps
Active to read or write delay tRCD 15 —— ns
Precharge command period tRP 15 —— ns
Active to precharge command (tCK<5,000ps) 45 70k
tRAS ns
(tCK>=5,000ps) 40 70k
Active-active/auto refresh clock period (tCK<5,000ps) 60 ——
tRC ns
(tCK>=5,000ps) 55 ——
Active to active command period tRRD 10 —— ns
Cas to cas command delay tCCD 2 —— ck
Write recovery time tWR 15 —— ns
Mode register set command cycle time tMRD 2 —— ck
Minimum time clocks remains ON after CKE
tDELAY tIS+tCK+tIH —— ns
asynchronously drops low
Average periodic refresh interval tREFI —— 7.8 µs
Refresh to active/refresh command time tRFC 127.5 70k ns
Exit self refresh to a non-read command tXSNR tRFC +10 —— ns
Exit self refresh to a read command tXSRD 200 —— ck
Exit prechatge power down to any non-read command tXP 2 —— ck
Exit active power down to read command tXARD 2 —— ck
Exit active power down to read command
tXARDS 6-AL (*2) —— ck
(Slow exit, Lower power)
CKE minimum pulse width (high and low pulse width) tCKE 3 —— ck
ODT turn-on delay tAOND 2 ck
ODT turn-on tAON tAC(Min) tAC(Max)+1 ns
2tCK
ODT turn-on (Power-Down mode) tAONPD tAC(Min)+2 ns
+tAC(Max)+1
ODT turn-off delay tAOFD 2.5 ck
ODT turn-off tAOF tAC(Min) tAC(Max)+0.6 ns
2.5tCK
ODT turn-off (Power-Down mode) tAOFPD tAC(Min)+2 ns
+tAC(Max)+1
ODT to power down entry latency tANPD 3 —— ck
ODT power down exit latency tAXPD 8 —— ck
*1 : WL=Write Latency
*2 : AL=Additive Latency

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6. Serial Presence Detect (SPD) Data Structure

Byte No. Function Hex Value Function Supported
0 Defines # of bytes written into serial memory at module manufacturer 80 128 Bytes
1 Total # of bytes of SPD memory device 08 256 Bytes
2 Fundamental memory type (FPM, EDO, SDRAM..) 08 DDR2-SDRAM
3 # of row addresses on this assembly 0D 13
4 # Column Addresses on this assembly 0A 10
5 # Module Banks on this assembly 60 1Bank
6 Data Width of this assembly 20 32bits
7 Reserved 00 Undefined
8 Voltage interface standard of this assembly 05 SSTL-18
9 SDRAM Cycle time (highest CAS latency) 3D 3,750ps (CL=4)
10 SDRAM Access from Clock (highest CAS latency) 50 500ps (CL=4)
11 DIMM Configuration type (non-parity, ECC) 00 NON-ECC
12 Refresh Rate/Type 82 7.8µs
13 Primary SDRAM Width 10 x16 bit
14 Error Checking SDRAM width 00 Non Use
15 Reserved 00 Undefined
16 Burst Lengths Supported 0C Burst Lengths (4,8)
17 # of Banks on Each SDRAM Device 08 8Bank
18 CAS# Latency 18 CAS Latency =4,3
19 Reserved 00 Undefined
20 DIMM Type Information 00 Non Support
21 SDRAM Module Attributes 00 Normal
22 SDRAM Device Attributes: General 01 Weak drive support
23 SDRAM Cycle time (2nd highest CAS latency) 50 5,000ps(CL=3)
24 SDRAM Access from Clock (2nd highest CAS latency) 60 600ps(CL=3)
25 SDRAM Cycle time (3rd highest CAS latency) 00 N/A (CL=2)
26 SDRAM Access from Clock (3rd highest CAS latency) 00 N/A (CL=2)
27 Minimum Row Precharge Time (tRP) 3C 15 ns
28 Row Activate to Row Activate Min. (tRRD) 28 10 ns
29 RAS to CAS Delay Min (tRCD) 3C 15 ns
30 Minimum RAS Pulse Width (tRASmin) 2D 45ns
31 Density of each bank on module 40 256MB
32 Command and Address signal input setup time 25 250ps
33 Command and Address signal input hold time 37 375ps
34 Data signal input setup time 10 100ps
35 Data signal input hold time 22 225ps
36 Write recovery time (tWR) 3C 15ns
37 Internal Write to Read command delay (tWTR) 1E 7.5ns
38 Internal Read to Precharge command delay (tRTP) 1E 7.5ns
39 Memory Analysis Probe charactristics 00 TBD
40 Extension of Byte41 tRC and Byte42 tRFC 06 Extension of Byte41,42
41 SDRAM Device Minimum Active to Active/Auto Refresh Time(tRC) 3C 60ns
42 SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh(tRFC) 7F 127.5ns
43 SDRAM Device Maximum device cycle time(tCKmax) 80 8,000ps
44 SDRAM Device Maximum skew between DQS and DQ signals(tDQSQ) 1E 300ps
45 DDR SDRAM Device Maximum Read DataHold Skew Factor(tQHS) 28 400ps
46 PLL Relock Time 00 Undefined
47-61 Superset Information (may be used in future) 00 Undefined
62 SPD Data Revision Code 10 Rev.1.0
63 Checksum for bytes 0-62 D2 Checksum
64-66 Manufacturer’s JEDEC ID code per JEP-106 7F
67 83
BUFFALO
68-71 00
72 Manufacturing Location 01
73-90 Manufacturer’s Part Number 20 BLANK
91-92 Revision Code 00 Undefined
93-94 Manufacturing Date ―― Undefined
95-98 Assembly Serial Number ―― Undefined
99-127 Manufacturer Specific Data ―― Undefined
128+ Unused storage locations ―― Undefined

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7. Packing/Label Specification

Item Reference standard

Packing/Label Specification –for SO-DIMM
Packing/Label Specification
(PDRB-28998-X063-xx)

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8. Revision History

Rev. Date Changes Issued

01 Jun.13.2007 ------------- M.Goto(D05)

BUFFALO INC.
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