1
Multipulse AC-DC Thyristor Converter with DC
Bus Current Shaper
Maryclaire Peterson, Student Member, IEEE, and Brij N. Singh, Member, IEEE
Abstract--This paper proposes an active current shaper for a
12-pulse thyristor converter, termed a load compensator
(LSTATCOM). The LSTATCOM injects compensation current
through a split winding interphase reactor connected on dc bus
of the 12-pulse ac-dc converter. It is desired that the
LSTATCOM provides sinusoidal shaping of the source currents
for variations in the output load as well as changes in the output
voltage requirements. For voltage sensitive dc loads, the
LSTATCOM should also be capable of compensating voltage sag
and voltage swell. To observe the dynamic and steady state
performance of the LSTATCOM based 12-pulse thyristor
converter, a detailed mathematical model of the system is derived
and the corresponding simulation models are developed. A
thorough investigation of the performance results reveals that the
proposed LSTATCOM provides sinusoidal shaped source
currents for a 12-pulse converter operating under a variety of
operating conditions and requirements.
Index Terms--Multipulse converter, hybrid current shaping,
harmonic reduction, current injection, LSTATCOM
I. INTRODUCTION
A CTIVE and passive harmonic filtering techniques have
been proposed to satisfy power quality standards [1-2]
when nonlinear loads are employed in different applications.
Passive filters are attractive solutions due to their low cost,
simplicity, and control-less operation [3-5]. These filters are
tuned to attenuate certain harmonics present in the line
current. However, passive filters suffer from the problem of
mistuning when the load deviates from the designed value [6].
On the contrary, active filters do not suffer from mistuning
and can provide simultaneous or selective compensation for
all harmonics [7-9]. Active filters are controlled power
converters connected either in series or in parallel depending
on the output voltage requirement. The voltage and current
waveforms generated by active filters cancel the harmonics
produced by the nonlinear loads. Nevertheless, cost,
complexity, control system design, and reliability are some of
the major drawbacks of active filters. Consequently, in place
of the standard six-pulse rectifier, 12-pulse converters are
gaining increased acceptance due to their simplicity,
Maryclaire Peterson and Brij N. Singh are with the Dept. of Elect. Eng. and
Comp. Sc., Tulane University, New Orleans, LA 70118, USA (e-mails:
mpeters2@tulane.edu, singh@eecs.tulane.edu). Maryclaire Peterson thanks NSF
for financial support through Graduate Research Fellowship program.
1-4244-1298-6/07/$25.00 ©2007 IEEE.
robustness, reliability, and reduced cost.
The 12-pulse converter exhibits a negligible level of 5th and
th
7 harmonic distortion and a reduced level of output voltage
ripple as compared to the standard six-pulse rectifier [10]. In
general, a 12-pulse uncontrolled converter consists of two six-
pulse rectifiers connected in parallel via an interphase reactor
[10]. The primary source current of the converter is formed
from the phasor sum of the input currents to the two six-pulse
rectifiers [11]. The time-displaced currents flowing through
both secondary windings form a multi-step source current on
the primary winding of the isolation transformer [10-13]. The
standard 12-pulse diode converter has a TDD value in the
range of 12-15% and dc bus voltage ripple of 1 to 2%. For
further reduction in the TDD and dc bus voltage ripples, the
pulse number of the converter can be raised by deploying
additional rectifier units. Higher pulse converters provide
additional steps with smaller time duration thereby making the
source current closer to sinusoidal. An increase in the pulse
number to reduce the TDD and dc bus voltage ripple
compromises the converter simplicity and cost by requiring
complex transformer winding arrangements, component
packaging, etc.
In general, the electrical structure of uncontrolled
converters deploying diodes and controlled converters made
up of thyristors is quite similar. However, contrary to
uncontrolled converters, in a thyristor converter, the source
current TDD, input power-factor, and dc bus voltage ripple
deviate from optimum values as control in the output voltage
is exercised requiring raised values of triggering angle (α)
beyond 0°.
This paper proposes a new topology for a multipulse
controlled converter, which consists of a standard 12-pulse
thyristor converter for ac-dc conversion and a novel
LSTATCOM on dc bus for sinusoidal shaping of the source
currents. The proposed LSTATCOM injects compensation
current in series with dc load current shared by each of the
thyristor rectifiers. It is desired that the LSTATCOM provides
sinusoidal shaping of the source currents for changes in the
output voltage requirements and variations in the output load
from 10% to 110% of the rated value. Also, the LSTATCOM
should compensate a limited amount of sag and swell in the
source voltage. A detailed mathematical model of proposed
converter is developed to simulate its dynamic and steady
state performance under various conditions.
 2

iL Gate signals vdc1 C S3 Active current

S1 dc1 Rdc
for S1 to S4 shaper
iinj1
ep1 ep2
iinj2
Control S2 S4
vdc1 System vdc2 C
dc2 Rdc
vdc2 iinj1 iinj2
Triggering
vd1 Angle α Linv
vd2 2 Rf Rf
Rinv
vdes Cf
Control signals Cf
for DC-DC
Converters. vinj1 vinj2
iL1 iL2
ipa(t) ia1 ichg1 ichg2
Ri Li vpcca Rs Ls DC-DC DC-DC ia2
vpa,b,c Th1 Th3 Th5 Conv. I Conv. II Th1 Th3 Th5
ipb(t) L
Ri Li Rs Ls ib1 ib2
vpccb Vd O vd2
vd1 iL
A
ipc(t) ic1 D
Ri Li vpccc Rs Ls ic2

Th4 Th6 Th2 Th4 Th6 Th2 Rs Rs Rs

Ls Ls Ls
i′a 2
ib′ 2 vsc
vsa
ic′ 2 vsb

Fig. 1. Proposed LSTATCOM based 12-pulse thyristor converter.

II. STRUCTURE OF PROPOSED CONVERTER
A 12-pulse converter exhibits a simple power electronics
structure and transformer winding arrangement. However, it
suffers from numerous problems, such as an increased value
of the source current TDD and limited or no control over
unexpected sags and swells in the source voltage. Moreover,
the 12-pulse thyristor converter does not offer any remedy for
a rise in the source current TDD when the output load drops
below its rated value.
To overcome the problems of higher source current TDD,
Choi, etal [13] have proposed a low power interphase reactor
based triangular current injector, which provides sinusoidal
shaping of the source currents of a 12-pulse diode converter.
Although the simple structure of the scheme is desirable, it
requires voltage control of both capacitors of the current
source connected on the secondary winding of the interphase
reactor. The single-phase dc-ac inverter based current source
produces a triangular wave shape current that is injected in
series with the two dc load currents shared by each rectifier
unit. However, any mismatch in the average values of the
voltages across the current source capacitors will produce an
unsymmetrical triangular wave shape current, resulting in
unwanted distortion in the converter source currents. Also,
this configuration is unable to handle the problems of voltage
unbalance, voltage disturbances in one rectifier, and
transformer design defects.
An active current shaper deployed in dc bus of a standard
12-pulse diode converter has been proposed in [14], which
can overcome the power quality problems, such as voltage sag
and swell, voltage unbalance, etc. The occurrence of any
voltage unbalance at the inputs of either rectifier may result in
unsymmetrical primary voltages across both halves of the
interphase reactor. The source voltage disturbance may be in
form of phase unbalance and/or magnitude unbalance. To
solve the problem of voltage unbalance, the topology
proposed in [14] requires an additional active leg in the single
phase inverter. Although the additional leg in the single-phase
dc-ac inverter increases the control system complexity of the
LSTATCOM, the system hardware allows the control system
to gain flexibility to address an array of power quality
problems such as single/three-phase voltage sags, swells, and
unbalance, wide range of load variations, etc. The
configuration presented in [14] is for a diode converter;
however, in this paper, the LSTATCOM will be employed to
a thyristor converter to maintain sinusoidal shaping of the
source current while changing the output voltage
requirements. The performance of the LSTATCOM for the
thyristor converter will be evaluated under the above-
mentioned operating conditions.
As described in the following section, the mathematical
model and control logic for the proposed LSTATCOM
scheme (Fig. 1) is more complex than that of the previous
topologies presented in [13-14]. The proposed control system
not only produces the switching signals for the single-phase
inverters but also generates control signals for two dc-dc
converters. The addition of the dc-dc converters establishes a
self-supporting dc bus, which provides the necessary voltage
across dc bus capacitors to avoid unwanted loss of the current
control and occurrence of current distortion [15].
Consequently, the self-supported dc bus of the LSTATCOM
ensures injection of an appropriate current (both shape and
magnitude) through the interphase reactor placed on dc bus of
the 12-pulse thyristor converter.
III. MATHEMATICAL MODEL OF PROPOSED CONVERTER
The mathematical model of the LSTATCOM-based 12-
pulse converter is systematically derived in this section. The
 3

development of the mathematical model involves deriving the represented as, IL1= IL2 = IL/2, where IL1, IL2, and IL are the
mathematical equations for each individual six-pulse average currents.
controlled rectifier and the mathematical equations for the As stated above, rectifier #2 is fed from a ∆-Y isolation
LSTATCOM devices and PWM controller. transformer. The supply voltages (vsa,b,c) of rectifier #2 are
expressed in terms of the voltages (vpcca,b,c) at the point of
A. Twelve-pulse Converter Model
common coupling (PCC), where rectifier #1 is connected.
Fig. 1 shows the standard 12-pulse thyristor converter with Therefore, the PCC voltages (vpcca,b,c) are considered as the
an active current shaper enclosed in a discrete block. The 12- supply voltages for rectifier #1.
pulse thyristor converter consists of two six-pulse controlled
rectifiers connected in parallel. In Fig. 1, rectifier #1 is vsa = 1
(v − vpccb); vsb = 1
(v − vpccc); and vsc = 1
(v − vpcca) (3)
directly fed from the ac mains and rectifier #2 is fed from a ∆-
3 pcca 3 pccb 3 pccc

Y transformer to provide the required 30° phase-shift between The ∆-Y isolation transformer ensures that the supply
the supply voltages, (vpcca,b,c) and (vsa,b,c) for both rectifiers. voltages (vsa,b,c) to rectifier #2 are 30° leading with respect to
The 30° phase-shift is essential for substantial elimination of the PCC voltages (vpcca,b,c). The PCC voltages (vpcca,b,c) are
the 5th and 7th harmonics in the source current [10] of the 12- determined as below.
pulse converter. The converter source currents (ipa,b,c) are
phasor sums of the individual rectifier input currents, (ia1,b1,c1) v pcca = v pa − Ri i pa − Li pi pa ; v pccb = v pb − Ri i pb − Li pi pb ;
(4)
for rectifier #1 and ( ia' 2,b 2,c 2 ) for rectifier #2. The equivalent and v pccc = v pc − Ri i pc − Li pi pc
circuit for the 12-pulse converter during the 30°+α to 60°+α
period of the source voltage is shown in Fig. 2. In Equation (4), quantities Ri and Li are the source
ipa(t)
resistance and inductance, respectively, (vpa, vpb, and vpc) and
Li Ls ia1 Th1 iL1 iL2 Th1 ia2
Ri vpcca Rs
vpa,b,c
(ipa, ipb, and ipc) are source voltages and currents, respectively.
ipb(t) ib1 L
Ri Li vpccb Rs Ls
Vd O
iL
Rearranged Equation (2) represents dynamics of rectifier #2.
ipc(t) Th6 A Th6 i
Ri Li vpccc D b2

v LLs 2 − 2 Rs iL 2 − RL (iL1 + iL 2 ) − LL piL1 (5)

Rs Rs piL 2 =
Ls Ls (2 Ls + LL )
vsc
vsa
Derived from Fig. 2, Equation (6) represents the dynamic
vsb
response of rectifier #1 during the 30°+α to 60°+α period of
Fig. 2. Equivalent circuit of the 12-pulse converter during the 30°+α to 60°+α
period of the source voltage.
the source voltage.

v pa − Ri i pa − Li pi pa − Rs ia1 − Ls pia1 − RL iL − LL piL ⎫⎪ (6)

The dynamic equation for rectifier #2 during the 30°+α to ⎬
60°+α period of the source voltage is given in Equation (1). + Rs ib1 + Ls pib1 + Ri i pb + Li pi pb − v pb = 0 ⎪⎭

vsa − Rs ia 2 − Ls pia 2 − RLiL − LL piL + Rs ib2 + Ls pib 2 − vsb = 0 (1) The difference between the source voltages (vpa–vpb) can
be expressed as the line-to-line source voltage to the
In Equation (1), p (= d/dt) is a differential operator, ia2, ib2, converter, vLLs1. The source currents (ipa,b,c) to the converter,
and ic2 are the input phase currents to rectifier #2, and iL is the which are phasor sums of the individual rectifier currents
converter load current. From the circuit shown in Fig. 2, drawn at the PCC, are expressed in Equation (7).
Equation (1) is simplified by realizing the equality ia2 = -ib2 =
iL2. Also, the load current (iL) of the converter is the phasor
i pa = ia1 + ia′ 2 = ia1 + 1
3
(ia 2 − ic 2 )
(7)
sum of the rectifier load currents, iL1 and iL2. In addition, the i pb = ib1 + ib′ 2 = ib1 + 1
(ib 2 − ia 2 )
3
difference between the supply voltages (vsa-vsb) can be i pc = ic1 + ic′ 2 = ic1 + 1
(i − ib 2 )
3 c2
expressed as the line-to-line supply voltage to the rectifier #2,
vLLs2. The simplified equation, which represents the dynamic In Equation (7), ia1, ib1, and ic1 are the input phase currents
response of rectifier #2, is given in Equation (2). to rectifier #1 and ia2, ib2, and ic2 are the input phase currents
to rectifier #2. Also, from circuit shown in Fig. 2 it is noted
v LLs 2 − 2Rs iL 2 − 2Ls piL 2 − RL (i L1 + iL 2 ) − LL p(i L1 + iL 2 ) = 0 (2) that ia1 = -ib1 = iL1. Based on information from Equation (7)
and Fig. 2, Equation (6) can be rearranged to result in
In Equations (1) and (2), the quantities Rs and Ls are the Equation (8).
input resistance and inductance for rectifier #2, and RL and LL
are the load resistance and inductance. Inclusion of the input v LLs 1 − 2 R i i L 1 − R i ( 13 i a 2 − 13 ic 2 ) − 2 L i pi L 1 ⎫ (8)
⎪
resistance and inductance (Ls, Rs) in the mathematical model − L i p ( 13 i a 2 − 13 ic 2 ) − 2 R s i L 1 − 2 L s pi L 1 − L L p ( i L 1 + i L 2 ) ⎬
− R L ( i L 1 + i L 2 ) + R i ( 13 ib 2 − 13 ia 2 ) + L i p ( 13 ib 2 − 13 i a 2 ) = 0⎪
⎭
is necessary to account for the effect of the transformer
parameters and to ensure equal sharing of the converter load
current between the two rectifiers [16]. This is mathematically As described above, the input phase currents (ia2, ib2, ic2) to
 4

rectifier #2 can be expressed as functions of the load current
(iL2) with possible values of iL2, 0, and -iL2. This inherent
operating characteristic allows for further simplification of
Equation (8). Consequently, ( 1 ia 2 − 1 ic 2 ) and ( 1 ib 2 − 1 ia 2 )
3 3
Equation (10) computes the load current (iL1) shared by
rectifier #1. In these two equations, the values for the line-to-
line supply voltages, vLLs1 and vLLs2, depend on the currently
conducting thyristor pairs in both rectifiers. For example,
3 3

can be written as k1 ⋅ i L 2 and k 2 ⋅ i L 2 , respectively. Equation (8) during the 30°+α to 60°+α interval of the converter source
voltage, thyristor pair Th6Th1 in rectifier #1 and thyristor pair
can be rewritten strictly in terms of the rectifier load currents.
Th6Th1 in rectifier #2 are conducting. Therefore, during the
30°+α to 60°+α interval, vLLs1= vpa-vpb and vLLs2 = vsa-vsb.
⎧ v LLs 1 − 2 R i i L 1 − R i iL 2 (k1 − k 2 ) − 2 L i pi L 1 − L i (k1 − k 2 ) pi L 2
⎨ As seen from Fig. 1, the high frequency switching of the
⎩ − 2 R s i L 1 − 2 L s pi L 1 − R L ( iL 1 + iL 2 ) − L L p ( iL 1 + iL 2 ) = 0 current controlled PWM inverter, which is discussed in the
(9) following section, will produce the desired voltage (vinj) across
In Equation (9), factors k1 ⋅ iL 2 , k 2 ⋅ i L 2 , k1 ⋅ p i L 2 , and the interphase reactor, where the injected voltage (vinj) is
k 2 ⋅ p i L 2 depend upon the discrete status of thyristor pair function of the injected current (iinj). Therefore, the PWM
conduction in both rectifiers. Table 1 provides a current control scheme ensures that the LSTATCOM
comprehensive list of these factors to cover the thyristor pair produces a desired injected voltage (vinj). To include the
conduction for one cycle of the input source voltage. dynamics of the LSTATCOM, Equations (5) and (10) are
From Table 1, it can be realized that (k1-k2) is a constant modified to account for the dynamics produced by the
equal to 3 . Consequently, Equation (9) can be made free injected voltage (vinj). The modified equations given in
Equation (11) will be used to represent the converter
from terms k1 and k2. Therefore, the final form of the
dynamics in the compensation scheme discussed in the
mathematical equation which represents the dynamic response
subsequent section.
of rectifier #1 is given below.
The quantity Tr in Equation (11) is the turn ratio of
v LLs 1 − 2 R i i L 1 − 3 Ri iL 2 − 3 L i pi L 2 − 2 R s i L 1 − R L ( i L 1 + i L 2 ) − L L pi L 2 interphase reactor. In Fig. 1, the interphase reactor is center-
pi L 1 =
(2 Li + 2 L s + L L ) tapped, resulting in half of the injected voltage being utilized
(10) for current shaping of rectifier #1 and the remaining half of
From the developed mathematical model, the dynamic the injected voltage shaping the input currents of rectifier #2.
response of the 12-pulse converter shown in Fig. 1 can be
represented by differential Equations (5) and (10). Equation
(5) computes the load current (iL2) shared by rectifier #2, and

TABLE I
Discrete values of input currents to rectifier #2 and factors k1 ⋅ iL 2 and k 2 ⋅ i L 2

Rectifier #2 Load
Thyristor Pair
Currents
Conduction Interval
Rect. Rect.
k1 ⋅ iL 2 k2 ⋅ iL2 k1 k2
#1 #2
ia2 ib2 ic2
0°+α to 30°+α Th5Th6 Th6Th1
1
3
(ic 2 − ib 2 ) 1
3
(ib 2 − ia 2 ) iL2 -iL2 0
1
3
−2
3

30°+α to 60°+α Th6Th1 Th6Th1

1
(i − ic 2 )
3 a2
1
(i − ia 2 )
3 b2 iL2 -iL2 0
1
3
−2
3

60°+α to 90°+α Th6Th1 Th1Th2

1
(i − ic 2 )
3 a2
1
(i − ia 2 )
3 b2 iL2 0 -iL2
2
3
−1
3

90°+α to 120°+α Th1Th2 Th1Th2

1
(i − ic 2 )
3 a2
1
(i − ib 2 )
3 c2 iL2 0 -iL2
2
3
−1
3

120°+α to 150°+α Th1Th2 Th2Th3

1
(i − ic 2 )
3 a2
1
(i − ib 2 )
3 c2 0 iL2 -iL2
1
3
−2
3

150°+α to 180°+α Th2Th3 Th2Th3

1
(i − ia 2 )
3 b2
1
(i − ib 2 )
3 c2 0 iL2 -iL2
1
3
−2
3

180°+α to 210°+α Th2Th3 Th3Th4 1

(i − ia 2 )
3 b2
1
(i − ib 2 )
3 c2 -iL2 iL2 0
2
3
−1
3

210°+α to 240°+α Th3Th4 Th3Th4

1
(i − ia 2 )
3 b2
1
(i − ic 2 )
3 a2 -iL2 iL2 0
2
3
−1
3

240°+α to 270°+α Th3Th4 Th4Th5

1
(i − ia 2 )
3 b2
1
(i − ic 2 )
3 a2 -iL2 0 iL2
1
3
−2
3

270°+α to 300°+α Th4Th5 Th4Th5

1
(i − ib 2 )
3 c2
1
(i − ic 2 )
3 a2 -iL2 0 iL2
1
3
−2
3

300°+α to 330°+α Th4Th5 Th5Th6 1

(i − ib 2 )
3 c2
1
(i − ic 2 )
3 a2 0 -iL2 iL2
2
3
−1
3

330°+α to 360°+α Th5Th6 Th5Th6

1
(i − ib 2 )
3 c2
1
(i − ia 2 )
3 b2 0 -iL2 iL2
2
3
−1
3
 5

T r v inj ⎫
v LLs 1 − − 2 Ri iL1 − 3 Ri iL 2 − 3 L i pi L 2 − 2 R s i L 1 − R L ( i L 1 + i L 2 ) − L L pi L 2 ⎪
pi L 1 = 2 ⎪
(2 Li + 2 L s + L L ) (11)
⎪
⎬
T r v inj ⎪
v LLs 2 + − 2 R s i L 2 − R L (i L 1 + i L 2 ) − L L pi L 1
2 ⎪
pi L 2 = ⎪
(2 L s + L L ) ⎭

Equation (14).
B. Proposed Current Injection Scheme
σ f 1.iinj1 > 0; Capacitor Cdc1 gets a charging current ⎫
The proposed compensation scheme depicted in Fig. 1 is ⎪
capable of sinusoidal shaping of the source currents for a load σ f 2 .iinj 2 > 0; Capacitor Cdc1 gets a charging current ⎪
⎬ Set #1
varying from 10% to 110% of its rated value as well as σ f 1.iinj1 < 0; Capacitor Cdc1 gets a discharging current⎪
addressing some important power quality problems, such as σ f 2 .iinj 2 < 0; Capacitor Cdc1 gets a discharging current ⎪⎭ (14)
voltage sags, voltage swells, and voltage unbalance. The
utilization of two thyristor converters not only offers control
of the output voltage but also provides an additional degree of σ f 3.iinj1 > 0; Capacitor Cdc 2 gets a charging current ⎫
⎪
freedom (triggering angle control) for overcoming the above- σ f 4 .iinj 2 > 0; Capacitor Cdc 2 gets a charging current ⎪
mentioned power quality problems. ⎬ Set #2
σ f 3.iinj1 < 0; Capacitor Cdc 2 gets a discharging current⎪
These power quality problems are addressed by splitting
the secondary winding of interphase reactor into two halves. σ f 4 .iinj 2 < 0; Capacitor Cdc 2 gets a discharging current ⎪⎭
The splitting of the interphase reactor allows for a decoupled
control for the current shaping of both rectifiers. As shown in A PWM current control based high frequency switching of
Fig. 1, each half of the interphase reactor is used to operate a the inverter devices may result in any of the conditions from
dedicated CC-VSI for an appropriate current shaping of both each set stated in Equation (14). Therefore, the net charging
rectifiers under a variety of power quality problems. or discharging effects of both capacitors depends on the
The dynamic response of the proposed LSTATCOM following conditions given in Equation (15).
scheme shown in Fig. 1 can be represented by the following
mathematical equations. σ f 1.iinj1 + σ f 2 .iinj 2 > 0; Capacitor Cdc1 charges
σ f 1.iinj1 + σ f 2 .iinj 2 < 0; Capacitor Cdc1 discharges
(e − R inv i inj 1 − R t i inj 1 − v inj 1 ) ⎫ (15)
=
p1
pi inj 1 ⎪
L inv + L t ⎪ (12)
σ f 3 .iinj1 + σ f 4 .iinj 2 > 0; Capacitor Cdc 2 charges
(e p 2 − R inv i inj 2 − R t i inj 2 − v inj 2 )⎬⎪
pi inj 2 = σ f 3 .iinj1 + σ f 4 .iinj 2 < 0; Capacitor Cdc 2 discharges
L inv + L t ⎪
⎭

⎛ v inj 1 ⎞ ⎛ v inj 2 ⎞ For a desired current control of the inverters, an equal

⎜i − ⎟ ⎜i − ⎟ average voltage across dc bus capacitors (Cdc1 and Cdc2) is
⎜ inj 1 Rf ⎟ ⎜ inj 2 Rf ⎟
⎝ ⎠ ⎝ ⎠ (13) necessary, even though their instantaneous values may be
pv inj 1 = pv inj 2 =
Cf Cf different. The dynamic response of dc bus voltage of both
inverters (Fig. 1) is represented by Equation (16).
where Rinv and Linv are the inverter resistance and
inductance, Rt and Lt are the transformer resistance and ⎛ v ⎞ ⎫
⎜⎜ σ f 1iinj1 + σ f 2iinj 2 − dc1 + ichg1 ⎟⎟ ⎪
inductance, and Rf and Cf are parameters of the low-pass filter. Rdc
pvdc1 = ⎝ ⎠ ⎪
In Equation (12), quantities ep1 and ep2 are the pole voltages of Cdc ⎪⎪ (16)
both inverters (Fig. 1), and vinj1 and vinj2 are the voltages ⎬
⎛ ⎞
⎜⎜ σ f 3iinj1 + σ f 4iinj 2 − dc 2 + ichg 2 ⎟⎟ ⎪
v
produced across both halves of the interphase reactor
Rdc ⎪
winding. In Equation (13), the term vinj/Rf accounts for the pvdc 2 = ⎝ ⎠⎪
dielectric loss in the filter capacitor Cf as well as the ohmic Cdc ⎪⎭
loss in the low pass filter. The quantities, iinj1 and iinj2, are the
injected currents produced by the PWM inverters. For proper current control without an occurrence of current
The PWM pole voltages (ep1 and ep2) and the switching distortion [15], a self-supported dc bus voltage for the
functions ( σ f 1 , σ f 2 , σ f 3 , and σ f 4 ) of the two inverter LSTATCOM inverter circuits is needed. This is essential
since the LSTATCOM injects currents (iinj1 and iinj2) in series
circuits depend on the switching states of their devices,
with the load currents (iL1 and iL2) shared by the six-pulse
IGBTs (S1, S2, S3, and S4) and diodes (D1, D2, D3, and D4).
thyristor rectifiers. An additional energy source may be
The charging and discharging of both capacitors in the
needed to provide the desired value of dc bus voltage for the
inverter circuits depend on the inequality conditions stated in
inverters. To eliminate this major drawback, the proposed

LSTATCOM is equipped with two buck-boost dc-dc
converters. For a standard 12-pulse diode converter, only the
step-down action of dc-dc buck-boost converter is needed.
However, for the 12-pulse thyristor converter presented in this
investigation, depending upon load voltage requirement both
the step-up and step-down actions of the buck-boost dc-dc
converter are required.
In Equation (17), ichg corresponds to the charging currents
supplied by the buck-boost dc-dc converters. In the novel
scheme proposed in this paper, the dc-dc converters provide a
unidirectional power flow link between the 12-pulse converter
dc bus and the LSTATCOM inverter dc bus. To produce
symmetrical triangular waveshaped currents from both halves
of the LSTATCOM (Fig. 1), the voltages across both dc bus
capacitors (vd1 and vd2) must be equal, requiring use of two
identical dc-dc converter circuits.
The dynamic response of the buck boost dc-dc converter
can be represented by the following equation.
(vd − Rbb ichg ) ; when switch SW is ON
⎫ vd2
pichg = ⎪
Lbb ⎪ (17)
pichg =
(− Rbb ichg − vdc ) ⎬
; when switch SW is OFF ⎪
Lbb ⎪ circuit
⎭
where vd is the voltage across the 12-pulse converter load
and Rbb and Lbb are dc-dc converter resistance and inductance,
respectively. In general, the power rating of the LSTATCOM
is about 2% of the 12-pulse converter [13]; as a result, the 12-
pulse converter could function as an alternative energy source
for the self-supported dc bus of the LSTATCOM inverter.
This effectively eliminates the need of an additional energy
source for the inverters. With the addition of dc-dc
converters, the equations for the individual rectifier load
currents (iL1 and iL2) given in Equation (11) have to be
modified as expressed in Equation (18).
vLLs1 − Tr vinj1 − 2RiiL1 − 3RiiL 2 − 3Li piL 2 − 2RsiL1 − Vd ⎫
piL1 =
(2Li + 2Ls )
vLLs2 + Tr vinj2 − 2RsiL 2 − Vd
piL 2 =
2Ls
A detailed description and mathematical model of the 12-
pulse thyristor converter along with the LSTATCOM have
been laid out in section 3. The control strategy of the 12-pulse
thyristor converter with an active current shaper on its dc bus
is described in the following section.
IV. LSTATCOM CONTROL SYSTEM
The switching states of the CC-VSI devices (S1, S2, S3, S4,
D1, D2, D3, and D4), shown in Fig. 1, can be obtained using the
PWM current control scheme presented in Fig. 3. For this, the
injected current (iinj) is compared with its reference
*
counterpart ( iinj ). The resulted error is processed in a PI
controller to ensure that the injected current (iinj) follows a
*
trajectory around the reference current ( iinj ). The output of
6
the PI controller is subjected to a limiter to avoid the problem
of under modulation. The limiter output is compared with a
high frequency carrier signal to obtain the control signals for
the switching devices used in the LSTATCOM inverter circuit
(Fig. 1). For the desired control of the LSTATCOM current
(iinj), it is essential to obtain an injected reference current
*
( iinj ) with an appropriate shape. Since the proposed scheme
(Fig. 1) is aimed to provide sinusoidal shaping of the 12-pulse
converter source current for a variety of operating conditions,
such as a load variations, voltage sag, swell, and voltage
*
unbalance, the reference current ( iinj ) needs to be a function
of the system quantities. In this investigation, it has been
*
determined that the reference current ( iinj ) is expressed as a
function of voltages, vd1 (output voltage of rectifier #1), vd2
(output voltage of rectifier #2), and iL (converter load current).
Gate drive signals to
LSTATCOM devices
vd1 Dead time
Injected *
iinj control To S1 and S3
reference PI
circuit
iL current
estimator
Controller
iinj
Carrier Signal
Dead time
control To S2 and S4
Fig. 3. Control scheme of the LSTATCOM shown in Fig. 1.
To provide a self-supporting dc bus for the active current
shaper, two buck-boost dc-dc converters are deployed
dedicated to each of the inverter circuits. The closed loop
control scheme of the buck-boost dc-dc converter is similar to
that for any standard dc-dc converter [17].
For a 12-pulse thyristor converter, the dc output voltage can
also be controlled by adjusting the triggering angle (α). The
maximum dc output voltage occurs when the triggering angle
(α) for both rectifiers is 0°. Under this condition, a thyristor
converter acts as a diode converter. When the requirement for
the load voltage reduces, the triggering angle can be raised,
leading to a higher TDD in the source current and lower
power-factor. However, under the condition of voltage sag for
⎪
⎪
(18) example, the triggering angle (α) can be reduced to provide
⎬ the desired output voltage at an improved power-factor.
⎪
⎪ Therefore, depending upon the operating condition a
⎭ simultaneous or selective control of the thyristors’ triggering
angle and the injected current magnitude can be exercised for
sinusoidal shaping of source current while addressing a
variety of power quality issues.
V. PERFORMANCE OF PROPOSED CONVERTER
The derived mathematical model of the proposed
LSTATCOM for a standard 12-pulse thyristor ac-dc converter
is used to develop the simulation model. The resulted
simulation model is used to obtain the dynamic and steady
state response of the proposed system. The simulation results
reveal that the proposed LSTATCOM not only provides
sinusoidal-shaped source currents but also satisfies the output
voltage requirement under a variety of power quality
conditions. To validate the viability of the developed
simulation model of the proposed LSTATCOM, the 12-pulse

converter has been tested under the following operating
conditions (a) steady state response followed by a change in
the output voltage requirements (b) perturbation of the
converter load, (c) sag in the converter source voltage, and (d)
swell in the converter source voltage.
The proposed LSTATCOM is capable of providing
sinusoidal shaped source currents despite changes in the
desired output voltage. To demonstrate the effectiveness of
LSTATCOM, the converter system is subjected to a transient,
which is sudden change in the thyristor triggering angle.
However, to reveal LSTATCOM effectiveness for transient
disturbance, it is pertinent to show the steady state response
for a finite duration. Fig. 4 shows the steady sate response of
LSTATCOM followed by transient results for a sudden
change in the thyristors’ triggering angle. A triggering angle
of 45° results in a desired output voltage of 235V and 5.15 %
TDD in the source current.
In Fig. 4 it is demonstrated that at time t = 0.28s, the
triggering angle (α) is increased to 55° resulting in a drop in
the output voltage from 235 V to a new desired value of
165V. From Fig. 4 is clear that LSTATCOM provides a
seamless transfer of converter operation from the old
operating condition to a new steady state point with the
exception of a quarter cycle needed to restore proper energy
balance. At time t = 0.31s, the triggering angle (α) is changed
from 55° to 35° to obtain a new desired value of output
voltage (350V). As expected, the LSTATCOM provides a
seamless transfer of converter operation to a new steady state
point in a half cycle time, which is the time elapsed to achieve
an energy balance between the input and output ports of the
converter circuit. This is due to the unidirectional power flow
in the system.
For both transient disturbances related to the thyristors’
triggering angle, it is found that the LSTATCOM maintains a
sinusoidal shaped source current by effectively following the
injected current (iinj) and injected voltage (vinj) in close
vicinity of their reference counterparts, reference current ( iinj
*
) Fig. 5. Transient response of converter for a load change from 23.11A to
and reference voltage ( v inj
*
), respectively. Also,
LSTATCOM maintains the source current TDD in the range
of 5%.
vd1, vd2
vpa
ipa
*
iinj , iinj
vd
iL
Time (s)
Fig. 4. Steady state and transient response of the proposed converter for changes
in the output voltage requirement.
7
The proposed LSTATCOM is also capable of providing
sinusoidal shaped source currents over a wide range of output
load variations. Fig. 5 shows the current shaping capability of
the LSTATCOM for transitions of the converter load from a
low value (23.11A) to a high value (62.91A). It is observed
that the converter system needs approximately a quarter cycle
to restore proper energy balance. It is also observed from Fig.
5 that regardless of any loading condition, the LSTATCOM
control system maintains the sinusoidal shaped source current
by appropriately changing the reference current ( iinj
*
), which
is expressed as a function of the load current (iL). The CC-
VSI working as active current shaper ensures that the injected
current follows the reference current ( iinj
*
). For a higher
loading condition, the output voltage of the rectifiers is
slightly reduced. Consequently, at time 0.31s, the value of the
triggering angle is reduced to provide the additional voltage
for a constant output voltage requirement. This results in a
simultaneous control of the triggering angle and injected
current magnitude to obtain the desired output voltage (vd)
while fulfilling load demand (iL) at an improved power quality
condition at input and output ports of the converter circuit.
vd1, vd2
vpa
ipa
*
iinj , iinj
vd
iL
Time (s)
62.91A.
the
For voltage sensitive loads connected at the output of the
converter, the LSTATCOM control system should be capable
of compensating an anticipated amount of sag and swell in the
source voltage. It is demonstrated in Fig. 6 that the
LSTATCOM control system compensates a 20% sag in the
source voltage (vpa,b,c). In LSTATCOM control system
design, the reference injected current ( iinj
* ) is expressed as a
function of iL, vd1, and vd2. Therefore, a drop in vd1 and vd2
during the sag forces the LSTATCOM control system to
compensate unwanted sag by injecting a higher value of
current through the interphase reactor, which is confirmed
from Fig. 6. An increased magnitude of the injected current
keeps the output load voltage in the desired range. Any
distortion in the source current during the transition from the
normal condition to the voltage sag condition and vice versa is
due to a sudden energy imbalance in the system. In Fig. 6, the
distortion in the source current lasts approximately one cycle,
which is the time needed to restore an appropriate energy

balance.
vd1, vd2
vpa
ipa
*
iinj , iinj
vd
iL
Time (s)
Fig. 6. Transient response of the converter for a 20% sag in the source voltages
(vpa,b,c).
Fig. 7 shows the transient response of the converter for a
20% swell in the source voltages (vpa,b,c). During the voltage
swell, the currents injected (iinj1 and iinj2) by the LSTATCOM
in series with the load currents (iL1 and iL2) shared by both
rectifiers maintains the desired flow of power from source to
load, resulting in sinusoidal shaping of the source currents
(ipa,b,c). Under the condition of voltage swell, the magnitude
of the source current must be reduced to achieve a constant
output power. From Fig. 7 it is clear that a 20% swell in the
source voltage (vpa,b,c) causes an additional flow of energy
from source to the load, resulting in an overshoot in the load
voltage (vd). The problem of voltage overshoot can not be
completely eliminated due to the unidirectional power flow in
the converter system. A finite amount of time is needed for
the converter system to restore the proper energy balance.
vd1, vd2
vpa
ipa
* measures,” IEEE Transactions on Industry Applications, vol. 32, no. 6,
iinj , iinj
vd
iL
Time (s)
Fig. 7. Transient response of the converter for a 20% swell in the source voltages
(vpa,b,c).
VI. CONCLUSION
This paper has proposed a novel load compensator
(LSTATCOM) scheme for a 12-pulse thyristor converter. The
mathematical model of the proposed converter system has
been segmented in two parts, the first part for the controlled
component (LSTATCOM) and the second part for the
individual rectifiers in the converter. The developed
8
mathematical model has been converted into a simulation
model using c-codes. The simulation model has been tested
for changes in the output voltage requirement operating under
different power quality conditions, such as a wide range of
load perturbation and a significant amount of source voltage
sag and voltage swell. It has been demonstrated that the
decoupled operation of the inverters in the LSTATCOM
system as well as appropriate control of the triggering angle
makes the load connected at the output of the 12-pulse
converter system free from expected power quality problems,
resulting in sinusoidal source currents and desired output
voltage. It is expected that the proposed converter system
could become an enabling technique for the high power dc
supplies used in a variety of engineering applications.
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