A 1-nW 95-ppm/◦C 260-mV startup-less

bandgap-based voltage reference

Gajendranath Chowdary Kalyan Kota Shouri Chatterjee
Department of Electrical Engineering Aura Semiconductors Limited Department of Electrical Engineering
IIT Hyderabad, Hyderabad, India Bangalore, India IIT Delhi, New Delhi, India
Email: gajendranath@iith.ac.in Email: kalyan.kumar@aurasemi.com Email: shouri@ee.iitd.ac.in

VDD VDD
Abstract—We present an ultra-low-power fractional bandgap-
based voltage reference and a unique method of generating a MN1 R VP T AT
M P2
small proportional-to-absolute-temperature (PTAT) current. The VX +VP T AT
PTAT current is used to generate a BJT complementary-to- N A
MN2
absolute-temperature (CTAT) voltage. We have achieved tem-
R VP T AT
perature compensation of the generated reference voltage by B MPSF
VX
subtracting a sub-threshold MOS CTAT voltage from the BJT VP T AT
CTAT voltage. The difference between the two CTAT voltages is VA R
temperature stable from -50◦ C to 85◦ C with a mean variation MN1
L

LOAD
LOAD
of less than 95 ppm/◦ C measured across chips, without any
MP1
additional trim. The proposed technique eliminates the need for MN2
additional start-up circuitry, which is mandatory for conventional
architectures. The 260-mV voltage reference designed in a 180-
nm CMOS process has a measured line regulation of 0.23 %/V (a) (b)
and consumes 1 nW at room temperature.
Fig. 1. PTAT current generation circuit schematics, (a) discussed in [5], and
I. I NTRODUCTION (b) proposed in this work.

Ultra-low power and low-voltage circuits require nano-

watt sub-1V voltage references. Band-gap references (BGRs)
are generally used to generate a process-voltage-temperature
(PVT) independent reference voltage. Classically, one elim-
inates the temperature dependence of a BGR by adding
a proportional-to-absolute-temperature (PTAT) voltage and a
complementary-to-absolute-temperature (CTAT) voltage. The
circuitry used to generate the PTAT current and the start-
up circuit, largely decide the total power consumption of the
BGR. The start-up current in the circuit is required to be higher
than the leakage current of the MOS devices to enable proper
operation. The PTAT current generation circuit and the start-
up circuit limit the BGR to operate with tens of nano-watts of
power [1]–[3].
[1]–[4] have shown voltage references consuming several
tens of nanowatts of power. Like in a conventional BGR
circuit, [1]–[3] also use an op-amp, a significant source of
power dissipation. In this paper, we propose an ultra-low-
at 27◦ C, and consumes 1 nW at room temperature.
II. P ROPOSED PTAT CURRENT GENERATION
The schematic of the PTAT current generation circuit in [5]
is shown in Fig. 1(a). In [5], MN1 is a device with a gate-
source voltage of 0 V, and is operating in deep sub-threshold.
MN2 is smaller than MN1 , and the voltage across MN2 is
PTAT. With the help of the two op-amps, a PTAT current
proportional to the voltage across MN2 is generated.
The circuit in Fig. 1(a) suffers from three drawbacks:
• MN1 and MN2 should be sized such that VP T AT is
greater than at least 3kT /q (75 mV) to avoid VDS
dependence on VP T AT . A large VP T AT requires a large
resistor to obtain a small PTAT current (e.g 75 MΩ to
generate a current of 1 nA).
• The circuit uses two op-amps to obtain a PTAT current.

power startup-circuit-free op-amp-less BGR-based circuit with • Body effect of MN1 and MN2 degrades the linearity of

a unique method of PTAT current generation. the PTAT current.

A low PTAT voltage allows us to generate small PTAT
currents in the circuit without using a large resistor. We have
generated a CTAT voltage from the PTAT current, and have
generated the final reference voltage by subtracting a CTAT
voltage from the former. The voltage reference was fabricated
on a 0.18-µm CMOS process. The circuit generates 260 mV
with a mean temperature coefficient (TC) of 95 ppm/◦ C at a
0.7-V power supply, with a line regulation (LR) of 0.23 %/V
From the above, it is clear that generating sub-nA PTAT
currents and restricting total power consumption to 1-nW is
not trivial. There are no bandgap-based circuits available in
the literature that operate at a power consumption of 1 nW.
In this work, a PTAT current is generated using three
pMOS devices MP1 , MP2 and MPSF as shown in Fig. 1(b).
MP1 is in deep sub-threshold, and MP2 sources the same
current as demanded by MP1 . VSD of MP1 and MP2 is well

978-1-7281-3320-1/20/$31.00 ©2020 IEEE

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 16
VP T AT voltage [mV]
L
14 VP T AT = VSG (T ) = m(T )φT ln N
)
12
10
8 MP2
Slow
6 VCT AT
-40 -20 0 20 40
Temperature [◦ C]
Fig. 2. Simulations of the proposed PTAT voltage across process corners
and temperature.
above 5kT /q for all temperatures and process corners. This is
achieved with the help of a negative feedback loop from node
B to A. Any difference between the currents in MP1 and MP2
is sensed, converted to a voltage, and applied at the gate of
MPSF , which is fed back to the gate of MP2 . Sufficient gain
in the feedback loop is provided by MP1 and MP2 . The aspect
ratio of MPSF is chosen to be small in order to make VSD
of MP2 greater than 5kT /q. VSG of MP2 is a PTAT voltage
which can be obtained by equating the currents through MP1
L VE (T ) = Ego (1 − α1 ∆T − β1 ∆2T ),
and MP2 . The ratio, N is chosen to be as small as possible
to generate a low PTAT voltage. The source to gate voltage
of MP2 can be found by equating the currents through MP1
and MP2 . The source to gate voltage of MP2 is given as:
VP T AT = VSG (T )
(1)
L
) = m(T )φT ln
N with the help of diode connected devices as shown in Fig. 3.
where L and N are the multipliers of MP1 and MP2 respec-
tively, with an unit width of W , m(T ) is the subthreshold
slope, and φT is the thermal voltage.
A VP T AT of 9 mV requires 6 MΩ to generate a 1.5 nA
PTAT current. A low PTAT voltage also reduces the non-
linearity in the PTAT voltage. No explicit start-up circuit is
required for the proposed PTAT generation scheme, since there
is no other stable operating point. The simulation results of the
proposed PTAT current across the process corners is shown in
Fig. 2.
III. P ROPOSED FRACTIONAL BAND - GAP REFERENCE
The generated PTAT current is pushed through a BJT as
shown in Fig. 3 to generate a CTAT voltage, VE . MN3a and
MN4a operate in deep subthreshold. The currents through the
two devices can be equated to obtain the gate-source voltage
of MN4a .
The generated VE as given in [6]:
T T
VE (T ) = Ego (1 − ) + VE (To )( ) + (n − 1) ln( ) (2)
To To
where, VE (T ) is the voltage across the BJT as a function of
temperature, Ego is the energy bandgap voltage of silicon at
room temperature, n is a constant (≈1.5), T is the absolute
temperature, and To is the room temperature.
The linearity of VE is dependent on the current passing
through the BJT. The non-linear variation of VE can be
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VDD
R VP T AT
N MN4a MN4b
M M
Typical Fast MPSF VCT AT
VP T AT
60 80 100 R
VE
VREF
L MN3a MN3b
VE
MP1 3 1 1
Fig. 3. Complete schematic of the proposed band-gap based reference. A
PTAT current is pushed through a BJT to generate a CTAT voltage VE on the
left side. VREF = VE /3 − 2VCT AT is implemented in the shaded region.
minimized by reducing the PTAT current non-linearity. By ne-
glecting the higher order non-linearities, VE can be expressed
as [7].
(3)
where α1 and β1 are the first and second order temperature
coefficients of VE and their typical values are −5 m/◦ C
and −1 µ/◦ C2 at 27◦ C respectively. The higher order non-
linearities at the output can be compensated, if we use the
curvature compensation technique as reported by [8]. A frac-
tion of VE is generated by dividing the voltage across the BJT
The divider is sized such that it draws less than 15% of the
total PTAT branch current to avoid loading. The worst case
error due to loading is less than 2 mV. The divider current is
chosen such that the leakage through the nwell-psub diodes in
the divider is less than 0.1% of the divider current across PVT
variations. V3E has a temperature coefficient of 667 µV/◦ C.
The shaded portion in Fig. 3 shows the structure of a novel
compensation scheme to eliminate the effect of temperature
coefficient of BJT to obtain a temperature compensated output
voltage. The MN4 (MN4a , MN4b ) transistor sinks the same
amount of current as that of MN3 (MN3a , MN3b ). The drain to
source voltage of MN3 and MN4 is sufficiently maintained to
be greater than 5φT for all temperatures and process corners.
The gate to source voltage of MN4 can be expressed as
1 W3

VGS (T ) = m(T )φT ln × −∆
M W4 (4)
= VGS (To )(1 + α2 ∆T + β2 ∆2T ) − ∆,
T
where M is the multiplier of MN4 , W3 and W4 are the widths
To of MN3 and MN4 respectively, m(T ) is the subthreshold slope
factor whose value is a function of temperature, α2 and β2 are
the first and second order non-linear coefficients of the CTAT
voltage of MOS generated respectively, and the error because
of the body effect of MN3 and MN4 is ∆.
With the help of (4), it is found that, to cancel the tempera-
ture coefficient of V3E , a large multiplier M of 300 is required.
 280
260

VREF [mV]
600 240
BJT CTAT voltage, VE
220 Line regulation : 0.23 %/V
500 200
CTAT voltage [mV]

180
400
160
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
300 VE Supply voltage, VDD [V]
3
200 (a)

Current consumption [nA]

100 6
MOS CTAT voltage, −2 × VCT AT 5
0 4
-40 -20 0 20 40 60 80 3
Temperature [◦ C] 2
1
264
0
263 -40 -20 0 20 40 60 80 100
VREF [mV]

262 Temperature [◦ C]
(b)
261
260 Fig. 5. Measurements of (a) VREF as a function of supply voltage, and (b)
259 current consumption as a function of temperature at 1 V supply.
-40 -20 0 20 40 60 80

Temperature [◦ C] 4
Mean = 260 mV
σ = 3.69 mV
Fig. 4. Measured BJT CTAT voltage, MOS CTAT voltage along with the 3

Number of samples
output reference voltage, VREF , as a function of temperature.

Two such stages are cascaded to relax the constraint on the

1
required multiplier M . The source and body of MN4a and
MN4b are not connected together, resulting in a body effect
coefficient ∆ (= ∆1 +∆2 ) to appear at the output voltage. ∆1 245 250 255 260 265 270 275
is CTAT as the source-body voltage of MN4a is CTAT. The Reference voltage, VREF [mV]
source-body voltage of MN4b is VREF which is insensitive (a)
to temperature. However, it was observed that ∆2 is PTAT 5
Mean = 95 ppm/◦ C
because of the temperature dependence of the body-effect σ = 35 ppm/◦ C
4
coefficient. The effective variation in ∆ with temperature is
Number of samples

observed, in simulation, to be less than 1.3 µV/◦ C. The body 3

effect error ∆ results in the output voltage of Ego /3 − ∆
(260 mV) instead of Ego /3 (360 mV). The output voltage of 2

the circuit is given by: 1

VREF = VA − VGS
Ego 0 40 80 120 160 200
= (1 − α1 ∆T − β1 ∆2T ) (5) Temperature coefficient [ppm/◦ C]
3
(b)
− VGS (To )(1 + α2 ∆T + β2 ∆2T ) − ∆
Fig. 6. Histogram of (a) VREF , and (b) temperature coefficient, for 9
The terms with the temperature coefficients are engineered to measured parts.
cancel. Further, VGS (T0 ) is tiny because it is the voltage drop
required for a leakage current, and the final voltage reference
is Ego /3 − ∆. With the help of a deep nwell process (not in The net error ∆ is the sum of ∆1 and ∆2 .
this paper), VREF will be an exact fraction of Ego without
any body effect induced non-linearity. IV. M EASUREMENT RESULTS
The difference between the thresholds of MN3a , MN4a and
Fig. 4 shows the measured DC performance of the BGR as
MN3b , MN4b are given by:
a function of temperature. The output voltage, VREF , exhibits
less than 120 ppm/◦ C from -50◦ C to 85◦ C at a supply voltage
p p 
∆1 = γ φs + VSB4A − φs
p p  (6) of 1 V. Fig. 4 also shows the measured BJT CTAT voltages,
∆2 = γ φs + VSB4B − φs
i.e., corresponding to VE and V3E , and the MOS CTAT voltage
where ∆1 and ∆2 are the VT differences, γ is the body effect as a function of temperature.
coefficient of the MOS device, and φs is the surface potential. Fig. 5 shows the variation of VREF with supply voltage and

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 TABLE I
C OMPARISON WITH OTHER STATE - OF - ART VOLTAGE REFERENCES .

This
[1] [2] [3] [7] [9] [10] [11] [12] work
TC (ppm/◦ C) 215 12.8 5.3 147 10 3.1 33 26 95
Min VDD (V) - - 0.5 0.9 1.4 1.0 1.0 ≥ 1.2 0.65
Power (W) 108n 28.7n 29.5p 100n 36n 0.8µ 192p 9.3n 0.98n
Line reg. (%/V) 0.45 0.92 0.036 - 0.27 0.03 0.02 0.08 0.23
Area (mm2 ) 0.21 0.48 0.0093 0.094 0.045 0.115 0.0045 0.55 0.075
Range (◦ C) -20 to 80 -10 to 110 -20 to 80 -40 to 120 0 to 80 -40 to 125 -20 to 100 0 to 110 -50 to 85
Reference (V) 1.18 1.76 0.175 1.09 0.66 0.635 0.693 1.24 0.26
Process (µm) 0.35 0.35 0.13 0.18 0.35 0.18 0.18 0.18 0.18
Type BG BG ∆VT BG VT BG Hybrid Hybrid BG

a sub-1V power supply, with ultra-low power consumption.

The 260 mV voltage reference designed in a 180 nm CMOS
process is the lowest-power bandgap-based voltage reference
that is currently available in the literature.
MP1MP2
182 µm

BJT MOS CTAT R EFERENCES

Resistor
412 µm
Fig. 7. Photo-micrograph of relevant portion of the 180 nm CMOS chip.
The silicon area of the voltage reference circuit is 0.075 mm2 .
the measured current consumption of the circuit with temper-
ature. The line regulation of the reference circuit is 0.23 %/V.
The current consumption is 1.5 nA at room temperature and
increases to 5.4 nA at 85◦ C. At room temperature, for a
0.7 V supply, the power consumption is 1 nW. In Fig. 6 we
have shown the variation and temperature stability of VREF
for 9 packaged samples. The mean temperature coefficient is
95 ppm/◦ C with a standard deviation of 35 ppm/◦ C. The
measured value of VREF has a mean of 260 mV, with a
standard deviation of 3.7 mV. In Tab. I we have compared
the performance of our circuit with other state-of-art voltage
references. Our circuit is the first bandgap-based reference to
be at a power consumption of 1 nW (to the knowledge of the
authors). Unlike non-bandgap-based circuits (such as [11]),
our technique provides a specific known voltage (260 mV, or
Ego /3 using a deep n-well process), over process, voltage and
temperature. Fig. 7 shows a micro-graph of the relevant portion
of the chip. The circuit occupies 0.075 mm2 of active area.
V. C ONCLUSION
In this work, we have developed a temperature-insensitive
voltage reference generation technique, using a BJT-based
CTAT and a MOS-based CTAT. We have also demonstrated
a novel PTAT current generation technique by using a small
resistor to generate a sub-nA current. Both of the above tech-
niques are integrated to build a sub-nW BGR operating from
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