IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. IE-32, NO.

4, NOVEMBER 1985 283

New M6805 Microcomputers Aim at Automotive

Applications
DANIEL A. ARTUSI, MEMBER, IEEE, AND RICHARD VALENTINE

Abstract-Several new additions to the MC6805 family of microcom-

puters include features particularly suited for automotive electronics.
These devices feature application specific logic for automotive ignition
systems and instrumentation designs. The MC6805S2, MC680S3, and
MC68705S3 microcomputers are useful for engine ignition controls,
where asynchronous events, such as engine speed and spark dwell time
must be computed with high accuracy. The MC6805K2 microcomputer
features EEPROM for critical data retention when the power source is
disconnected. The instrumentation odometer is one such application
where the EEPROM feature is mandatory. The MC68HCO5C4 (ROM
version) and M68HC805C4 (EEPROM version) are the latest general
purpose MCU's that also offer many important features for automotive
applications. The HCMOS silicon technology allows minimal power
dissipation which means the devices can operate in an ambient tempera-
ture range of - 55 to + 125 degrees C. These two devices also feature SCI
and SPI serial interface ports. The devices run at a fast 2.1-MHz internal
bus speed.
This paper will describe the key internal architectures of these new Fig. 1. MC6805S2 ignition system.
MCU products and will show system designs that utilize these features.
applications. The clock sources for both prescalers can be
I. IGNITION SYSTEM independently selected by software. The clock sources in-
clude: external (Port C), internal (fosc divided by four), gated
FIG. 1 shows a MCU-based ignition design [1]. The basic internal, and disabled. The timer control registers (TACR,
design requirement is to measure the angular rotation of TBCR) bits 4 and 5 set up the clock sources.
the engine and fire the appropriate spark plug at the best time Timer A Control Register bits 0, 1, and 2 set the division
for maximum power. The MC6805S2, MC6085S3, or ratio for prescaler number 1. This ratio can be from 1 to 128.
EPROM version, MC68705S3, feature a flexible timer sub- Prescaler number 2 division ratio is set up by the Timer B
system as shown in Fig. 2. Control Register. Bits 0, 1, 2, and 3 allow a ratio of 1-32,768
The timer subsystem consists of one 8-bit timer (0-255), to be selected. The Miscellaneous Register (MR) bits 2 and 3
one 16-bit timer (0-65735), and two prescalers. The 16-bit
can be used to load up prescalers 1 and 2 to all ones. Bit 1 in
timer is used to calculate the engine speed and the 8-bit timer is
MR controls which prescaler is hooked to the timers.
used to set the coil "on" time. The 16-bit timer free runs and The timers themselves are an 8-bit countdown type (Timer
is read when an external interrupt signal is detected from the
ignition timing input sensor. By comparing this new value with A) and a simple 16-bit timer (Timer B). A dual-mode modulus
the previous value, the engine speed can be calculated. latch is used to load Timer A. The mode in operation is
controlled by a bit in the Timer A Control Register. In mode
Acceleration or deceleration rates can also be computed by
comparing three or more engine speed values. Once the engine zero, the value in the modulus latch itself is loaded, and when
speed and rate of speed change are known, then the coil "on" the timer underflows (actually at timer = 00). In mode one,
time can be set upon the detection of the ignition timing input the value in the modulus latch is loaded into the timer, both
when the timer underflows and on an external asynchronous
signal. Other factors, such as battery voltage, manifold
vacuum, and coolant temperature are also used to interpolate event, which is in fact an interrupt request generated via the
the required spark advance. As you can see, the timer INT2 pin. The timer can be read at anytime. When the timer
subsystem performs the critical engine timing requirements. underflows, in addition to reloading itself, it can either
The timer's internal architecture will be reviewed next. generate an interrupt request or directly toggle a Port B pin, or
both.
Referring back to Fig. 2, the timer subsystem consists of Timer B uses a pipeline latch between the (8-bit) data bus
two timers, two prescalers, two control registers, and a
and the high byte of the timer to ensure that a synchronous 16-
miscellaneous register. The two prescalers can be swapped, bit transfer takes place when the timer is read or loaded. At
thereby allowing high program flexibility for timing intensive underflow the timer is loaded with $FFF and, as with timer A,
either an interrupt request or direct toggling of a Port B pin, or
both will occur. Port B pins BO and BI are equipped with the
Manuscript received October 25, 1984.
The authors are with Motorola Semiconductor Products Sector, Phoenix, toggle feature. Therefore, the choice of pin BO or BI, as the
AZ 85062. timer input, is under control by software via a bit in MR. Bits

0278-0046/85/1100-0283$01.00 © 1985 IEEE

 284 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. IE-32, NO. 4, NOVEMBER 1985
Fig. 2. MC6805S2 timer subsystem.
are also available in other registers to enable or disable the
toggle facility in both BO and B1 independently. This feature
provides the designer with an extremely flexible dual timer
structure, totally under software control, using no more than
22 control bits.
The MC68705S3 and MC6805S3 include one more timer.
This can be utilized for an extra timer requirement. One
example would be to measure road speed. This timer is 8 bits
and shares either prescaler 1 or 2. It also features an input read
capture latch that is refreshed when an external voltage
transition occurs on pins PCO or PCI.
A 12-bit auxiliary counter is used on the MC6805S2 and
MC68705S3 devices for a system watchdog. If the MCU
should lose control of the program and execute through non-
valid memory space, this auxiliary counter will reset the
MCU. The auxiliary counter is a fixed 12-bit counter with just
two modes of operation. It runs at internal clock frequency
(fosc divided by four). The total count period is 4095 cycles.
The MCU communicates with this counter via the MR bits 5
and 4 (MR5, MR4). Upon overflow, the auxiliary counter
control/status bit in MR5 is set. Countdown may be aborted at
any time under program control, which also will reset the
counter to 4095 ($FFF). To do this, the microcomputer must
write to MR5 the inverse of what is read from MR5.
During reset, the auxiliary counter is preset to its maximum
count of 4095 ($FFF), and MR5 is cleared. The value of the
counter is not accessible to the MCU; however, the possibility
of detecting an underflow and presetting it at any time under
program control allows it to be used as a fixed-rate polled
timer in applications requiring lengthy time-out periods.
When the auxiliary counter reset mask bit in MR4 is clear
and the MR5 bit is set as a result of counter time out, the reset
pin is internally pulled to ground. This feature is useful in
many applications, and particularly in automotive systems,
where the MCU operates in a noisy environment.
II. MC68HCO5 IGNITION
The MC68HCOSC4 8-bit microcomputer may also be used
for ignition applications. This device features higher tempera-
ture ranges plus low-power requirements. It does not,
however, include A/D channels. The use of an external A/D
device can be easily interfaced to the MC68HCOSC4 through
the use of the SPI bus which will be explained later in this
paper.
To use the MC68HCOSC4 for ignition control designs, its
timer architecture has to be utilized fully. Fig. 3 shows the
MC68HCOSC4 timer block diagram. As can be seen, the timer
uses a 16-bit architecture throughout. A 16-bit free running
counter is utilized along with a fixed divide by four prescalers.
The timer can resolve down to 2 As with a 4-MHz external
crystal. The input capture register would be used to measure
engine speed and spark timing. The output compare register
would set up the coil "on" time. As with the MC6805S2
devices, the MC68HCOSC4 software program has to service
the timer subsystem. The timer control register (TCR)
contains 5 bits of which 3 bits control interrupt flags associated
with the timer status register (TSR). The other two bits control
the input capture edge detector polarity and the output level
when the next successful output compare occurs. Fig. 4 shows
the bit definition for the TCR.
TSR contains only 3 bits which are READ ONLY. These three
bits indicate if an input capture transaction has occured, a
match has been found between the free running counter and
the output compare register, and if the free running counter
has rolled over. Fig. 5 shows the TSR and its bit definition.
Other internal specifications for the microcomputers listed
in this paper are fairly straightforward and can be obtained
from the manufacturer's product specifications [2]-[4].
III. DIGITAL INSTRUMENTATION SYSTEMS
The MC6805K2 device offers several features for automo-
tive instrumentation designs. The most important is the 128
bytes of EEPROM. This can essentially store 128 alphanu-
meric characters. Table I lists data that would be desirable to
retain for system functionality and serviceability. Service
diagnostics may include maximum values of vehicle speed,
engine RPM, and temperature. The vehicle ID and manufac-
turing codes could be accessed by the dealer's diagnostic
equipment, or possibly a home computer for the "do-it
yourself" car owner.
ARTUSI AND VALENTINE: NEW M6805 MICROCOMPUTERS 285

LO I
Fig. 6. MC6805K2 instrument cluster.

A digital instrument cluster block diagram is shown in Fig.

6. The SPI (Serial Peripheral Interface) port is utilized in this
design to update the various displays. This allows each display
driver to share the SPI data and clock lines. The remaining I/O
port lines are used to enable the appropriate driver. The
displays can, therefore, be updated either on a periodic basis
or on a required basis. In this system the RPM and vehicle
speed displays require a higher data rate than the odometer,
oil, fuel, and temperature displays. An update rate of 10 times
ndtasU per second for the RPM and odometer would be adequate.
Fig. 3. MC68HCO5C4 timer subsystem.
7 0
IV. SPI DESCRIPTION
TCR ICIE IOCI ITOIE |0e 0 0 1IEDCIOLVL Sl2
1
The use of the SPI port allows the microcomputer to
B7,ICIE - INPUT CAPTURE INTERRUPT ENABLE communicate with other logic networks at fairly high data
B6,OCIE - OUTPUT COMPARE INTERRUPT ENABLE rates. A review of the SPI shows that this serial data link is
B5,TO1E - TIMER OVERFLOW INTERRUPT ENABLE
B 1 IEDG - INPUT CAPTURE REGISTER TRIGGER SELECT quite versatile and can be adapted to mesh with several
O = FALLING EDGE I = RISING EDGE peripheral devices. A partial list is shown in Table II. What
BO,OLVL - OUTPUT COMPARE LEVEL SELECTR started as a simple input/output (I/O) technique for pin-limited
O = LOW OUTPUT 1 = HIGH OUTPUT
Fig. 4. MC68HC05C4 timer control register. microcomputers (MCU's) has evolved into the well-defined
standard SPI.
7 a
The availability of an on-board SPI in the MC6805S2 and
TSR IICF |OCF |TOF 0 ° |0° 0° 0 | 0° S13 the MC6805K2 microcomputers provides system flexibility.
B7,ICF - INPUT CAPTURE FLAG. SET BY INPUT The designer can use a standard MCU such as the MC6805S2
CAPTURE EDGE DETECTOR. CLEARED BY
ACESSING TSR AND INPUT CAPTURE
or the MC6805K2 and interface through the SPI to an external
REGISTER LOW BYTE. dedicated circuit to perform a specialized function [5], [6].
B6,OCF - OUTPUT COMPARE FLAG. SET WHEN OUTPUT The SPI provides a communication link from one MCU to
COMPARE REGISTER EGUALS TIMER VALUE.
CLEARED BY ACESSING TSR AND OUTPUT one or more other MCU's or hardware logic peripherals. It is
COMPARE REGISTER LOW BYTE. a means of sending data between devices without trying to get
B5,TOF - TIMER OVERFLOW FLAG. SET WHEN TIMER into major definition of protocols, packets, or mode/control
ROLLS OVER FROM SFFFF TO 0000. CLEARED
BY ACESSING TSR AND TIMER COUNTER bits. That definition is left to the user's software. This
LOW BYTE. ( Si 9) approach allows the user to configure a system using standard
Fig. 5. MC68HCO5C4 timer status register. off-the-shelf general purpose logic currents and/or MCU's. It
TABLE I
gives the user more flexibility in defining a serial protocol that
EEPROM DATA FOR INSTRUMENTATION CLUSTER suits the application, and avoids being trapped into one
particular bus configuration or peripheral type. The SPI circuit
EEPROM MEMORY MAP $80 - $FF has also been included in other microcomputers implemented
$80 SECURITY CODE VEHICLE ID in HCMOS technology such as the MC68HC05C4 and the
SECURITY CODE OWNER ID MC68HC 1 1.
I MILE INDEX SEAT POSITION 1 The SPI concept may use only two pins (data and clock) or
10 MILE INDEX SEAT POSITION 2 as many as four pins (data in, data out, clock, and slave select)
100 MILE INDEX MIRROR P05. 1 to transfer data from one device to another. Data transfers
1000 MILE INDEX MIRROR POS. 2 using a two-pin configuration are normally from an MCU to a
MAX RPM XI100 $9B [ ALARM ENTRY l simple peripheral such as an 8-bit serial input/parallel output
MAX ENG. TEMP
MIN OIL PRES.
device. A three-wire hookup is usually from a master MCU to
ENGLISH/METRIC
etc one or more slave MCU's, and a four-wire hookup is defined
as a system with multiple master and slave MCU's. The SPI
$8A I ECU CODES
may be interrupt driven to allow foreground/background
 286 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. IE-32 NO. 4, NOVEMBER 1985
TABLE II
SPI COMPATIBLE DEVICES

MCI 4499 7 SEG LED DVR

SPI WMCI 45001 4 SE LQ
4$000 44
~MCI SEG LCDDVR
MCI 45453 33 SEG LCD DVR
DISPLAY DRIVERS

MCI 45041 IC%211 8BIT A/D I

VOLTAGE INPUT
MC1441 10 60i 6BIT D/A
MC144111 4C 6BIT D/A VOLTAGE OUTPUT
MC68HC68A I 8Q1IOBIT A/D
DATA CONVERTORS
MC145155 14BIT N
MC145156 7BIT A IOBIT N
MC145157 I4BITNN TV TUNER
-MC145158 7BIT A IOBIT N CATV
MCl 45159 ANALOG PH DET AM/FM RADIO
PLL FREQ SYNTHESIZR

MCM68HC68RI/R2 128/256 RAI

MC68HC68TI REAL TIME COK
| b_mml- MC74HC165/166 8BIT SHIFr RE
r-_
-.- .r^ 4V-
^^^^Ar
OMPUTER
MC74HC299 8BIT BIDIRECTIONA SLfYSTEM
etc. SHIFT REGISTER
MPU BUS DEVICES

Fig. 7. SPI subsystem for MC6805S2/K2 MCU's.

software design, and data may be routed over two separate
wires allowing full duplex operations. Fig. 7 shows a block
diagram of the SPI subsystem used in the MC6805S2 and
MC6805K2 devices.
A system clock shifts data into or out of the data register
(MSB in first; MSB out first) in a synchronous fashion. Clock
timing is programmable for rising or falling edge transitions.
The fact that the SPI may be the master, clocking the slaves or
vice versa implies that the SPI clock may operate at different
speeds in a single system.
An MCU is considered a master when its slave select pin is
a logic high. The slave select pin acts as a chip select in a
multi-MCU system and allows devices to be addressed
individualy. To ensure that there is only one master control-
ling the system at a time, hardware constantly monitors the
slave select logic when the SPI is programmed as the master.
If a master is transmitting data and the slave select pin is pulled
data transfer has taken place. Two devices attempting to be
outputs are normally the result of software error; however, a
system protocol may be defined which contains a default
master, which automatically restarts the transfers when a
collision occurs [7].
There are two levels of the SPI circuit available to the user.
These two levels of SPI are implemented to ensure that the
user may serially communicate in either a synchronous or
asynchronous fashion. An MCU with a Level I SPI also has
the asynchronous Serial Communication Interface (SCI) cir-
cuit on-chip, whereas an MCU with a Level 2 SPI does not.
Level 1 SPI is available on the MC68HCO5C4 and
MC68HC11. The Level 2 SPI circuits are available on the
MC6805S2 and MC6805K2 MCU's.
A Level 2 SPI allows the user to cross couple on-chip
peripheral circuits to the SPI circuit thus increasing its
versatility and allowing the user to configure SCI line using
an

low, the master will relinquish the bus and become a slave. a combination of software and hardware' [8]. An RS-232
Also, a mode fault flag will be set to indicate that an error in interface with a maximum speed of 9600 baud is achievable by
ARTUSI AND VALENTINE: NEW M 6805 MICROCOMPUTERS 287

tying the receiver input to the Interrupt 2 input for synchroniz- PCI
7
SEC ImI I BY/AU W/E VPOx PGE PLE SOB
ing the on-chip clock to the center of the incoming bits. Cross
coupling of on-chip peripheral circuits allows a software/ B7,SEC - SECURITY BIT
B6,IVM - INTERNAL VOLTAGE MULTIPLER ENABLE
hardware combination to implement the Philips IIC bus (Inter B4,BY/BU - BYTE OR BULK OPERATION
IC bus) [9]. B3,WJE - WRITE OR ERASE SELECT
B2,VPON - VPP DETECTOR,READ ONLY
Despite the apparent complexity of control and the number B I ,PGE - PROGAMMING ENABLE
of bytes required or involved in the SPI operation, once the BO,PLE - ADDRESS/DATA LATCH ENABLE
control bits are initialized correctly they need not change. Fig. 8. MC6805K2 program control register.
Therefore, the SPI actually operates under control of only few
bits.
A Level 2 SPI uses the on-chip timer as the clock source in
the clock master mode, the maximum bit rate frequency is 125
kHz (Level 1 maximum is 1.05 MHz output and 2.1 MHz
input). Also the use of an on-chip timer allows a greater
selection of bit-rate frequencies.

V. USING THE EEPROM [10]

The MC6805K2 EEPROM feature requires a software
routine to initiate its operation. The 128 bytes of EEPROM in
the MC6805K2 are located in page zero of the address map,
from address $80 to address $FF, and can be accessed using
the direct addressing mode of the M6805. The direct mode
saves one byte of opcode over the extended addressing mode.
The EEPROM operation in the MC6805K2 is controlled via
the Program Control Register (PCR) shown in Fig. 8. The
control register PCR is an 8-bit register and is located at
address $OB.
The EEPROM in the MC6805K2 has two basic modes of
operation: READ and PROGRAM. In the READ mode the address
and data latches are transparent (bit PLE = I in PCR). The
EEPROM then operates as a ROM. Portions of the user's code
can be executed from the EEPROM. Execution of bit test and Fig. 9. MC6805K2 EEPROM operations.
branch instructions is allowed in the EEPROM memory space
if read operations are enabled by setting the PLE bit. The
erased EEPROM bits read as logical "'" s. test mode of the MC6805K2. The access to the EEPROM is
In the program mode (Fig. 9) four different program then limited to the on-chip user's software stored in the ROM.
operations can be selected by bit 4 and 3 (BY/BU and W/E) of This software can be designed to use some secret codes stored
the program control register (PCR), namely ERASE or WRITE, in the EEPROM. The security feature in the MC6805K2 can
and bulk ERASE or byte WRITE. These operations require a be used in an odometer application where safeguards against
programming voltage of 21 V applied to the VPP pin, or in the tampering have to be built into the system.
case of 5-V only systems, turn on of the on-chip voltage The only way to erase the security bit is by a bulk erase to
multiplier, which is done by clearing the IVM bit (bit 6) of the the EEPROM array. To avoid unauthorized erase of the
PCR. The internal voltage multiplier is turned off by setting EEPROM array and reprogramming it with new values, a
the same bit. software "trap" can be built into the software. A factory
The programming voltage generated by the internal voltage assigned character is programmed into the EEPROM and the
multiplier is simultaneously applied to the VPP pin and on the main program checks if this value exists before starting
internal EEPROM data/address decoders. The monitoring of execution of the rest of the program. Should this byte not be
the programming voltage VPP is done through bit 2, VPON, present because of a bulk erasure, then the program will abort
of the PCR. The VPON detector clears bit 2 of the PCR when execution.
the programming voltage is present on the VPP pin. Additional flexibility is provided in the MC6805K2 by
The security bit is an additional EEPROM bit control including a standby supply input for the lower 16 bytes of the
register (PCR bit 7). This unique feature protects the integrity 96 bytes of on-chip RAM. These 16 bytes of RAM can be
of the data contained in the EEPROM, from nonauthorized battery backed-up and used to extend the amount of nonvola-
external access. When the security bit SEC (bit 7 of PCR) is tile memory available in the MC6805K2.
programmed to zero it disables the nonuser mode (NUM) or Some of the applications which can take advantage of the
288 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. IE-32, NO. 4, NOVEMBER 1985
MC6805K2's EEPROM are:
engine tune-up calibration tables;
odometer/speedometer;
seat positioning information for multiple drivers;
radio station memory;
DIP switch replacement for module configuration;
keyless entry systems (Driver ID);
maintenance reminder;
system configuration information.
VI. SUMMARY
As the microcomputer technology continues its evolution
towards more complex and powerful single-chip microcontrol-
lers, automotive system designers will be able to incorporate
sophisticated features that were not economically feasible just
a few years ago. The use of standardized serial bus ports will
allow systems to be configured with minimal interconnections.
The EEPROM technology when used in a single-chip MCU,
greatly increases the usefulness of MCU-based automotive
systems.
REFERENCES
[1] P. E. V. Philips and M. W. Lowndes, "Microprocessor based
ignition-an innovative solution," Motorola Ltd., Milton Keynes,
England, Nov. 1983.
[2] Motorola Inc., MC6805S2 data sheet, 1984.
[31 Motorola Inc., MC68HC05C4 data sheet, 1984.
[4] Motorola Inc., MC6805K2 design spec., Internal Doc., May 7, 1984.
[5] D. R. Gonzales, "SPI bus eases multiple MCU hookup," Design
News, pp. 89-95, May 7, 1984.
[61 M. Gallup, "The serial peripheral interface enhances system expan-
sion," presented at Electro/84 Conf., Boston, MA, May 1984.
[7] D. R. Gonzales, "SPI bus eases multiple MCU hookup," Design
News, pp. 89-95, May 7, 1984.
[8] - , Appl. Note AN-901, Motorola Inc., May 1984.
[9] Philips International BV, HC Bus Spec.
[10] P. M. Yates, "Application of non-volatile memory in automobile
odometers," Lucas Electrical Electronics and Systems Limited, En-
gland, 1983.