library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity EXAM is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
F : out STD_LOGIC);
end EXAM;

architecture Behavioral of EXAM is

begin

F <= A OR ((NOT B) AND C);

end Behavioral;
1.-1111101Bin_Dec 125

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4.-5EFHEX_BIN 10111101111

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