Electronics 2

3. Junction Field Effect

Transistor (JFET)
Review
Dr. Abdessattar Bouzid
Electrical Engineering Department
Faculty of Engineering & Islamic Architecture
Umm – Al Qura University
abdessattar_bouzid@yahoo.fr

Umm Al-Qura
Electrical Engineering Department
Faculty of Engineering and Islamic Architecture
Electronics 2 – Dr. Abdessattar Bouzid 1
 Chapter Outline

• The JFET.

• JFET Characteristics and Parameters.

• JFET Biasing.

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Electrical Engineering Department
Faculty of Engineering and Islamic Architecture
Electronics 2 – Dr. Abdessattar Bouzid 2
 Chapter Objectives

• Discuss the JFET and how it differs from the BJT.

• Discuss, define, and apply JFET characteristics and
parameters.
• Discuss and analyze JFET biasing.
• Discuss the ohmic region on a JFET characteristic
curve.

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Electrical Engineering Department
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 Introduction

• Field effect transistors control current by voltage

applied to the gate.
• The FET’s major advantage over the BJT is high input
resistance.
• Overall, the purpose of the FET is the same as that of
the BJT.

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Electrical Engineering Department
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 Review

• Semiconductor (Silicon).
• N type material.
• P type material.
• P-N Junction.
• Depletion.

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 A Silicon Atom (Si)

• Basic building material of most integrated circuits.

? ? Has 4 valence electrons.

The outer electron shell
Si needs 8 to be “full”.
Silicon will try to lend or
? ? borrow 4.

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 Silicon (group 4) bonds

Si Si Si Si

Si Si Si Si

Si Si Si Si

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 A Pure Silicon Crystal Lattice

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 An Arsenic Atom (As)

?
Has 5 valence electrons.

One surplus for fitting in

As to the lattice.

? ?

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 Arsenic Doping (group 5) – N type

Si Si As Si

-
Si Si Si Si

-
Si As Si Si

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 A Gallium Atom (Ga)

?
? ? Has 3 valence electrons.
One short for fitting in to
Ga the lattice.

? ?

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 Gallium Doping (group 3) – P type

Si Ga Si Si

Si Si Si Si

+
Si Si Ga Si

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 P-N Junction

N Type Depleted P Type

Si Si Si Si As Si Si Si Si Si Si Si

- +
Si As Si Si Si Si Ga Si Ga Si Si Si

Si Si As Si Si Si Si Ga Si Si Si Ga

- +

Si Si Si Si As Si Si Si Si Si Si Si

- +
Si As Si Si Si Si Si Si Ga Si Si Si

Si Si As Si Si As Si Ga Si Si Si Ga

- +

Si Si Si Si As Si Si Si Si Si Si Si

- +
Si As Si Si Si Si Ga Si Ga Si Si Si

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Electrical Engineering Department
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 What causes the depletion?

• Electrons move from left to right to fill the + holes.

• Where electrons and holes combine the area is “depleted”
of current carriers.
• This leaves the left (N Type) positive so eventually this
prevents the depletion spreading any more.
• Applying negative to N type replaces the depleted carriers
and the current resumes (Forward biased diode).
• Applying positive to the N type removes more electrons
and increases the depletion. Almost no current flows
(Reverse biased diode).

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 Field Effect Transistor (FET)

• A Field-Effect Transistor (FET) has a gate (G) terminal which

controls the current flow between the other two terminals, source
(S) and drain (D).
• In simple terms, a FET can be thought of as a resistance
connected between S and D, which is a function of the gate
voltage VG.
• The mechanism of gate control varies in different types of
FETs, e.g., JFET, MOSFET.

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 Field Effect Transistor (FET)

• FETs can be used for analog and digital applications.

In each case, the fact that the gate is used to control
current flow between S and D plays a crucial role.
• Two main types of FET:
- JFET: Junction Field Effect Transistor.
- MOSFET: Metal Oxide Semiconductor Field
Effect Transistor.
• D-MOSFET ~ Depletion MOSFET
• E-MOSFET ~ Enhancement MOSFET

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 JFET - Labels

• The terminals of a JFET are the source, gate, and drain.

• A JFET can be either p-channel or n-channel.

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 FET vs BJT

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 FET vs BJT

BJT FET

Bipolar: two types of carriers (electrons Unipolar: Only one type of carrier (electrons
and holes) are participating. or holes).

Current-controlled device. Voltage-controlled device.

High input impedance (can be used as a
Low input impedance.
buffer).
Carriers move through the base by Carriers move through the channel by drift
diffusion process. process.
Has a higher switching speed due to the drift
Has a comparatively lower switching
process; the drift of the carrier is faster than
speed due to the diffusion process.
diffusion.
Linear (Ic ≈ Ib) Nonlinear (ID ≈ Vgs2)
In case of IC fabrication, the BJT requires In case of IC fabrication, the FET requires
more space than the FET. less space than BJT.

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 Junction Field Effect Transistor (JFET)

• The JFET in its simplest form is

essentially a voltage controlled
resistor.
• The resistive element is usually a bar
of silicon.
• For an N-channel JFET this bar is an
N-type material sandwiched between
two layers of P-type material.
• The two layers of P-type material are
electrically connected together and
are called the gate.

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 Junction Field Effect Transistor (JFET)

• One end of the N-type bar is called

the source and the other is called the
drain.
• Current is injected into the channel
from the source terminal, and
collected at the drain terminal.
• The interface region of the P- and the
N-type materials forms a P-N
junction.

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Electrical Engineering Department
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 Junction Field Effect Transistor (JFET)

• If the channel is doped with a donor impurity, n-type material is

formed and the channel current will consist of electrons.

• If the channel is doped with an acceptor impurity, p-type

material will be formed and the channel current will consist of
holes.

• N-channel devices have greater conductivity than p-channel

types, since electrons have higher mobility than do holes; thus n-
channel JFETs are approximately twice as efficient conductors
compared to their p-channel counterparts.

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Electrical Engineering Department
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 Junction Field Effect Transistor (JFET)

• In addition to the channel, a JFET

contains two ohmic contacts: the
source and the drain.

• The JFET will conduct current

equally well in either direction and
the source and drain leads are usually
interchangeable.

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 JFET Operation
• JFET operation can be compared to a water spigot:

• The source of water pressure – accumulated electrons at the negative

pole of the applied voltage from Drain to Source
• The drain of water – electron deficiency (or holes) at the positive pole of
the applied voltage from Drain to Source.
• The control of flow of water – Gate voltage that controls the width of
the n-channel, which in turn controls the flow of electrons in the n-
channel from source to drain.
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 A Biased N-Channel JFET

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 JFET Operating Characteristics

There are three basic operating conditions for a JFET:

1. VGS = 0, VDS increasing to some positive

value.
2. VGS < 0, VDS at some positive value.
3. Voltage-Controlled Resistor.

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 VGS = 0, VDS Increasing to Some Positive Value

Three things happen when VGS = 0 and VDS is

increased from 0 to a more positive voltage:
• When we apply a drain-source voltage (VDS > 0), a
current starts to flow from drain to source (ID).

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 VGS = 0, VDS Increasing to Some Positive Value

• If we increase VDS, the depletion region between p-gate and

n-channel increases at the drain end of the channel.
• Increasing the depletion region, decreases the width of the
n-channel which increases the resistance of the n-channel.
• But even though the n-channel resistance is increasing, the
current (ID) from Source to Drain through the n-channel is
increasing. This is because VDS is increasing.

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 VGS = 0, VDS Increasing to Some Positive Value

• Once again, increasing VDS causes the depletion region to

spread farther into the channel. This results in a
corresponding increase in channel resistance due to the
reduction of channel cross section area.
• The voltage at which the two depletion regions just touch in
the middle of the channel is called the drain saturation
voltage or the pinch-off voltage (Vp).

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 VGS = 0, VDS Increasing to Some Positive Value

• Operation of the JFET at voltages below and above the

pinch-off voltage are referred to the linear (or resistive) and
saturation regions, respectively.
• Above Vp, changes in VDS cause little change in ID.
• ID maintain the saturation level defined as IDSS.

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 VGS = 0, VDS Increasing to Some Positive Value

• Once VDS > VP, the JFET has the characteristics of a current
source.
• As shown in figure, the current is fixed at ID = IDSS, the
voltage VDS (for level >VP) is determined by the applied
load.
• IDSS is the max drain current for a JFET and is defined by the
conditions VGS = 0V and VDS > | Vp|.

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 VGS = 0, VDS Increasing to Some Positive Value

At the pinch-off point:

• Any further increase in VDS produces

very little increase in ID. VDS at
pinch-off is denoted as Vp.

• ID is at saturation or maximum. It is
referred to as IDSS.

• The ohmic value of the channel is at

maximum.

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 JFET Typical Operation

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 JFET Model

• JFET model when ID=IDSS, VGS=0, VDS>VP.

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 VGS < 0, VDS at Some Positive Value

• VGS is the controlling voltage of the JFET.

• For n-channel devices, the controlling voltage VGS is made
more and more negative from its VGS = 0V level.
• The effect of the applied negative VGS is to establish
depletion regions similar to those obtained with VGS = 0V
but at lower level of VDS (to reach the saturation level at a
lower level of VDS).

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Electrical Engineering Department
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 VGS < 0, VDS at Some Positive Value

• If we decrease VGS (VGS = -V1), the depletion region spread

into the channel, which causes an increase of the channel
resistance.
• In this region, JFET can actually be employed as a variable
resistor whose resistance is controlled by the applied gate to
source voltage (VGS).

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 VGS < 0, VDS at Some Positive Value

• As VGS becomes more and more negative; the slope of each

curve becomes more and more horizontal.
• When VGS= -VP= with VDS= 0, the two depletion layers
touch over the entire channel length and the whole channel is
closed.
• The channel said to be off (ID = 0).
• VGS(off) = -Vp.

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 Voltage-Controlled Resistor

• The region to the left of the

pinch-off point is called the
ohmic region.
• The JFET can be used as a
variable resistor, where VGS
controls the drain-source
resistance (rd). As VGS becomes
more negative, the resistance (rd)
increases.

ro
r =
d
(1 − VGS )2
VGS(off)

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Electrical Engineering Department
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 And as Summary in Practical…

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 Transfer Characteristics

• The transfer characteristic of input-to-output is not

as straight forward in a JFET as it was in a BJT.

• In a BJT, β indicated the relationship between IB

(input) and IC (output).

• In a JFET, the relationship of VGS (input) and ID

(output) is a little more complicated:
VGS 2
ID = IDSS(1 − )
VGS(off)
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 Transfer Characteristics

• From this graph it is easy to determine the value of ID for a

given value of VGS.

Transfer Curve

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 JFET Transconductance

VGS 2
ID = IDSS(1 − )
VGS(off)
• The JFET transconductance is defined by:
∆I D
gm = Siemens (S)
∆V GS

 V GS 
=
g m g m 0 1 − 
 V GS (off )
 

2I DSS
gm0 =
V GS (off )

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 JFET Transconductance

I D (mA)
What is the transconductance for
the JFET at the point shown? 10 mA

8.0

6.0 5.7
4.0 3.7
2.0
∆I D 5.7 mA − 3.7 mA
=
gm = –VGS
∆VGS −0.7 V − (−1.3 V) −4 −3 −2 −1 0
−1.3 −0.7
2.0 mA
= = 3.33 mS
0.6 V

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 JFET Transconductance

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 JFET Datasheet

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 JFET Terminal Identification

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 JFET Input Resistance

• The input resistance of a JFET is given by:

VGS
RIN =
I GSS

Where IGSS is the current into the reverse biased gate.

• JFETs have very high input resistance, but it drops when the
temperature increases.

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 JFET Input Resistance

Compare the input resistance of a 2N5485 at 25 oC and

at 100 oC. The specification sheet shows that for VGS = -
20 V, IGSS = 1 nA at 25 oC and 0.2 µA at 100 oC.

VGS 20 V
At 25 oC, =
RIN = = 20 GΩ!
I GSS 1 nA
VGS 20 V
At 100 oC, =
RIN = = 100 MΩ
I GSS 0.2 μA

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 JFET Biasing

• Just as we learned that the bipolar junction transistor must be

biased for proper operation, the JFET must also be biased for
operation.

• Let’s look at some of the methods for biasing JFETs.

• In most cases the ideal Q-point will be the middle of the

transfer characteristic curve, which is about half of the IDSS.

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 JFET Biasing – Self Bias

• Self-bias is the most common type of biasing method for

JFETs. No voltage is applied to the gate.

• Gate terminal is connected to

ground through resistance RG.
• A supply voltage of +VDD is
connected for n-channel JFET
and ‒VDD for p-channel JFET.

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 JFET Biasing – Self Bias

V GS =V G −V S =0 − I D R S

V GS = −I D R S

V DS = V D −V S = V DD − I D (R D + R S )

• It is usually desirable to bias the JFET near the midpoint of its

transfer characteristics (at ID = IDSS/2). This allows the maximum
amount of current swing between 0 and IDSS. At this current value,
VGS = VGS(off) /3.4.

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 JFET Biasing – Self Bias

+VDD = +12 V
Assume the resistors are as shown in
the figure and the drain current is 3.0
RD
mA. What is VGS? 1.5 kΩ

VG = 0 V

+ IS
RG RS 330 Ω
VG = 0 V; VS = (3.0 mA)(330 Ω) = 0.99 V 1.0 MΩ –

VGS = 0 – 0.99 V = − 0.99 V

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 JFET Biasing Q-Point

Setting the Q-point requires us to determine a

value of RS that will give us the desired ID
and VGS . The formula below shows the
relationship.
RS = | VGS/ID |

To be able to do that we must first determine

the VGS and ID from either the transfer
characteristic curve or more practically from
the formula below. The data sheet provides
the IDSS and VGS(off).
VGS is the desired voltage to set the bias.
ID = IDSS(1 - VGS/VGS(off))2 Transfer characteristic curve

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 JFET Biasing Q-Point

What value of RS should you I D (mA)

use to set the Q point as 10 mA
shown? 8.0

6.0

Q 4.0

The Q point is approximately at 2.0

ID = 4.0 mA and VGS = −1.25 V. –VGS

−4 −3 −2 −1 0
VGS 1.25 V
=
RS = = 375 Ω
ID 3.0 mA

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 JFET Biasing – Midpoint Biasing

Since midpoint biasing is most

common, let’s determine how this is
done.
Step 1. The value of RS determine the
approximate midpoint bias. Half of
IDSS would be ID midpoint. The VGS to
establish this can be determined by
the formula below.
Step 2. VGS ≅ VGS(off)/3.4

ID = IDSS /2, when VGS = VGS(off)/3.4

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 JFET Biasing – Midpoint Biasing

The value of RS needed to

establish the computed VGS can
be determined by the previously
discussed relationship below.
Step 3. RS = | VGS/ID |

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 JFET Biasing Q-Point

The transfer characteristic curve along with

other parameters can be used to determine the
midpoint bias Q-point of a self-biased JFET
circuit.
First determine the VGS at IDSS from the
Load Line
formula below.
VGS = -IDRS
Intersect
#1 VGS = -IDRS = (0)(470Ω) = 0V (ID = IDSS/2)
#2 VGS = - IDRS =(10mA)(470Ω)= -4.7V
Where the two lines intersect gives us the ID
and VGS (Q-point) needed for midpoint bias.
#1
#2

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 JFET Biasing Voltage-Divider Bias

• Gate terminal is connected to

voltage-divider between VDD and
ground.
• A supply voltage of +VDD is
connected for n-channel JFET and
‒VDD for p-channel JFET.

R2
V GS = V G −V S = V DD − I D R S
R1 + R 2

V DS = V D −V S = V DD − I D (R D + R S )

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 JFET Biasing Graphical Analysis

In using the transfer characteristic curve to

determine the approx. Q-point, we must
establish the two points for the load line.
The 1st point is for ID = 0.
(Note: VGS = VG when ID = 0).
VGS = VG = (R2/R1 + R2)VDD
The 2nd point is ID when VGS
is 0.
ID = VG/RS

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 Conclusion

This lecture of the JFET illustrates that:

1. The JFET is basically a voltage controlled resistor.

2. The JFET operates as a depletion mode device.

3. The JFET performs as a voltage controlled current

amplifier.

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