A 230ns Settling Time Type-I PLL with 0.

96mW
TDC Power and Simple TV Calculation Algorithm
Ja-Yol Lee, Mi-Jeong Park Hyun-Kyu Yu, Cheon-Soo Kim
RF/Analog Circuit Lab, ETRI RF/Analog Circuit Lab, ETRI
Daejeon, Korea Daejeon, Korea
ljylna@etri.re.kr cskim@etri.re.kr

Abstract— This paper describes a fast-settling all-digital PLL

with a low-power TDC based on retimed reference clock and a
lock detector focused on monitoring a toggling phase error. With
the intention of reducing power dissipation, the proposed TDC
employs the low-rate reference (CK¦ref) and retimed reference
(CK¦ros) clocks to measure the fine fractional phase error
between the low-rate reference (CK¦ref) and high-rate oscillator
(CK¦osc) clocks. In addition, the use of the retimed reference
clock to the TDC results in a new simple DCO clock period (TV)
calculation algorithm which employs the maximum and
minimum values for the fractional error correction (e). A lock
detector, which is required to accomplish the switchover of the
DCO frequency tuning mode, allows a fast settling to be actuated
independent of loop bandwidth and frequency step. By
dissipating 8mW at 1.2-V supply voltage, the proposed digital
PLL achieves 230ns settling time, 1.7psrms period jitter.

Keywords— PLL, DCO, TDC, phase-error compensation Fig. 1. Proposed ADPLL with TDC operating both CK¦ref and CK¦ros

I. INTRODUCTION present a new TV calculation algorithm to normalize phase

One attempt for low-power and low-cost transceiver is to
develop digital-like RF/analog circuits [1][2]. An example is
all-digital phase-locked loop (ADPLL) in which all input-
output signals are digital and processed arithmetically [3]-[10].
One of key components is a time-to-digital converter (TDC)
dominating in-band phase noise. TDC contains two basic
problems to be addressed. First, metastability in sampling
device, which originates from asynchronous nature of reference
clock and oscillator clock, results in data reading error in its
latch circuit. Another problem is that the TDC consumes much
more power than other digital blocks excluding high-speed
counter; a high-speed clocking for the delay buffer increases
both dynamic and short current power in proportion to clock
speed [7]. Also, when DCO drives such heavy loads as 50-W
measurement systems, a DCO phase accumulator, and TDC
delay buffers, much more power becomes consumed in the
DCO and its buffer. Therefore, a direct drive on the TDC delay
buffer by the oscillator clock, CK¦osc, aggravates power burden
on the DCO. In conventional TDC [1], the number of delay
buffer corresponding to two DCO clock periods is required to
measure DCO clock period (TV) whereas the proposed TDC
using oversampled reference clock (CK¦ros) needs only the
delay buffers corresponding to one DCO period. In this paper,
we propose a low-rate oversampled reference clock-based TDC
to address metastability and large power consumption, and also
error detected by time-to-digital converter.
II. PROPOSED ADPLL ARCHITECTURE
The proposed TDC digital PLL of Fig. 1 consists of a DCO,
a reference phase accumulator, a DCO phase counter, a TDC, a
loop gain controller. TDC measures very small time intervals
between reference clock (CK¦ref), and oversampled reference
(CK¦ros) unlike the conventional TDC operation proposed in
[1]. In the loop gain control block of Fig. 1, lock detector
generates a pulse to indicate loop locking-state, and one of the
three DCO operating modes such as PVT, Acquisition, and
Tracking, is selected by the mode switch block. From now, a
brief description for the PLL operation will be given here.
Phase error, fE[k], is calculated through the phase detector
arithmetic operation using digitally-converted three phase
values such as FCW reference phase (RR[k]), fractional phase-
error correction (e[k]), and sub-sampled DCO phase (Rv[k]).
And then, the calculated phase error is tracked by the closed
PLL loop. The tracking operation is constantly repeated until
phase error become zero or constant, resulting in phase locking.
A. Proposed TDC Operation
Since the DCO clock-edge counting is used to estimate
phase error, the phase-error detecting resolution in the integer
precision configuration cannot be finer than a half cycle of the
DCO clock. And much finer phase quantization under a half

978-1-4799-4132-2/14/$31.00 ©2014 IEEE 370

period (sub-Tv) is essential in wireless applications requiring
low phase noise. In many ADPLLs [1]-[6], accordingly, the
fractional phase error, e, is measured using TDC whose time
quantization resolution is a buffer delay time, Dtinv. Fig. 2 (a)
illustrates the block diagram of calculating fractional phase
error, e, i.e. the time interval between reference clock and next
significant rising edge of DCO clock [1] or between reference
clock and the rising edge of the oversampled reference clock,
as illustrated in Fig. 2 (b). The fractional time difference, e
(sub-TV), is expressed as a fixed-point digital word, i.e. to be
more specific given as the number of delay buffer. In the (a)
phase detecting system, the use of rough TDC output putting
on integer form should be avoided because its unit time
resolution is a varying physical parameter: that is, buffer delay
time is varying under PVT environment with the development
of time, and then the fractional error correction, e[k],
represents no constant value, which results in serious jitter or
phase noise. For the purpose of eliminating PVT variation
under the PLL steady state, therefore, the raw TDC output has
to be normalized by DCO clock period (TV) [1], as shown in
Fig. 2 (a), and only the normalized fractional phase-error
correction, en[k], is used in the phase detector. (b)
Fig. 2 (b) illustrates the timing diagram to measure the very Fig. 2. (a) Proposed TDC architecture, and (b) operating timing waveforms.
small time interval between CK¦ref rising edge and next CK¦osc
rising edge when the delayed CK¦osc phases are sampled using clock in the TDC, which has benefit of low power [12]. In Fig.
an array of registers whose Q outputs make up a pseudo- 2 (a), e is measured by passing CK¦ref through a chain of delay
thermometer code in fractional phase-error estimation [1]. buffers whose outputs are then sampled by an array of
From the outputs of sampling registers, the edge detector finds
out the position changing from ‘1’ to ‘0’, which indicates a sampling registers at the rising-edge of oversampled clock,
quantized time delay, Dtr, between CK¦ref sampling edge and CK¦ros. And since the sampling registers outputs form a
previous CK¦osc rising. Likewise, the position of the transition pseudo-thermometer code, there will be a series of 1’s and 0’s.
detected from ‘0’ to ‘1’ denotes the quantized time interval of As only the position changed from ‘1’ to ‘0’ is searched by
Dtf between CK¦ref sampling edge and CK¦osc falling edge [1]. using thermometer code, the proposed TDC edge-detection
Since CK¦ref rising edge develops behind both CK¦osc rising algorithm is much simpler than conventional one.
and falling edges as shown in Fig. 2 (b), both the time intervals
B. Fractional Phase-Error Estimation
have to be interpreted as positive values. In the TDC operating
timing waveforms of Fig. 2 (b), DCO clock half period is used For calculating a DCO clock period, it is necessary to
to calculate both positive and negative phase errors [1]. measure fractional time interval constantly until the difference
Equations of calculating en are rather complicated because the between emax and emin, corresponding to one DCO period, is
quantized time parameters such as Dtf, Dtr and TV have to be estimated as shown in the TV normalization block of Fig. 3 (a).
estimated beforehand [1]. In (1), it has been found out through simulation that the DCO
Fig. 2 (a) illustrates the proposed fractional phase-error clock period, TV, is equal to the difference between the
estimation. The proposed TDC is similar to the conventional maximum time interval, emax, and the minimum time interval,
one, but its input operating frequencies are quite different [1]. emin.
In Fig. 2 (a), CK¦ros is to oversample reference clock (CK¦ref)
by the high-rate DCO clock (CK¦osc), and used to estimate the T = ε  − ε  (1)
fractional phase error as observed in Fig. 2 (b). A closer look
at the proposed clock scheme of Fig. 2 (b) reveals the fact that Once both emax and emin are detected, their difference value is
the time interval between CK¦ref rising edge and next CK¦ros maintained until their new values are updated every 64th
rising edge corresponds to fractional phase-error (e) between reference clock. The calculated TV is constantly changing
CK¦ref edge and next CK¦osc rising edge. When a low- because DCO frequency varies during unlocked state as
frequency clock is oversampled to a high-frequency clock, the demonstrated in Fig. 3. In Fig. 2 (b), since e is directly
edge information of high-frequency clock is preserved in the measured without estimating Dtf and Dtr, its calculation
low-frequency retimed clock. Therefore, it is possible to process is straightforward compared with the conventional
calculate fractional phase error without using high-rate DCO fractional phase-error estimation [1]. Therefore, the

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normalized fractional phase-error correction, en[k] of (2), is
obtained by simply dividing e by TV, at positive and negative
phase errors.


ε =  (2)


In Fig. 3 (a), the TV normalization block calculates the

variable DCO clock period, TV, and produces en. The
(a)
normalization block consists of a emax_hold block, a emin_hold
block, an adder, a TV update block, and a memory. The edge
detector receives 32-bit sampled output TDC_Q [31:0] from
previous register array, and then provides 6-bit e with the two
e-estimation blocks: emax_hold is for evaluating maximum e
value and emin_hold for minimum e value. A full DCO clock
period TV is calculated via the subtraction after calculating
emax and emin. In Fig. 3 (b), the emax_hold block updates e larger
than the previous one every reference clock until the largest
value for e is detected. Likewise, the emin estimation block
holds current minimum value until it detects smaller e value. If
the new values of both emax and emin are evaluated, the TV
update block renews TV value of (1) every Ud_En trigger
signal, which is generated every 64th reference clock. In (1), e (b)
is divided by TV to be normalized, which is much complicated
to realize divider in terms of hardware, and therefore a simple
memory is used to provide the normalized value, en. An array
of 14-bit digital words, corresponding to inverse TV values
between 1/4 and 1/32, are pre-calculated and stored in the
memory. Finally, the normalized fractional phase-error
correction is computed by multiplying raw fractional phase
error e by1/TV. At the startup of PLL, the pre-calculated value
of 1/TV preset to a target PLL output frequency can be loaded
into TV normalization block until TV value is calculated using (c)
(1). Fig. 3. (a) Tv normalization block, (b) Tv estimation block, and (c) Tv update
enable signal block
For the purpose of making easy calculation of TV and
obtaining the linear transfer characteristic of 1/TV, it is
desirable to take a long-term average for the DCO clock
period TV [1]. However, the proposed TDC outputs the
updated TV value every 64th reference clock cycle. As shown
in Fig. 3 (c), the TV-update enable block consists of a 6-bit
accumulator, a 6-bit comparator, and a MUX. The MUX
selects between logic High and Low, depending upon the
comparator output, which changes from “LOW” to “HIGH” in
the case that the accumulator represents 64. The normalized
fractional phase error, en[k], is made up of 16-bit digital words
whose MSB bit is used as the carry input of integer phase
detector. The other 15-bit digital words of en[k] are input into
the 15-bit fractional phase detector [1]. Fig. 4 Simulated results for TV-normalized block and edge detector.
Fig. 4 represents simulation results for both TV-normalized
block and edge detector. The edge detector estimates how
every reference clock. And both emax and emin are detected as
many delay buffers are passed through by reference clock for
28 and 5, respectively. The estimated Tv value (Est_TV = 23)
the quantized time difference e i.e. detects the pattern changed is equal to the initial value (Preset_TV). The estimated TV
from ‘1’ to ‘0’. In Fig. 4, the edge detector output value or value represents one period of 2170MHz clock with buffer
waveform, i.e e does randomly change between 5 and 28 delay time of 20ps.

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 III. MEASUREMENT RESULTS TABLE I. PERFORMANCE COMPARSION

Fig. 5 represents the implemented chip photograph for [3] [8] [9] This
2GHz ADPLL using 90nm low-power CMOS process 90nm 90nm 0.18μm 90nm
Technology
technology. Fig. 6 shows the measured jitter noise of 1.7ps. CMOS CMOS CMOS CMOS
Table I summarizes the proposed TDC performance results Supply 1V 1.3V 1.8V 1.2V
Minimum
and provides comparison with previously reported TDC 0.75ps 20ps 1.25ps 20ps
resolution
measurements. The designed TDC consumes lowest power of
Operating
0.96mW at 1.2 V. The DCO tuning range is from 1.8GHz to 1.68GHz 26MHz 60MHz 30MHz
Frequency
2.2GHz. With an area of 0.35mm2, the PLL achieves a fast Power
settling time of 230ns that has been obtained by monitoring 70mW 1.8mW 1.8mW 0.96mW
consumption
phase error settling behavior [12].

IV. CONCLUSION
The paper demonstrated a 2-GHz low-power ADPLL with a
new fractional phase-error estimation algorithm. The proposed
TDC uses both reference clock and oversampled reference
clock to detect fractional phase error en. Since the high-rate
input operating clock of the delay buffer chain in TDC is
decimated to a much lower rate reference clock, the operating
Fig. 5. Chip die photograph power of the TDC is reduced. The new TV estimation
algorithm of using emax/emin is also proposed to diminish the
number of delay buffer and alleviates TV-calculation
complexity.

REFERENCES
[1] R. B. Staszewski, et al., “All-digital TX frequency synthesizer and
discrete-time receiver for Bluetooth radio in 130nm CMOS,” IEEE J.
Solid-State Circuits, vol. 39, no.12, pp. 2278-2291, Dec. 2004.
[2] V. K. Parikh, P.T. Balsara, and O. E. Eliezer “All digital–quadrature -
modulator based wideband wireless transmitters,” IEEE Trans. Circuits
and System I, vol. 56, no 11, pp 2487-2497, Nov, 2009.
[3] M. Lee et al., “A low-noise wideband digital phase-locked loop based on
a coarse-fine time-to-digital converter with subpicosecond resolution,”
IEEE J. Solid-State Circuits, vol. 44, no.10, pp. 2808-2816, Oct. 2009.
[4] S. Yang et al., “A 7.1mW, 10 GHz all digital frequency synthesizer with
dynamically reconfigured digital loop filter in 90 nm CMOS technology,”
IEEE J. Solid-State Circuits, vol. 45, no.3, pp. 578-586, March 2010.
[5] E. Temporiti et al., “A 3.5 GHz wideband ADPLL with fractional spur
suppression through TDC dithering and feedforward compensation,”
Fig. 6. Measured jitter noise. IEEE J. Solid-State Circuits, vol. 45, no.12, pp. 2723-2736, Dec. 2010.
[6] Liangge Xu et al., “A 2.4-GHz low-power all-digital phase locked loop,”
IEEE Custom Integrated Circuits Conference, pp.331-334, Sep, 2009.
[7] Dake Liu and C. Svensson, “Trading speed for low power by choice of
supply and threshold voltages,” IEEE J. Solid-State Circuits, vol. 28,
no.1, pp. 10-17, Jan. 1993.
[8] R. B. Staszewski, et al., “1.3V 20ps time-to-digital converter for
frequency synthesis in 90-nm CMOS,” IEEE Trans. Circuits and
SystemII, vol. 53, no.3, pp. 220-224, Mar. 2006
[9] Seon-Kyoo Lee, et al., “A 1GHz ADPLL with a 1.25ps minimum-
resolution sub-exponent TDC in 0.18μm CMOS,” IEEE International
Solid-State Circuits Conference, vol. 45, no.12, pp. 2874-2881, Dec.
2010.
[10] Younggun Pu, et al., “Low-power, all-digital phase-locked loop with a
wide-range, high-resolution TDC,” ETRI Journal, vol. 33, no.3, pp. 366-
2373, Jun. 2011
[11] Seon-Kyoo Lee, et al., “A 1GHz ADPLL with a 1.25ps minimum-
resolution sub-exponent TDC in 0.18μm CMOS,” IEEE International
Solid-State Circuits Conference, vol. 45, no.12, pp. 2874-2881, Dec.
2010.
[12] J. Y. Lee, et al., “A 4-GHz all digital PLL with low-power TDC and
Fig. 7. Measured settling time. phase-error compensation,” IEEE Trans. Circuits and System-I: Reg.
Papers, vol. 59, no.8, pp. 1706-1719, Aug. 2012.

The study was supported by the Ministry of Knowledge Economy, in

Korea (KI001915).

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