DIGITAL COMPUTER SWITCHING OF

HIGH VOLTAGE SUBSTATIONS

BY

ANIBAL TRAQA DE CARVALHO ALMEIDA

A Thesis Submitted for the Degree of Doctor

of Philosophy in Engineering

Department of Electrical Engineering

Imperial College of Science and Technology

University of London

March 1977
 2

ABSTRACT

This thesis is concerned with the use of digital computers

to control switching operations in high voltage substations.

A model of a 4CC kV mesh substation was constructed and

interfaced to a control processor from which it receives the

switching instructions on-line. A data acqUisition processor is

used to obtain digital and analogue data from the substation thro,Igll

suitable transducers. The data is transferred into the the core

of the control processor using a direct memory access and E.n

intermediate first-in first-out store, designed by the author

to give a rapid response to system changes.

Fault switching programs are developed to clear a fault

with back-up and reclosing facilities implemented automatically

by the control computer acting on the model.

Representation of the state of the substation and the

adjacent networks together with a method of configuration analysis

are presented which can be used to increase the reliability of

manual switching or to achieve a correct sequence of operations

when passing automatically from one configuration to another.

Finally an extension of conventional switching constraints

is used to increase the quality and reliability of switching

operations.
 3

To my Wife
 ACKNOWLEDGMENTS

The work in this thesis was carried out under the supervision

of Dr. B.J. Cory, B.Sc.(Eng.), D.Sc.,A.C.G.I., C.Eng., F.I..E.,

Reader in Electrical Engineering, Imperial College of Science and

Technology, London. I wish to thank Dr. Cory for his helpful guidance,

constant encouragement and keen interest during the preparation and

completion of this project.

I am grateful to the University of Coimbra, Portugal and the

Instituto de Alta Cultura for the financial support which made this

work possible.

I would like to thank all my colleagues of the Power System

Section, particularly Messrs. E. Horne, G. GonzElez, A. Ranjbar,

P. Ong and S. Molina who contributed directly cr indirectly to this

work.

b'inally I would like to thank the Electrical Engineering

Department of the Imperial College of Science and Technology for

the opportunity given to lecture in the Digital Protection of Power

Systems, Post Experience Course in 1975 and 1976.

 5

TABLE OF CONTENTS

Page
Title 1

Abstract 2

Acknowledgments 4

Table of Contents 5
List of Abbreviations and Symbols 8

CHAFTER I : INTRCDUCTION

1.] The use of comruters in poer systems 10

1.2 Substation switching

15
1.3 Contents of this thesis 16

CHAPTEil II : HARD4ARE CONFIGURATION

2.1 General' features of the system

19
2.2 Substation model 21
2.3 Data acquisition interface
29
2.4 Data acquisition processor

2.5 FIFO link

34
2.6 Control and protection processor
36
2.7 Control interface
37
2.E Conclusions Ao

CHAPTER III : NETWORK REPRESENTATION

3.1 Introduction
41.
3.2 Substation matrix
42,
3.3 Path finding algorithm
4(3
3.4 Final comments 5Z
 6

CHAPTER IV : INTERLOCKING AND SEOJENCE SWITCHING

4.1 Interlocking

4.1.1 Introduction

4.1.2 Survey of existing schemes 55

4.1.3 Proposed method 58
4.1.3.1 Isolator operation 58
4.1.3.7 Circuit—breaker operation 59
4.1.3.3 Isolator and circuit—breaker switching 62

4.1.3.4 z-lintenance 65
4.1.3.E Transformer paralleling 68
4.1.4 Conclusions 69
4.? sequence switching ,

4.2.1 Introduction 71
4.2.2 General method 72
4.2.3 Application of the method to several types 81
of substations
4.?.4 Conclusions 85

CflAPT,M V : PAULT CLEARANCE

5.1 Introduction 88

5.2 Opening of circuit—breakers 89
5.3 Correct o-neration of primary protection 94

5.4 Failure of primary protection 97

5.5 Fault clearances subroutines in

5.6 Final comments 105

CWJTER VI : CONCLUSION

6.1 Use of digital computer for switching purposes 106

 7

6.2 Noise and interference 106

6.3 General conclusions 107

6.4 Suggestions for future work 309

6.5 Original contributions 110

Appendix 1 Substation model control hardware

1. Substation model

2. Switch status interface

3. Control interface

4. Power supplies for interface

Appendix 2 FIFO link

1. Function of the device

147
2.rode of operation
148
3. Programming 155

References 183
 8

LIST OF ABBREVIATIONS AND SYMBOLS

The most commonly used symbols and abbreviations are given

below . Other symbols used in the text are explained when they

first occur .

CEGB Central Electrical Generating Board , U.K.

CIGRE Conference Internacional des Grands Reseaux Electrics

a haute tension

DAP Data acquisition processor

CPP Control and protection processor

DB Data base

FIFO First-in first-out store

CPU Central processing unit

I/O Input-output

DMA Direct memory access

ADC Analogue to digital converter

ASCII USA standard code for information interchange

API Automatic priority interrupt

VDU Video display unit

BCD Binary coded decimal

OR Output ready

IR Input ready

PD Pulse dump

PL Pulse load

DCHGR Data channel grant

DCHENA Data channel enable

DCHRQ Data channel request

 9

SINGCYIN, Single cycle request

OFLO Overflow

CAF Clear all flags

BL Block lenght

SM Substation matrix

A)(B Circuit-breaker between nodes A and B

A /B Isolator between nodes A and B

Closed circuit-breaker
4--
Open circuit-breaker
-00-
Closed isolator
-4--
Open isolator
-e-
 CHAPTER I

INTRODUCTION

1.1 The use of digital computers in power systems

Modern society uses increasing amounts of energy and in parti-

cular electric energy because of its flexibility and cleanliness.

Consumers of eleCtricity want a low-cost and reliable supply.

The early electricity supply systems were of small size and

complexity, so were controlled manually . Functions where time of

response was important, such as protective relaying, generator

voltage regulation and speed regulation, were automated using ana-

logue equipment . As networks became larger and more complicated

the task of operating the system under security and economic

constraints becomes more difficult . A huge amount of data related

to the power system states is necessary to obtain peak performance,

as necessary in such a costly investment • The decreasing computational

costs of digital computers with an ever increasing processing power

and reliability made possible the wide use of computers in power

systems . Digital computers can process data , store it and communi-

cate with the outside world . They can perform analogue equipment

functions plus a large range of capabilities for which analogue

equipment cannot be used-. Their programmability means flexibility

when modifications are necessary . Digital computers are now available

in a range which extends from huge data processing machines to tiny

one chip microprocessors .

At first , computers were used for off-line operating studies(1)

 11

such as load flows , fault level analysis , transient stability ,

besides being applied to accounting and financial operations .

From large-scale network planning and contingency evaluation , the

(1,2) .
digital computer extended its use to economic dispatch y data

(3-11),
logging and display state estimation , alarm analysis (12,13)
(11)
generation control control of circuit-breaker and other
(10,14,15) (16-22)
switching operations . Now even primary and back-
1
-up relaying is being considered.

The operation of power systems aims at suppling power econo-

mically ,with reliability and with minimum damaE-e to the envircno7ent ,

(26).
this being a problem of constrained optimisation Although

computers and other control equipment have a relevant role in

achieving that optimisation,the human cperatLr is essential ,because

a totally automatic operation would require to forecast all possible

contingencies which is impracticable .

An electric power system is a physically distributed system ,

interconnected with other systems . For this type of structure the

27,28)
control system must be hierarchical (26'27'28 with distributed

sensors and actuators . Totally centralized control must be excluded,

because the burden on the central system would be too heavy , with

large c=unication requirements .

The different control levels are define: according to the

(A))
er system structura substtion ,network area ,network
power

board . The lower '.evels extract data from the network and perform

local control and controls from upper levels . For local control

it may be necessary for some extra data to be sent from the upper
 1Z

level , in particular information relative to the limits of the

zone under control .

At substation level there are functions whose reliability and

timing are critical . These requirements dictate that control for

those functions must be local . In particular the" protectionfunctions

have been implemented up to now by special purpose analwi-ue equipment .

For economy and flexibility reascnsl it is envisaged that future

compute'r controlled systems will supervise most substations

(29).
functions Since the data requirements for logging , control and

protection overlap , there are economic advantages of having a common

(30,31,32).
data base for all the applications This integrated approach

contrasts with the dedicated approach in which processors are used

for each specific application with limited communication between them .

Table 1 (24) presents a comparison of the advantages and disadvantages

of both systems . To combine the advantages of both systems Cory and

others (24) propose dedicated processors for protection functions plus

a separate integrated computer system with appropriate redundancy .

Complete redundancy can be used , which allows modifications or repair

in one of the systems , without degrading the total system performance .

An alternative is to use overlapping of integrated systems controlling

adjacent zones . Data from and control to any point of the network

would be related to at least two systems . The integrated system will

check the performance of the dedicated system taking over in case

of its failure .
In the studies in this thesis , an integrated computer contrclic:

system is assumed . The system block diagram is shown in Fig. 1.1 .

A processor is uses. to control the collection of ata and validate

(31 . Th-. data base is
a data base common tc all the applications

situated in the core of a separate processor used for control and protecticn.

Dedicated
I Reliability 1. Smaller size gives greater
hardware reliability per module.
2. Failure limited to one application
Data 1. Limited data validation
Validation possible.,
• 2. Central data base available
Cost 1. Interface costs high for a
multiplicity of applications.
Speed 1. High processing speeds
possible.
Flexibility 1. Each new application requires
a separate computer system
Maintenance 1. Only one function at a time
need be taken out of service.
Software 1. Software is specific to each
processor and is therefore
modular and simpler.
2. Any intercommunications at
high speed between dedicated
mac:lines v.::1 be difficult.
3. On-line .development
ir-.7ractic:-.1.
Comput,:r 1. Total configuration could be
complex where intercommuni-
cation is required.
Man/machine I. Difficult to make very
interface effective for continuous
communication.
TABLE 1 Comparison of dedicated and integrated systems
13
Integrated
I. Software complexity gives mere
errors
2. Major hardware/software
failure could affect all
* applications, hence redundancy
must be adequate.
I. More data available in common
data base to detect hardware'
software faults i.e. system is
more tolerant of failures.
for onward transmission of
data.
1. Shared facilities make for
more economic applications.
2. Software costs may be higher
for a more complex system.
1. Careful system design
necessary to ensure adequate
speed of operation.
1. System is radial in concept
and easily modified for
additions or deletions of
plant.
2. Common data base provides
access to data for new
application.
I. Adequate redundancy essential
since all applications are
affected by taking out one
system.
2. Larger system can support
more comprehensive
monitoring and diagnostics.
I. Software, other than for the
applications programs, is
complex.
2. Communication between programs
associated with items of plant
is achieved via the common data.
3. On-line development possible.
1. Basically implemented on a
radial principle with
computer hardware at centre.
I. All the information required
would be concentrated in
. common data base. Only one
system requires accessing.
 SUBSTATION EQUIPMENT

Analog inputs Digital inputs (switch positions)

V
DATA ACQUISITION
. PROCESSOR ( DA P ) '

IFl I Fo

DATA BASE ( D B )

V
CONTROL & PROTECTION
PROCESSOR (CPP)

Circuit breaker Other control

and isolator control outputs

Fig 1.1 System block diagram

 IS

1.2 Substation switching

This tresis deals with the control of switching operations

as one of the functions of the substation control and protection

processor .

As power systems networks increaLe in complexity,decision::

have to be taken quickly and safely . A digital computer is well

suited for this kind of problem,because of the logic nature of

switching constraints . The development or the storage of pre-

-planned sequences cf switching operations do not pose any special

problems either . In addition,computers offer higher flexibility

to cope with changing rc.quiress than dedicated hard-wi red

circuits .

The desirability of a switching operation is decided by

predicting the effects of that operation . In cases where speed

is important ,such as reswitching after a fault , it is necessary

toE-.tore sequences of pre-planr,_:d cperat:ons for the different

contingencies . When time requirements are not critical . the

sequences can be developed on-line . To prepare sequences for all

likely c a es would require a large computer memory to store all

the sequences . and much off-line computer study . Here novel

methods are proposed for switching decisions to be taken on-line

with modest computer size and core requirements .

 16

1.3 Contents of this thesis

This thesis deals with the use of digital computers to control

switching operations in high voltage substations .

Chapter II describes the hardware configuration , constructed

to test the switching strategies . model of a mesh substtl - n

built and interfaced with adjacent digital processors (See Fig. 1.1).

Data from the substation model is fed to the Data Acquisition Processor

(11:".P) . The data consists of analogue quantities representing voltages

and currents and digital, values related to the switch positions .

This processor controls the data collection and carries out data

validation , checking the consistency of the redundant collected

data . The validated data is sent to an intermediate First—In ,

First—Out (FIFO) store which has its output interfaced with the

Control and Protection Processor (CPP) . This interface is designed

to carry out a fast transfer in a Direct gemory Access (D:-IA) mode

to the core cf the CPP . The CPP controls the subtation modl thro'17h

a suitable interface which decodes the processor instruction: .

Chapter 111 covers the area of network representation .

process for the representation of the state of the network using

information internal and external to the network , is formulated .

The information relevant to switching operations is deposited in a

single matrix , the Substation gatrix (Sg). A method described

to extract information about the interconnections in the network .

Chapter TV deals with interlocking Lald sequence switching .

A survey of existing interlocking schemes is made . A method is

proposed which predicts the effects of a switch operation to

 17

evaluate the desirability of that operation . An extension of con-

-
ventional switching constraints is proposed and the interlocl'inL

scheme is extended to the different types of switches . Tests were

made on-line to simulate several conditions and the results reported .

The se::uence Twitching prob:371 is for7.1117ted rp:'ro:ch

is presented . The applicability of the method is shown for the

mesh type substation and for other common types of substation .

Again tests were carried out on-line , to simulate the tra nsition

from one substation configuration to another , and the results

presented .

Ch,pter V describes substation fault clearance controlled by

digital computer and an extensive presentation of the possibilities

of fault clearance is made . Correct operation of primary protection ,

failure of ,primary protection through simulation of stuck circuit

breaker condition and reswitching reouences were tested .

Chapter VT ;resents the conclusions -nd sur-i7estions for futlire

work .

Appendices 1 and 2 describe in detail the hardware work done

by the author . Appendix 1 deals with the substation model , its

interface with the Control and Protection Processor and the switch

status interface with the Data Acquisition Processor . Appendix 2

describes the First-In First-Cut intermediate store which the

two processors .

The contributions offered by this thesis are the following :

i. the construction of a substation model with suitable interfaces

which enabled the simulation and testing of the switching strategies .

 18

The construction of a First—In First—Cut store and associated circuitry

enabling a quick link between the two processors ( Chapter 11 ,

Appendices 1 and 2 ) .

ii. a compact form of network representation is proposed which includes

all the relevant information for switching . ( Chapter 111

•
iii. development and testing of a comprehensive interlocking scheme

which takes an extended range of switching constraints . ( Chapter IV )

iv. presentation of interlocking constraint messages to give the

operator a clear picture of the system using the path—fincing

algorithm . (Chapters III and IV )

v. a sequence switching method is presented and tested to proceed

from one network configuration to another in an optimal manner .

( Chapter IV )

vi, on—line testing of fault—clearance programs with back—up simulation

and reswitching facilities . ( Chapter V )

 CHAPTER II

HARDWARE CONFIGURATIGIT

19

2.1 General features of the system

A substation model interfaced with adjacent processors was

(10
built to test on—line switching algorithms , line protection

data validation (34), and transformer protection(35)

A mesh substation was chosen for modelling because of its wide-

spread use by C.E.G.B. in their 400kV grid . The mesh layout is shown

in Fig. 2.1 The advantages of this arrangment are :—

i)only four circuit—breakers are required to control eight or more

feeders

ii) the maintenance of any mesh circuit—breaker does not produce loss

of supply to any circuit

iii) a fault on the central busbar causes the loss of only one feeder

iv) a fault on a mesh circuit—breaker causes the loss of a maximum of

two feeders

These advantages are gained at the expense of extra complexity in control

and protection making this layout a good application for digital devices.
The system block- diagram is given in Fig. 1.1 . Data from

the substation model is fed , through a suitable interface , to

the iJata Acquisition Processor (DAP) . The data consists of analogue

quantities of voltages and currents and digital values related to

switch positions .

The DAP controls the collection of data through the interface

(33,36) and validates it by checking the consistency of the redundant

collected data . Bad or missing data can be detected and corrected(34)which

would otherwise cause misoperation or deterioration of the scheme .

'the Data Base (DB) is a data store where the data relevant for

the protection ,:nd control of the suLstation is 'r_< r1, . lt receive:-

data from the 6AP and s,tpplies the data to the Control and Protection

Processor (CPP) . Separate processors were used for data acquisition

and control because the burden would be too heavy for a single computer,

especially in the development stages .

 20
The CPP inspects the validated data to detect abnormal situations

such as a•fault , issues the appropriate instructions and controls

the substation switching configuration . The CPP instructions cause

•
the operation of the circuit—breakers or isolators of the substation .

With the availability of cheap microprocessors the use of

separate processors for the different protection Tin-poses and

swi tchir.g control becomes an economic pcssibility . The multiprocessor

scheme ,communicating with the same DB - has the advantage of speed

over the single processor which must otherwise perform the different

tasks in a serial mode . In this experimental scheme only one CPP

is used so the different tasks were tested separately . The ]CVA

1210 was used as DAP i:nd the PDP 15 was the CPP .

The substation simulated is a mesh substation as in Fig. 2.1.

For control purposes the substation is divided into four equal corners

which allows the burden for data acquisition and control to be spread

among four separate computer systems . The analogue data collected was

only from one corner but digital data came from the complete substation.

Thus it was advantageous for the DAP and CPP to communicate with adjacent

corner processors . In a hierarchical computer controlled system there

would also be further communication with a central computer not

represented here . Communication with the central (area) computer is

simplified as the validated data is placed in the common data base .

It is intended that the central computer should coordinate the control

of the several zones issuing the appropriate commands . The relevant

data for area control is sent to the area computer .

As mentioned in section 1.1 an integrated computer system should

be used in conjunction with a dedicated system (either analogue or

digital) for reliability reasons. In case of failure of the main system

the other would cover for it. The reliability is increased by the

self—monitoring capabilities of computers which allow them to detect

. •••••■•••••••-•■•• •• r•-•-•••■••• • - • •---•■••.-.••• -•••••- ••••••• - -

 .21
hardware and software failures and take appropriate "`action . Sonic form

of duplication in the integrated system further increases the system

performance .A complete duplication of the system can be used in each

corner or there can be system overlapping of data bases and control

functions . In case of a failure of a corner system- , the adjacent corner

which is overlapping the failure would take over . The decisions would

be taken on a one out of two basis. If there is a failure in the data

acquisition of one of the systems , the inconsistencies are detected and

the output inhibited . The same happens when there is a failure in

one of the processors sensed by using a diagnosing routine .

Fig. 2.2 shows a more detailed block diad--am of the system ,

consisting of six main subsystems ; (i) the substation model ,

(ii) the data acquisition hardware , (iii) the DAP (iv) the

DAP-CPP intermediate FIFO store (v)the CPP and (vi) the control

hardware . The details of each will be considered in the next

sections . Only the corner with analogue transducers in Fig. 2.1 is

fully simulated and this supplies analogue data to the DAP •

2.2 Substation model

One corner of the substation has been chosen for modelling .

For symmetry reasons , principles applied to one corner can be easily

extended to the other corners. The simulated corner has three-phase and
neutral simulation in which circuit-breakers and isolators are

simulated by three (3-0

-phase contactors ' controlled by circuits

activated auxiliary contacts of miniature relays . Vol tare and

current transducers provide measurements of those quantities .

 SECONDARY 1
CIRCUIT

/ /
14 X 15 , 16 17 20 23 24
x
25
(one line simulation)

PRIMARY CIRCUIT
,( three phase simulation) •

Ol

4 8 11 12 13
0-M- x
1-
•/

Key

M Transducer
(Linear coupler)
-CD- Voltage transfOrmer 10
Fi9.2:1 Mesh substation primary and
secondary circuits.
 .23

r Substation-1i
model I

Mimic diagram

50 Hz Primary Secondary
power circuit circuit
supply

r _J
1
7D 14D
42AC

Synchron.r. Switch
Drivers clock S.B. H. circuits
positions
(PLL)

Data
Switches Acquisition
control logic MUX and ADS Hardware
data input -
Nova Interface

PDP-15 out- _J
put control T-
Interface
;
Data output
—►
I Nova FIFO (
Nova 1210
(PDP-15 inter - •
DAP
mediate store
PDP - 15
(CPP)

F19.22 System block diagram.

 24

These corner circuits are called the "primary circuit" . In the

three other corners of the substation the circuit—breakers and

isolators are represented by miniature relays without any ectriCal

connection between them or the primary circuit . This part of the

model called "secondary circuit" is used to simulate switch positions

and is•useful.to test programs involving more than one corner of

the substation such as fault clearance with back—up , interlocking

and sequence switching . A mimic diagram shows the substation layout

and gives indications of the state of the switches both in the primary

and in the secondary circuits .

2.2.1 Primary circuit modules

The primary circuit is divided into seven blocks (Fig. 2.1).

The connections between the blocks are made with heavy current cables

via heavy current plug sockets . The seven blocks are built in five

boxes fixed onto a vertical rack (See Appendix 1) and each box

contains a contactor unit with the control circuitry ,current and

voltage transducers . The front panels contain the current plugs

( Bulgin six way type ) , small monitoring sockets for checking

currents and voltages , and red and green lamps to indicate the

contactor status , "close" and "open" respectively . A push button

switch below each lamp is used for manual "close" or "open" operation .

A 30C mA fuse is provided to protect each contactor control

circuit .
 25

2.2.2 Contactor unit and control circuit

A three phase open type contactor ,Klockner Moeller Dil

CCA 41/59 , is used to simulate the circuit-breakers and iso]ators

in the primary circuit . It has two auxilary contacts , one normally

open (i•J/O) and one normally closed (N/C) rated at 50C V AC ,?C .

A microswitch is fitted on the top of each contactor which

changes state when the contactor is operated . The microswitch has

one r/o and one N/C contact which supply information ,in a duplicat:::

way , to the DAP .

The contactor control circuitry is shown in Fig. 2.3 . The

relay state is controlled by the CPP through the control interface .

This is described in detail in Appendix 1 . When the relay is energited

the relay contacts move to the opposite position to that shown in

Fig. 2.3 causing current to flow in the contactor coil , through

the 3.9.C1 and 50C _C-1_ resistors . When the contactor has closed)

th r/c contact is replaced by the 5.1k.fl. resistor to ho]d on the

contactor . The 33i4F capacitor across the N/C contacts boosts the

coil current when the closing operation takes place to produce

a large initial current for a fast closing action and a much smaller

operating ,current to minimize the power requirements . The N/0 contact

bypasses the 3.9_c resistor reducing the wear on the relay contacts .

When the relay is de-energized the coil and the 5.1k.n. is shunted 7

causing the current in the coil to fall . The r/c contact opens

to break the current so that the relay contact is thus never used

for current breaking .



26

r
$ A Red
closed signal ion the mimic diagram
(MS)
r--
1

Front
panel

open L t-- micro switch

200V *
o

-3A Fuse

5001

5W
R1

- -1
-2 VI
I
IIL
I
I 1
(AR) V 1 1
I Green
I I
I I
I I C 1
_.1 I
Auxiliary
relay 11 I
Red I
L _,

On the front
panel

Fig.2.3 Contgctor control circuit

 .27

2.2.3 Current transducers

The current is measured using (38)

linear couplers which are

air—cored transformers . Linear couplers were used in preference

to iron—cored current transformers because they do not suffer from

saturation non—linearities . Also the decaying DC component with

long time constants will be attenuated in relation to the 50Hz

component because of the device differentiating action . However

for this same reason any harmonics and noise will be amplified

causing the output waveform also to be very noisy .

The output is nominally 6mV per lA at 50Hz in the primary

conductor .
It is to be noted that measurements used fcr this research were

only related to the state of the substation switches .

2.2.4 VoltaF:e transducers

The voltages are measured using miniature 240/6 V voltage

.transformers . The primary of each transformer is connected across

the line and the neutral .

As the voltages across the transformer secondaries are too

large for the data acquisition equipment , voltage dividers are

used across the secondaries to attenuate the measured values .

2.2.5 Secondary switches

The relays which simulate the isolators and circuit—breakers

in.-the secondary circuit are mounted in the same box.'The relays are Omen

12V , 430.n. and simulate the switch positions . Three of the four

pairs of contacts are used (Appendix 1). One pair is used for the

mimic diagram , another for the computer switch status and the third

for monitoring purposes using the sockets on the pane] front .

 .28

The relays are also controlled by the CPP through the control

interface (See section 2.7) .

2.2.6 Mimic diagram

Mounted above the model (See Appendix 1) , a mimic diagram

displays the substation layout . Each switch has an adjacent red

lamp which , when lit ,shows the adjacent switch is closed . The

circuit-breakers 5x8 and 4X16 have additional yellow lamps

which indicate the "stuck" breaker condition (See section 2.7) .

2.2.7 Power supplies

The primary circuits require a 2CCV DC unregulated and a

12V DC regulated power supplies . The secondary circuits use a

12V DC regulated supply for the relay coils and switch status

and al2V DC unregulated for the mimic diagram .

These supplies are described in Appendix 1 and are installed

the bottom of the model equipment .

In this thesis the following symbols are used in the text

to differentiate between circuit-breakers and isolators :

A X B circuit-breaker between buses A and B

A /B — isolator it II II II

2.3 Data acquisition hardware

2.3.1 General description

•

40) interfaced with the DAP,

The data acquisition hardware (39,

is shown by Fig.2.5 in a block diagram form .

Both analogue ( 64 inputs ) and digital ( 48 inputs ) data

 29
can be fed into the interface through a patch panel (See Appendix 2).

All the inputs terminate an lmm sockets . A computer controlled

sampling system synchronized to the supply , is used to sample

the analogue inputs which are multiplexed into three analogue to

digital converters (ADC) channels . Three ADCSare necessary to minimize

the overall conversion time and for security purposes. It is important

that the conversion time allows a data validation to be made in each

sampling period . If there is a failure in one channel the values from

the two other channels (phases) could be used to estimate the third

phase values . This feature has not yet been implemented but it is hoped

to do this at a later date to improve system reliability .

2.3.2 Digital inputs

An input facility of four 16 bit digital wcrds is available

on the interface . The least signicant bit of each word is transferred

to bit 15 upon input to any accumulator , and the most significant

to bit 0 . Reference should be made to Appendix 2 for greater

detail .

The inputs are standard positive TTL logic . The digital inputs have

no status or interrupt flag . Ih the patch panel the two lower

words have been allocated address 43 , and the two upper words 44 •

The transfer of one word to any accumulator is effected by the

following program instructions :

bottom word DIA (AC),43

second word DIB (AC),43

third word DIA (AC),44

top word DIB (AC),44

 • 2 flags

I/ 16 bits data bus

NOVA A I

1
addr. sam le
1210 bus bus bus bus bus !bps
dr1 dr:2 dr3 dr 5 dr. 7.1 , rec. clock pulses
addr. "11 :ki A

10 dec.
control %
bus 71 k 71A 71
contr.

oxj _loiu!uog.tsynb3DD/DQ
dec. adc. adc.
3 sera clock
ref

A mux.
sero.
16 16 16 16 16. 16
arrp
dr
x X X- x x //
4 16
digital inputs analgue inputs
 31

The accumulator (AC) can be any of the four 0,1,2,3 .

2.3.3 Analogue inputs

The interface provides'for 48 analogue inputs multiplexed in

sixteen groups of three . Inputs to the multiplexers in excess of

± 10V are clipped to that value . The input voltages should never

be allowed to exceed t 15V , otherwise damage will occur to the

multiplexers . Each of the ADC's is served by a sixteen way analogue

input multiplexer which may be operated either by program control or

incremented automatically by the"end of conversion"pulse . The three

ADC's operate within a range of It 10V to give 10 bit , two's

complement conversion . Resolution of the least significant bit is

19.53mV and conversion time is 25ps . The converter status is

indicated by common "busy" and "done" flags . The "busy" flag

is set by the computer issuing a "start of conversion" pulse and

when the conversion is complete , the "end of conversion" pulse

clears the "busy" flag and sets the "done" flag . For special

purposes a data "zero within tolerance" flag is available from

each converter . This is input with the converted data to bit 0

of the chosen accumulator .

2.3.4 Phase locked clock

The phase locked clock shown in Fig. 2.6 is used to synchronize

the data acquisition functions of the computer interface to a selected

frequence referency in the range 40-6C Hz . The phase detector

compares the relative phases of input reference and the feedback

signal to produce an error signal . The presence of an integrator

avoids any steady—state error . The integrated error signal is applied

 32

Input nf .
reference 4-
V. C.O. output
integrator

divider
by n

Fig.2.6 Phase locked clock

 33

to the voltage controlled oscillator (VCO) causing a change in the

frequency . The oscillator is nominally running at some integer

multiple of the input reference frequency . The feedback loop is

completed by a division network .

The oscillator output is to be used to communicate with the

computer , causing interrupts every pulse period and to command

the sample and hold circuits . Trough program control the enabling

of the clock output and the pulse repetion rate can be set to nil ,

2,4,6,8,12,16,24,32 pulses per cycle of the reference frequency .

the pulse rates are taken from a divider network whose input is

the VCO output .

2.3.5 Power supplies

This section is described in greater detail in Appendix 1 .

The interface and sample and hold circuits require six regulated

supplies as follows :

+ 5V ± 0.25V
+ 15V 1V

— 15V 1V
+ 12V 2- 1V

— 12V ± 1V

— 18V ± 1V

All these power supplies are overcurrent and overvoltage

protected .
2.4 Data Acquisition Processor (DAP)

A NOVA 121C minicomputer with 12K of core memory is used as

DAP . The NOVA main characteristics are :

Bit lengh --- 16 bits

Cycle time --- 1.28S

112 of accumulators --- 4

Besides being interfaced with the data acquisition equipment

and through the FIFO link with the PDP 15 , it is interfaced with

a teletype , fast paper tape punch (110 bytes/S) and a fast paper

tape reader (250 bytes/S) .

2.5 NOVA-PDP15 FIFO link

This section is described in detail in Appendix 2 . A fast

data transfer link between the two computers was built using a

First-In First-Cut (FIFO) memory . This has an independent read-

-write operations which allows the connection between the two computers

to run asynchronously .

Fig. 2.7 shows the block diagram of the FIFO link . Validated

data words are put in the NCVA I/O bus using appropriate output

instructions together with a timing pulse . As the two computers

are far apart line drivers and line receivers are used to steer

the data words along the connecting cable to provide noisehomunity .

For the same reasons twisted pair cables are used for all the

signals.

In order not to waste CPP processing time the data corresponding

to a sampling period is accumulated in the FIFO and then transferred
 35

A
NOVA I/O BUS

DATA NOVA CLOCK

DATO A

/ V LEVELS

LINE DRIVERS

100 WAY CABLE

\/
ILINE RECEIVERS
I

DATA NOVA CLOCK

LEVEL 5
FIFO STORE AND
CONTROL LOGIC
FOR SINGLE CYCLE
DATA CHANNEL D.M.A.

DATA CONTROL

PDP-15 I/O BUS

Fig.2.7 Block diagram of the transfer of data from the NOVA •

to the PDP-15.
 36

through a Direct Memory Access (DMA) to the PDP 15 core . This type

of transfer is very fast , being able to transfer 18 bit words at

1MHz rate and does not interfere with the Central Processing Unit

(CPU) . The CPU can continue processing except when it has to

communicate with the memory . In this case the DMA has priority

and the CPU waits until the transfer finihes .

The FIFO control unit keeps track of word count and address

count . The starting address is set through dual—in—line miniature

switches in one of the cards but the number of data words in

each sampling period and the number of samples relevant for the

application can be varied . To cope with these requirements the

device has the possibility of setting the number of words in each

sample up to 64 and the number of samples up to 99 . The maximum

size of the PDP 15 core occupied by the sampled and validated data

is 99)(64 in an allocated core area in the Data Base (DB) .

2.6 Control and Protection Processor (CPP)

The PDP 15 was used to perform as the CPP . It has 18 bit

word length ,24K of core memory with a cycle time of 8COnS , it

is equipped with hardware multiply—divide and automatic priority

interrupt , having only one accumulator . This lather feature makes

programming somewhat inefficient .

The associated peripherals include a magnetic tape system

consisting of two tape transports ,fast paper tape reader (30C bytes/S),

fast paper tape puncher (5C bytes/S) , a Tektronix storage display,

a line printer (300 lines/minute) ,XY plotter , 12 bit AD converter

and a teletype .
 37

2.7 Control interface

This equipment is described in detail in Appendix 1 but

Fig. 2.8 shows the block diagram of the PDP 15 control interface .

The control words are sent to a buffer register interfaced

with the PDP 15 I/O bus through the use of special I/O instruction .

This instruction causes the control word previously deposited in

the accumulator , to be transferred to the buffer register , whose

associated circuitry decodes the peripheral address (See Appendix 1) .

The control word is sent through line drivers and receivers

to the decoding circuits . Fig. 2.9 shows a simplified diagram of

these circuits . As mentioned previously , two switches enable the

possibility of simulating a "stuck" circuit-breaker . In addtion

to the switch address group of bits , other discrepancy bits are

used to disable normal operation and cause the proper yellow

lamp to lit . In a normal operation the 4-16 decoders are used

together with the I/O pulse to clock the bistable corresponding

to the address to be decoded . The bistable output will then turn

on the corresponding relay transistor driver causing the relay to

change its state and to operate its corresponding contactor .

2.8 Conclusions

A model of a mesh substation was built and interfaced with

a data acquisition processor and a control processor . A FIFO link

enables fast transfer of data between the two processors . The whole

system was tested with the switching algorithms described in the

 PDP 15 UO BUS '
38
address
data . and
control

Output register Device selection

10P4
V

Line drivers

Line receivers

IOP4
Timing
Open
Close

Discrepancy
and switch
decoders

Bistables

Relay drivers

Primary Secondary

••■■■■•■•••■■••■■•••■■■■■•■•••••■■•■■■1
■

FigvControl interface block diagram

 39

enable discrep. 'enable switch

-if (0) bit group
discrep. Ir close
-1 address open bit switch address
10 4, d- 1
H -I -V - II
10 9 8 7 6 5 4 3 2 1 0

2-4
'f V TT

4 -16 2 with
Group 1 Decoder discreps
if tit 5:0

• 6
D,.. normal

Clock
Timing

4 -16 16
Decoder normal
Group 2
•if bit 6:0

Enable control if bit 8 z-

Fig.2.9 P D P-15 output control interface.

 40
next chapters . The system operated satisfactorily after some noise and
A

timing problems were eliminated . In the substation model the control

logic circuitry is near the contactors . When these operate the electrical

noise generated can produce random switching . All the wiring which goes

from the contactor boxes to the control circuitry had to be decoupled

or "tied" through low impedances to the supply or the earth . In a real

environment additional precautions must be taken to avoid the effects

of interference , mainly due to switching , lightning and insulation

breakdown . To avoid destruction by transients of the electronic

equipment , this should be isolated from the high voltage using optical

isolators . The use of varistors and spark gaps is also necessary to

(46)
attenuate the transient spikes . Careful shielding is needed to

minimize interference in the signal cables which could cause maloperation .

A single radial earth was used , but when large distances are involved

separate earthing with optical isolation between subsystems is advisable .

(4s)
Experience in operating digital devices in substation environment is

now being obtained and all indications are that reliable operation

is possible provided proper attention is paid to the above points .

The most unreliable feature of the system were the electro-

mechanical components of the computer controlled miniaturo relays.

Their contacts needed frequent cleaning .

With the appearance of cheap and powerful microprocessors

on the market it is now possible to use a dedicated processor for

each function accessing the same data base . The system cannot only

operate at higher speed but also with considerably simpler software.

The latest microprocessors have the same range of speeds as

minicomputers , being in fact minicomputers without control panel and

some interface facilities thus making them much cheaper . In applications

where there is no need for progam development and the same job is

always done the microprocessor is the obvious choice .

 41

CHAPTER 3

NETWORK REPRESENTATION

3.1 Introduction

Information abut the power system network in particular

its structure', is nbcessary to control switching operations . Aprocess

for representation of the state of the network is formulated in

this chapter based on information both internal and external to

the network .

The information must be as accurate as possible and the data

should have enough redundancy to allow it to be validated , using

recognised techniques (34'47). Loss of data or errors due to

transducer,i and associated equipment malfunction can be solved

using consistency checks of the redundant data . Errors in the

communications subsystem due to external noise can be eliminated

by the use of codes with error detection and correction

capabilities (45)

If lack of data prevents a solution being obtained "the worst

case conditions must be assumed . These cases should be avoided

whenever possible because the "worst case condition" depends upon

the constraints imposed .If for example , in earth switching

or isolator operation it is assumed that all unknown feeders are

connected to generators , then to avoid loss of supply , the absence

of generator connections to those feeders must be established .

Section 3.2 describes how the information relevant for switching

operations is deposited into a single matrix , called the "Substation

Matrix" (Std) .
 To extract and analyse information about the interconnections

between parts of the system , 4 path finding algorithm was developed ,

described in section 3.3 . This algorithm scans the substation

matrix and is widely used in Chapter 4 for interlocking and sequence

switching purposes .

3.2 Substation Matrix (SM)

In the formulation required for switching , busbars , lines ,

transformers and other connecting items of equipment are considered

as nodes . These components are used either to carry power or to

control the voltage .

Operational components , which can change the topology of

the network , such as circuit-breakers ,load switches and isolators

are considered as branches .

All live terminals of loads are considered as the "sink" nodes

and the live terminal of generators are considered as "source"

nodes . The sink and source nodes can be commoned into one sink

node and one source node . The source node is denoted by node 1

and the sink node by node n+2 ,thus between them there are n nodes ,

corresponding to the network nodes (48)

If the generators and the loads are external to the network

being considered , the information concerning the connections of

the network limiting nodes can be given by an adjacent area

computer (47)

The information about the substation which is relevant for

switching purposes is deposited in SM . To identify the kind of

switches between two nodes i and and their state the elements
 13

SMij l<i<n+2 , 1cjoi+2 , are formed by the following rules :

Type of switch Switch open Switch closed

Circuit—breaker SM j=00 SMirl°

Load switch 00 10

Isolator Type 1 01 11

Isolator Type 2 02 12

Otherwise 03

Circuit—breakers and load switches are given the same code

because for operational switching they have the same capabilities .

The isolators are capable of breaking magnetising currents

and leakage currents . An isolator is type 1 if it has an adjacent

circuit—breaker and type 2 otherwise . For example in Fig. 3.1

the isolator between nodes 4 and 5 is type 1 and the isolator

between nodes 3 and 4 is type 2 .

Each switch has an operation code (See Appendix 1) which is

issued by the control processor when the need for an operation

arises . These hardware switch operation codes can be included in

SM . In this case the above code would apply to the first two digits

of SMii , the other digits being the operation coda .

The external connections between the source and nodes are

represented by a "Source connection vector" . The ith component

is 14 if there is a connection external to the network between the

source node and node i , otherwise it is 04 . In the same way in

the "Sink connection vector" the ith element is 1.2 if there is

a connection external to the network between the sink node and node i
 221

8 21

14 NJ 16" 16
x 2 0 I
/ 23
2
2 3'

2 3 8 11,
/
15 12 XL3
/

Cz/ -6 c a tr z 6/
(3

'7Y 101

Fig. 3.1 Mesh substation

Fig. 3.2 Substation Matrix

 45

(but not with the source'node) , otherwise it is L5. . These vectors

occupy the first row and the last column , respectively of SM

(See Fig. 3.2) .

To describe the earthed part of the network an "Earth

connection vector" is formed . The ith component is 16 if the node

•
is earthed and 06 otherwise . The connections can be made through

permanent earth switches or temporary earth connections . Nodes

which are not directly connected to earth are also given the code

06 . The "Earth connection vector" is placed in the last row of SM .

The diagonal elements SMii are used to identify the type

of nodes in the following way :

20 if node i is a portion of busbar

21 line
=
22 ,, transformer

23 otherwise

The elements SMij (iij I< i<n+2 , 1<j <n+2) can be

subdivided into two zones separated by the diagonal elements .

In the zone above the diagonal (1(j) can be stored another

network configuration which is useful when it is desired to go

from the present configuration to another whore the switch states

are different.

The first column of SM can be used for storing the earth

connections in the final configuration .

Fig. 3.1 represents the layout of a mesh substation widely

used by C.E.G.B. in the 40CkV grid . A model of that substation

 46

was built (See Chapter 2) having the facilities of receiving

switching orders from the control computer and sending switch

status data to its core . As the switch states change SMij

change accordingly .

Fig. 3.4 represents an example of SM for initial and final

configurations of Fig. 3.3 .

It is possible that in the future , power systems networks

will be controlled by an integrated hierarchy of computers (26,27)

Local computers will communicate with adjacent local computers

and with the central area computer but it is important to minimize

the communication requirements . For this purpose ) the network

information can be synthesized . For the outside network it is

necessary to know how the limiting nodes are connected among

themselves and which type of connection they possess (eg. source

sink but not source earth) . In the case of the mesh substation

in F1g. 3.1 there are 8 limiting nodes,so that two 8 element

vectors are necessary .

The "Feeder internal connection vector" (47) describes how

th
the feeders are connected . The i element is equal to the

"first" (according to a chosen order) of the limiting

th
nodes to which the i limiting node is connected . An arbitrary

order was chosen as 2 , 13 , 14 25 , 7 , 10 , 19 , 22 .

Fig. 3.3 shows that vector for the initial configuration of Fig. 3.3 .
The "Feeder state vector" describes the feeder state . The

earth connections could be either external to the network or ,

through a connection to an earthed vector in the network ,the

 KEY. )( Closed circuit—breaker
, Closed isolator
47

Open circuit-
-breaker 22
_0_ Open
isolator
21

16

INITIAL
CONFIGURATION

(71

6
f I :):,! VI CT DR

2 for initial
13 configuration 7 . 10
25
14
14
14 19 221
25 )1(
IS 21

\
PAG // 17 2 1 /
3 /
FINAL

CONFIGURATION

2 3 /+
x-"
6p
7

Fig. 3.3 Examples of initial and final configurations . The feeder

limiting nodes 2,13,14,25 are considered connected to source .
The outfeeder limiting nodes 7,10,19,22 are considered to be
connected to sink .


48

:JJE::- T0110N MATRIX

= _
7 : 14 4 4 4 4 4 4 4 4 4 4 14 14 1 4 4 4 4 4 4 4 4 4 11 4

A 20 10 : 7: 3 :7: - - ,
-7.: .3 3 .3 3 3: .3 ,
3 3, ,
3 .,
3 ,
.3. .3, • • 3
3, 3 3

- - - •-• •-• .7. 3 3: 3 3: 3

3 3 :*

A 3 1 20 12 ? ? 7 :

• :7: :3 1 ;f :20 11 10 :7: .3 :3 :3 3 3 3 :3 3 3 3 3 3

A :3 .3 :3 11 22 10
7 _

_
6. 3: 3 3 7: i1 7: 3 3: 15

6. :3 3 :7: 10 .3 20 11 :3 13 :3 3 3 :3 3 3 :3 .3 3 3: 3 3 :3

A 3 3 11 *2_2 1 CI

4 :3 3 .3: .7: it :3 10 21 - 3 3_ 3 3 :3 15

3 3 20 11 3: 3 3 3_ _ _ 3 :3 .3 10

F. 3 3: 3:: 3 3 3 3: 3 3 1 21 10 3: 3: 3 33 -3 3: 3 3 3 .3 5

A 3: 3 :3 3 :3 3 3 3: :7: :3 020 .7: :3 3 3 3 3 3 :3 3 3 .3 3 5

4 :3 3 0 3: :3: 3: 3 .3 3: 3 3 3. $

6 3: 3: :3 3 :3 -3 3: 7: 3: 3: 3 10 2j •-•
• • •-3 -3 7 ,

3 3 10 :3 :3_ :3 3: .3 33331120123333335:
• 35

• .3 3: 3 :3: 3 3 :3 : 7 33122011310 3 3.3 3

A :3: 3 3 3 3 :3 3 3 3 3 :3 3 .3 :3 3 11 22 10 -3: 3 3 3 3 3 5

6. 7: 3 :3 .3 3 .3 :3 .3 :3 :3 3 3 3 3 :3 3 10 21 3.. 3 0 :3 3 .3 15

6. 7: :7: :7: 3: 3: 7: 3 :3 3: :3 .3 3 .3 3 3 0 3 3 20 11 3 12 3 .3 5

A 3 3 :3 3 - ---3:- * 3 3 3: 3 3 3 3 3 3 11 32 10. 31 -3j 5

3 :3 .3 3 3 :3 3 3 3: 3 :3 3: 3 .3 it .3 1.0 21 ?

.3 3 :3 3: .3 3: 3 0 3 3 3 3 3 .3 .3: .3 12 3 3 20 11

• 3 3 3 3 7: ? .3 .3 , 3 .3 3 3 :3: 11 21 10 5

3 .3: 3 * 3: 3 10 20

-1: A A 4 4. 4 4 6 4 6. 6. 6 67-7;

Fig. 3.4 Substation Matrix for the configurations shown in Fig. 3.3
 13

source and sink connections considered are external . The following

rule is used to form that vector :

14 node i connected to a source

15 n " " sink

th (but not to a source)
element .
16 earthed directly or indirectly

06 otherwise (eg. open circuit)

3.3 Path finding algorithm

The path finding algorithm arises from the need.to know for

switching purposes if there is any electrical path between two

points of a network . Not only is it necessary to determine if

two nodes are connected , but also the possible different paths

must be found when more than one path exists .

Figs. 3.5 and 3.6 show the flowchart used for path finding .

The philosophy of the program is to start with initial node II

and then , by looking for adjacent nodes in SM proceed through the

network avoiding any repetion of a node using the same path until

final node JJ is reached .

In the flowchart "test node 1" and "test node 2" are the

names given to the nodes,when checking if they are directly connected .

If they are connected through a closed switch the corresponding

element in .SM will be greater or equal than 10 . When testing

final configurations the search is made in the upper part (i Gj)

of SM unless the sink or the source are involved . The same applies
Fig. 3.5 Flowchart for TA RTD 50
path—finding V
Set N° d1 -1-,M-1,5 A yew
cv-,!,10,..44 ro
set
set, cad,

sa 1i x n J,
c
Ittr.-tife. 2

i (Ai b.) Icirft.1 ;j

hockib ;tn. -11 1v ivt<==rt
yl

St ,i xt -tncv.i to.„/.2‘.
vAct:. 2

V 5,4 ef-c cvnt4,

on/MCA:I

Y y
I +11) c(tAn4 ot.
Wks

V
4I^J GC..4 ;11±7c
1nS 1\1 rr;..t CY
v i ks
(1)
 51

Fig. 3.6 Flowchart for path—finding (continuation)

 52

for the initial configuration the search being made in the lower

part of SM (i> j) . Fig 3.7 shows an example of the path finding

routine to find the paths be•twoen the nodes 2 and 1.2 . The zeroes

correspond to empty elements in the array .

3.4 Final comments

Methods have been described to extract information from

power systems networks to control switching operations. Although

used here in a substation , these methods can be applied to

any network .

Intrinsic information about the network , eg. the layout

needs only to be read once . Information about the switch status

is scanned and fed into the control processor (Chapter 2 and

Appendix 2) to update the network representation . Some information

external to the substation may be necessary , which can be fed

from adjacent network computers .

SM contains all the information which is important for

switching operations . The "Feeder state vector " and the "Feeder

internal connection vector" describe in a synthetic way the

network connections to outside and those can be used for

communication to other computers .

A path finding method proposed scans the network information

to give a detailed view of the interconnections of the network .

The computer requirements are discussed in Chapter 4,where

the above methods are used for interlocking and sequence switching

purposes •


KEY 53
closed circuit—breaker
—4_ closed isolator
open circuit—breaker

open isolator
—e—

19 22

18

2e_a_ 16 7 0 23 2' 25

41 12 w 13,----

IV

Path 1 4 S 11 1 I'D 0 0 0 0 0 I -) 11

Path 2. .7: 1 !A 17 iF 2: :71 20 11 12 1? ::1 I:1

Path 1 d 11 11: ■-■

Fig: 3.7 — Paths between nodes 2 and-13 for the above configuration
 51}

CHAPTER IV

INTERLOCKING AND SEQUENCE SWITCHING

4.1 Interlocking
4.1.1 Introduction

Interlocking provides a means of safe switching . Both

operational and maintenance procedures require switch operations .

Care must be taken to avoid damage to equipment hazards to

maintenance staff and unnecessary loss of supply to comsumers .

Configuration analysis techniques described in Chapter III

are used to predict the effects of a switch operation . If any

undesirable effects arise from the switch operation it should not

be carried out . A good interlocking scheme should prevent all

undesirable operations and allow possible ones .

In section 4.1.2 a survey is made of existing schemes and

their characteristics are highlighted . A comprehensive interlocking

scheme is presented in section 4.1.3 covering the operation of

circuit—breakers ,load switches , isolators , earth switches and

the paralleling of transformers against a range of constraints .

The method was tested on—line using the model described in

Chapter II and the computer test results and requirements are

presented in sections 4.1.3 and 4.1.4 respectively .

The proposed method can be used for automatic operation of

a substationoras a result an operator request .In the latter case

the operator receives a message which indicates if the operation can or

cannot be carried out .

 55
4.1.2 Survey of existing schemes

As already stated an interlocking scheme should prevent any

operation which violates switching constraints , but otherwise

allowing operations to be as flexible as possible .

(49)
Early schemes were simple , dealing with small parts of the

network to minimize data requirements . Interlocking was provided for

isolator and earth switch operation and for the access doors to places

normally containing live equipment . Padlocks, mechanical arrangements

envolving camshafts and electromagnetic bolts are normally used to

avoid wrong operations or dangerous situations. Worst-case assumptions

of feeders energized were made about their state for isolator and

earth-switch operation . These schemes were comprehensive enough

in relation to the operation of those switches , but some possible

and desirable operations could not be carried out and those

assumptions about the feeders state can produce loss of supply to

some loads .

In many schemes isolators are interlocked to adjacent

circuit-breakers and only if they are open can the isolators be

allowed to operate whatever the state of the other switches and

feeders . Although isolators cannot make unsafe operations , some

flexibility is lost . In fact , to carry out some desirable

operations , interlocking must be defeated and Hutchinson (49)

points to the inconveniences of such schemes . The defeating of

the interlocks induces in the operator a sense of disregard for

the interlocking .Interlocking should only be defeated in case of

component failure .

To overcome these problems Hutchinson proposed an interlocking

scheme which uses two secondary check circuits containing auxiliary

switches of isolators and circuit-breakers . Cne of this circuits

dual of the network circuit with all impedances and E.M.F.s made
 56

,that
zero ,is used to determinerthere_is a short-circuit path across

an isolator's auxiliary switch . A short-circuit in the dual circuit

is equivalent to an open-circuit in the direct equivalent and means

that the isolator is not operating on load . The other circuit is

an equivalont .circuit of the network , with impedances represented .

This circuit is used to check if there is a short-circuit path

across the isolator's auxiliary switch contacts . A low impedance

shunt-path allows the operation of an isolator , even on load .

This method has several drawbacks . Only planar circuits

have the corresponding dual and though the method is good for

isolators it is not applicable to circuit-breakers and earth-

-switches .
(50)
Cory proposed an interlocking scheme using mathematical

logic together with electronic logic circuits . Auxiliary switches

feed the inputs of logic circuits which implement the constraints

relative to a switch operation . The combinational logic produced

an output which according to its value enabled or disabled a

switch operation . This scheme has a broader scope since it can

be used to implement a wide range of operating constraints . These

constraints must be written as logical statements and then implemented

using logic circuitry . Besides using switch states as inputs

other variables can be used , such as currents or voltages measured

above or below a certain reference level .

If a modification is made in the network theconstraints have

to be reformulated and circuits changed which could be time consuming

and costly.
 57

(51)
In order to provide flexibility ) Hope and Cory proposed

the use of digital computers .

The constraints concerned with the operation of each switch,

expressed as combinational expressions of the inputs , are fed

into an off—line digital computer.. The computer processes the

information to produce a minimized logic controller . This logic

controller can then be used to control , through an on—line computer ,

the switching operations . If the network is modified a new logic

controller must be produced off—line . This method requires the

enumeration of all ope/uting constraints and a forecast of all

possible contingencies . In extensive networks this involves much

off—line work and size of the logic controller also grows quickly

with the system size .

(52)
A simpler but less complete approach was used by Row

The constraints for isolator operation were developed again under

the form of combinational logic as a function of the switch states .

The on—line computer was then programmed with a set of combinational

logic constraints .

Instead of using off—line study to process all possible contingencies

and obtain a computer programmed logic controller , the computer ,

using available network information , can'analyse the effect of

a switch operation and decide on the desirability of such an

(53)
operation . The method to be presented here employs this principle,

making use of constraints in a broader sense . It covers the operations

of the different types of switches and can be used on—line for

operational or maintenance purposes .

 58
•

4.1.3 Proposed method

The proposed method is designed to be used on-line either

automatically or in conjunction with the operator .

In sections 4.1.3.1 through 4.1.3.5 different aspects of

interlocking are considered and results of on-line tests presented .

Any particular constraints such as paralleling of two given feeders ,

can be added after the checks indicated are performed . Validated

data (45)about the network structure and state is assumed . As

mentioned previously in Chapter III , missing data leads to the

assumption of "worst-case" condition which prevenls the full

achievement of the interlocking process . In section 4.1.3.6 the

computer requirements are outlined .

4.1.3.1 Isolator operation

Because of its mechanical design , isolators cannot normally

make or break load current and even less fault current , They

cannot be used to parallel sources unless a zero impedance shunt-

-path exists . Besides scanning the network information to check

if an operation is possible the method also provides for the operator

to find the constraints upon that operation .

To avoid maloperation , switching should not be allowed if

the isolator adjacent nodes -

are both connected to sources

one- is connected to a source and the other connected to a sink

or an earthed node

Operation is possible in both of the above cases if there

is a direct shunt-path between the adjaCent nodes . This path

 5'3

should only include busbars and other short connecting items having

zero impedance , which can be checked by examining the nodes in

each path .

The isolator is considered open during the test and I and J.'

are the adjacent nodes of the isolator . The flowchart in Fig. 4.1

gives details of the method .

The constraints can be generated either under a form of

"sum of products" or a compact "product of sum of products" • In

the sum of products each product represents a constraint path 1

whereas the second case is a reduced form . Only the circuit-breakers

are included in the constraints , as by opening one or more the

operator can enable the operation .

Figs 4.2Aana 4.21i show examples of the constraints in both

forms to operate isolator 4/5 in the first configuration of Fig. 3.3 .

4.1.3.2 Circuit-breaker operation (including load switches)

The opening of this type of switch can cause the loss of

supply to some loads and/or the overloading of

parallel feeders .

Assuming the circuit-breaker is already open , a check is

made that all outfeed nodes are connected to the source through

at least one path .

Each feeder has a maximum power transfer capacity which is

dependent on its own rating and the transmitting end . To test

this constraint the substation network is divided , according

to internal connections , into groups of internal feeders and

 60 !

177.0,a-1
TB\
there\
any shunt
path across
nodes
J

Conn-
ections
between source
tnd

conn
ections
between sourc
end J . %Ann-
ections
between source
and J
Corin
ections 1-Z
between J
tad
OnTRAINTS1 etthi:

Conn-
ectichc
etween J
tnd
sink

PERAT:6? 1•r nL
OSS:BLP., CONST,7../;W:Z

Fig. 4.1 Flowchart for isolator operation

 GI

Adjacent nodes
Operating code
Opertor typed control

4 5

CONSTRAINTS FOR ISOLATOR 4, 5

L(14,15)
AND
L(16, 4)
AND
L( 6, 7)

OR

L(14,15)
AND
L(16, 4)
AND
L( 5, 3)
AND
L( 9,10)

Fig.4.2A Constraints for opening isolator 4/5 in initial configuration

in Fig. 3.3 under a form of "Sum of products"

4 5 0

CONSTRAINTS OR ISOLATOR 4, 5

(((
L(14, 15 )
AND
1.(1G, 4)
)))
AND
(( (
L( 6, 7)

OR

L( 5, 3)
AND
L( 9,10)
)))

Fig. 4.2B The same constraints under more compact form

 62

outside feeders . The process used is the same as that in

forming the "Feeder internal connection vector" (See Chapter III) .

For each group the elements of that vector are the same . In each

group the power demand should be lower than or equal to the

combined feeder capacity in the group .

Fig. 4.3 shows the flow-chart for determining circuit-breaker

operation . Again if,there is a direct shunt-path both opening

and closing operations are not constrained .

Fig. 4.5 shows the computer message received for the opening

of circuit-breaker ,5X.8 in the first configuration of Fig. 3.3 .

Circuit-breaker closing requires precautions if both adjacent

nodes are live in which case a synchrocheck is necessary prior to

operation . Using the path finding routine , connections between

source and adjacent nodes are sought , to determine if there is

need for a synchrocheck (some analogue relays can do this auto-

matically) .

To connect a live node to directly or indirectly earthed node

causes a fault . If one node is connected to a source and the other

to an earthed node the operation is forbidden .

4.1.3.3 Isolator and circuit-breaker switching

To carry out individual switch operations safely it is useful

to have aprogram to deal with both isolators and circuit-breakers .

In the developed program the operator types the adjacent nodes

and 0 or 1 for a switch to be opened or closed respectively .

Fig. 4.4 shows the flowchart of this program . After reading in

 63

(START

non( C.g.ttv

Ma ki .sr... J.434

0 c t • Ate,/

Fig. 4.3 Flowchart for circuit-breaker operation

 64

Fig. 4.4 Flowchart for

combined switch operation
 65

the above data it is checked for a direct shunt—path across the

nodes . If the switch is to be closed , the condition of node alive

is looked for and depending on the switch type , the isolator or

circuit—breaker routines are executed .

If there are any constraints , these are written in the V.D.U.

or teletype in an easy to understand message . If there are no

constraints the operator must type 1 for the operation to be carried

out . After the operation is executed the SM (See Chapter III) is

modified with the new switch data . Then the program controls

returns to the start ready to receive new switch instructions .

If the operator wishes just to test any constraints on the operation ,

he types 0 for the program control to return to start .

Figs. 4.2 4.5A and 4.5B show examples of operator instructions

and their respective outputs ,all relative to the first ccnfiguration

in Fig. 3.3 •
If the operator types in meaningless nodes or nodes between

which there is no switch the program returns automatically to the

start . If the state the operator types is the present switch state,

he receives the message shown in Fig. 4.5B

Fig. 4.7 shows an example of a message written when the

opening of a breaker produces a power shortage in part of the network .

4.1.3.4 Maintenance

Due to the need for regular checks or for servicing equipment,

it is necessary to earth part of the network . This part should

be. the smallest possible but large enough for the maintenance work
 66

5 8

OPENINCi OF 3REAKER 5, 3 CAUSES LOSS OF SUPPLY TO LOAD 10

Fig. 4.5A Constraints for opening breaker 5X8 in initial

configuration of Fig 3.3 •

4 5 1

SWITCH ALREADY IN THAT STATE

Fig. 4.5B Message when operator tries tc close an already closed

switch

7 1L 1

ADJUST TAP C11AN3ERS

Fig. 4.6 Closure of breaker 7/10 with nodes 7 and 1C energized

 67

17 20

GROUP 25 IS NOT SAFE

22

IF 13REAX 17,2(1 OPENS

Fig. 4.7 In the network shown on the top the power supplied

and consumed by the feeders is represented by the

numbers inside the circles . The constraints for

opening breaker 17X2C are see at the bottom .

 68

to be carried out safely. The nodes which limit that part of the

network should be earthed . Before each node is earthed it is first

necessary that it is not alive .

If an isolator or a circuit—breaker needs maintenance the

surrounding switches should be opened and only then car the two

adjacent nodes be earthed . Isolators type 2 (Chapter II1) , in

particular , cause considerable outage , in a corner of a mesh

substation , when work is required on them.. The layout in Fig. 3 .3 is a

simplified one . The mesh H.V. circuit—breakers have on each

side isolator switches , not represented in Fig. 3.3 , so their

maintenace does not cause the loss of any feeder . When the

equipment corresponding to a node is serviced,the limiting switches

have to be opened before the node is earthed . In both cases the

"Earth connection vector" (Chapter III) is modified to take account

of the earthed nodes . As previously described,any closing operation

is proceeded by a check to avoid energising an earthed node .

When using a portable earth to earth a network node, this.information•

must be input via the operator)as normal scanning willTbe ineffective

to read those type of connections .

4.1.3.5 Transformer paralleling

Before paralleling two transformers thetap changers should

be adjusted to equal taps . This situation occurs when the switches

adjacent to transformers are closed and energized . In the low

voltage part of the substation in Fig. 1.1 ,when the metalclad

breaker 7)<10 is to be closed , if the high voltage transformer

 69

nodes 1 and 1C are connected to a source , the tap changers should

be monitored . For this condition , the computer must write a

message for the operator to &djust the tap changers before allowing

the operation to proceed .

Normally the tap change operation is carried out for both

transformers at the same time to give the same final position and

so these precautions would not be necessary .

Fig. 4.6 presents an example of an attempt to close circuit-

breaker 7 X10 , in the configuration shown .

4.1.4 Conclusions

The interlocking scheme presented here is intended to be

implemented on-line , integrated into a digital computer control

system . A data acquisition system provides data for the different

system functions . The methods of network representation described

in Chapter III are used in conjuction with this interlocking scheme.

Using the mesh type substation with 24 nodes the computer store

requirements are about 3K . The programswere written in Fortran IV,

with the exception of the hardware operating routines which were

written in assembler 11acro-15 . The computer used was a PDP 15 .

Execution times were of the order of tenths of seconds ,thus

suitable for computer on-line implementation .

Significant advantages result from the approach used , in

relation to previous methods because off-line sSoldies are avoided

and computer requirements are modest .

This mehtod is able to achieve the full aims of interlocking

 70

and preventing undesirable operations whilst allowing all the other

functions . Difficulties could be experienced due to the unavaila-

bility of some data and attempts should be made to ensure as

complete a data base as possible at all the times -.

4.2 Seouence switching

4.2.1 Introduction •

The aim of sequence switching is to proceed from one network

configuration to another by. choosing automatically , the best

intermediate steps . Techniques developed for interlocking purposes

in section 4.11 are used to test the security of the intermediate

switch operations .

The method used for sequencing is to minimize the number of

switch operations , without allowing violation of any switch

constraints or feeder ratings and to avoid loss of supply to loads .

In section 4.2.2 a method is presented and tested on—line

in the substation modell described in Chapters. In section 4.2.3

the method is applied to the most common types of substation .

The execution times and compute'r memory requirements are of

suitable size for on—line application .

Previous approaches (54'55) to sequence switching used

sophisticated mathematical processes which were heavy on computer

operating requirements .

Couch (54) proposed a method which uses a penalty function to

evaluate the different possible sequences . The sequences are optimised

by penalising sequences envolving unnecessary or undesirable switch

operations . The optimal sequence will have the lower value of penalty
 7

satisfying both initial and final conditions . The number of possible

sequences grows quickly with size and in an n switch network the

number of switch configurations is 2n . The number of possible sequences

between two configurations can be much larger. To_store and examine

all possible sequences would require a lot of computer storage

and time although the possible number of network configurations can

be restricted but this will prevent the achievment of an optimal solution.

The use of dynamic programming allows a reduction in the problem

size by searching through only those sequences which start with the

initial configuration. Even with this technique the method has

large computer requirements . A further improvment is to use branch

and bound methods to limit further the number of scanned sequences .

When searching the different sequences no further scanning in a

particular sequence is executed if :

i)there is a high penalty associated with a switch operation

ii)the penalty already exceeds the penalty of a complete sequence

previously scanned

iii)one configuration occurs more than once

However the computer requirements are still too heavy for on—line use .

The assignment of the different penalties is quantitatively arbitrary

although it can influence the speed of the process .

Udo (55) formulated the problem in a different way . Fi2st ,

configurations which satisfy given conditions are detected , then

possible sequences are scanned to find the one which uses the minimun

number of switch operations . The state of the network is described

by two matrixes , one relating the connections between feeders and

buses , and the other relating to the connections of the buses

between themselves . The conditions which the final configuration

 1Z
• at

must satisfy are specified in terms of the feeders connected together .

All the possible combinations of states of circuit—breakers and

isolators are selected to satisfy those conditions. If there were

no constraints (deenergized network) the best solution would be the

final configuration in which the number of different switch states

from the initial configuration is a minimum . A "worst—case" assumption

of all feeders energized is made to decide about isolator operation

which when on—load , can only be allowed if there is a bypass .

In each step a check is also made for security of supply .

To find the optimum sequence of switching operations again

dynamic programming is used . Although employing a compact form of

network representation the program requires about 35k for a 16 node

network . No information is given on execution time , but as the method

also depends on testing many sequences it is probably also heavy

on computer time and unsuitable for our purpose here .

4.2.2 New general method

fine of the functions of the substations is to marshall circuits

(such as grouping feeders , transformer changeover , isolate parts

of the network for maintenance , etc.) . For this purpose the

network has to change its configuration through the operation of

several switches . It is important that an adequate series of

intermediate steps is produced for speedy changeover•.

Undesirable operations , which violate switching constraints,

and unnecessary operations should be avoided to minimize the number

of operations .

Isolators were previously classified in Chapter III, as type 1

 73

or type 2 according to whether an adjacent circuit—breaker is

connected to at least one side . The operation of isolators type 1

should be closely related to that of its adjacent breaker(s). As

loss of supply must be avoided , switches which are closed in the

final configuration are closed before opening those which are to

be opened latterly . Due to its nature,the operation of isolators

type 2 can raise problems and be impossible without cutting supply

to some loads .

The following steps are taken in the solution :

(i)To ensure security of supply the final configuration is checked

to see if all the loads are connected to at least one source and

that the ratings of the feeders or connected generators are not

exceeded . If this is not possible thefinal configuration must

be modified , which could be made automatically , until the

requirements of supply are met .

(ii)Closure of isolators type 1 . Operation should be possible

since their adjacent circuit—breakers should only close afterwards

(next step) . If this does not occur and there are constraints in

the closure , the adjacent breaker should be opened .

(iii)Check for constraints in the operation (openinj, or closing)

of isolators type 2 . Operate only those whose operation does not

impose any constraints .

(iv)Close the circuit—breakers which are to be closed in the final

stage . If the nodes on either side are live , make a synchrocheck .

 7 11

(v)Close isolator type 2 after checking if there are any constraints .

If none operate . If there are constraints for each different

type of substation which has isolators type 2 , a series of solutions

should be developed . For the mesh substation a complete set of

solutions was found . If any circuit-breakers were opened to allow

for this operation restore their state only if they are to be

closed in final configuration .

(vi) Open isolators type 2 , using the same procedure as in

step (v) .

(vii)Open those circuit-breakers which are to be open in the final

stage . Before opening , check if there is loss of supply to any

load , and the ratings of the feeders and generators are not

exceeded . If soo the circuit-breaker is not operated and a message

is printed indicating why operation is not possible .

(viii)Open isolators type 1 . Again their operation should be

possible , because their adjacent circuit-breaker should have

opened in step (vii) . If not , the same procedure as in step (ii)

appplies .

Fig. 4.8 presents an example of sequence switching when

passing from the first to the final configuration of Fig. 3.3 .

Each message is written before the corresponding operation is

executed . Another example is shown in Fig. 4.10 which makes the

transition between the two configurations shown in Fig. 4.9 .

 4

L:LL!!-::c. 1 !..."!;:: i1

1 NEAKER
,_J-MAKE•S.YNL'HU!..:HECK CLUSING 2

MIAtet: E:EFORE CLOSING EREAKER 11. 22

SYNCHF:OCHECK E:EFORE cLa.E.11He EREAKER 12.113

MAKE SYNCHRIP-:HFCK.EEFORE riOsiNri BREAKER 17, .20

11-*AKLF: 1,1- 1c:

(TOR
_OPFN 1A

Fig. 4.8 Sequence switching steps for configurations shown

in Fig. 3.3
 76

INITIAL

CONFIGURATION

8
dy 3 0 1t/ 25
A x
FINAL

CONFIGURATION

3 71;

Fig. 4.9 In both configurations nodes 2,13,14,25 are

supposed to be connected to source .

 77

., ., ·1·-',
J. J. J i..:::"

·1 ·1
J• .,.

..i··;'
,

,-.', -':, !:-. f

., . -. - -- .. -
, .. " . _.- ......-. :-.; .. ' .~. .....
,;

"
~_.
..L... ," ..
l ...~ ::.:'
"

.i.
.. ,-
r"~ t..~
• ~ .• _," C':' ....... t,.' .. ~: .. :-
.I. •• ', \ ' •• _r··"··.~.1 \. 1. J. ,-

OPFN. ISGL0TOR 23; 24

Fig. 4'.lC Seque,nce switching steps f-6r configurations shown

in Fig. 4.9
 78

Checking the security of supply of the,final configuration

and the sequence of the steps, adopted , ensures a simple and smooth

procedure for operation of isolators type 2 . If the operation is

not possible , because there is no direct shunt-path and there are

source-sink or source-source paths , the network is classified into

one of the following types :

(Only isolator 4/5 is considered but others can be dealt in a similar

manner by reason of symmetry)

a) Considering the central mesh four important cases can arise .

In all of them , the closure of a single circuit-breaker closes

the central mesh , creating a direct shunt-path between the nodes

of the type 2 isolator making the operation possible . Fig. 4.11

shows those configurations and the corresponding testing conditions .

If 4X16,16/17,17X20,2C/23,11X23 and 8/11 are closed Close 5X8

If 4X16,16/17,20/23,11X23,5X8 II II II
Close 17X20

If 4X161 16/17,5X8,17X20,2C/23 ,1 n Close 11X23

If 5X8,16/17,17X20,11X23,20/23 it 11 II 11 Close 4x16

Fig. 4.11 Possibilities of closing the central mesh by closing a

single circuit-breaker
 79

b) If switches, 2)C3 and 3/4 are closed and 4)(16 is open ,

breaker 2)(3 should be opened to allow the operation of isolator

4/5 . Due to the structure of the previous steps , nodes 7 and 10

are connected to a source by a path not passing through isolator

4/5 . The same applies for the next step . Fig. 4.12 .

16

7 so
Fig. 4.12 Opening of breaker 2)■3 enables the operation of 4/5

c) If switches 2X 3 or 3/4 are open , open breaker 4X 16 after

which operation of isolator 4/5 is possible . Fig. 4.13 presents

this case .

Fig. 4.13 Opening of breaker 4)(16 enables the operation of 4/5

 80
d) If at least one of the breakers 2X 3 or 4'X 16 -is to be

opened in the final configuration they should be opened , unless

•the operations cause loss of supply to a load..

e) General procedure . If all the previous steps do not allow

isolator 4/5 operation the sequence in Fig. 4.14 should be used .

./ 3 Lf /5
X / X 8.

Close 7)(10 if not already closed

Close 8/ 9 " " u u

Close 9 X10 " u II II

Open 6X7

11 11 tl
open

Cpen 5X 8 II 11 tl II

Fig. 4.14 General procedure for operating isolators type 2

In the majority of, normal operating conditions these steps

will not be necessary . Step can only be applied if all the four

mesh circuit-breakers are available for operation . Stops 121 1

ca are in most cases an anticipation of procedure vii and in

the event they do not increase the total number of operations

necessary for the sequence . Fig. 4.16 shows the sequencing output
 81.
for the configurations shown in Pig,. 4.15 . The opening of breakers

2X 3 and 24X 25 is required to allow the opening of isolators

4/5 and 20/23 respectively , but the total number of operations

is not increased . Usually the number of operations required is

equal to the minimun number of.operaticns to change the configuration

ignoring the constraints .

Fig. 4.17 shows an example of a configuration for which it

is necessary to use step el , the general procedure to close

the central mesh .

If breaker 5X8 is out for maintenance and is bypassed , and

it is necessary to use step e) to operate isolator 4/5 , the supply

must be cut .

The program can include constraints which are particular to a

certain network . For example the constraint that some load must have

at least two feeder supplies is met by checking additionally that there

are at least two paths from the load node to the feeder nodes .

4.2.3 Application of the method to several types of substation (56'57)

These problems do not occur in other types of substations ,

in which the application of the method is very simplified because

either there are no isolators type 2 or , if there are , they

behave as isolators type 1 .

Fig. 4.18 represents a "breaker and a half" substation layout.

All the isolators are typo 1 . The sequence switching now only

involves steps i,ii,iv,vii,viii . Provided that the final configuration

is a safe one , the sequencing gives the minimum possible (the

minimum regardless of constraints) number of switch operarions .

Owe
 7
g
Fig. 4.15 In both configurations nodes 2,13,14,25

are supposed to be connected to a source

INITIAL

CONFIGURATION

2 \/ 3 1.3

19 22

13

lit 15 26 17 .20 23 2,5

i-‘

INITIAL

CONFIGURATION

3 / Li ,__(z)
)(

-

83

-CLOSE ISOLATOR 11, 12

• - - - _

==CLOSE ISOLATOR 15, 16 -

_ CLOSE I SOLATOR 8, 11_ _ _ _

- - - -------- - - - - - - -- - -

_ _ _ _ _ _ _
:----=-=CLOSE SOLATOR 16, - 17 - -
_ _
- -
_
_ _ _ . _ _ _
- - - - - - - -

MAKE SYNCHROCHECK BEFORE CLOSING BREAKER 12, 13 -

'
MAKE SYNCHROCHECK BEFORE CLOSING BREAKER 14, 15
.

- -OPEN BREAKER 2, 3

- _ . _ . _ _
--OPEN ISOLATOR 4,
- - ■■•
_ -
•■•■•

- - - - - - - ----------

BREAKER 25, 24 . _ _

_
—OPEN ISOLATOR 20, 23

-jj:LOPEN ISOLATOR 3, 4

OPEN ISOLATOR 23, 24

Fig. 4.16 Sequence switching steps fo configurations shown

in Fig. 4.15
 81

CONFIGURATION
x

io

41

CONFIGURATICN

Fig. 4.17 In both configurations nodes 13,14 are supposed

to be connected to a source . In the transition

between the two configurations it is necessary

to use step €21

 g5

The same applies to the double-busbar (double-breaker) substation

of Fig. 4.19 , with the mesh type substation in Fig. 4.20 , and

with single busbar and ring busbar substations .

In the double-busbar with bypass substation in Fig. 4.21

the bypass isolators are typo 2 but as they work in series with

tha bus-coupler they behave as type 1 isolators . In the double-

busbar with selection isolators substation in Fig. 4.22 , the

selection isolators work in series with the feeder circuit-breaker

behaving also as isolators type 1

For all these types of substations the method is simplified .

Steps envolving isolators type 2 are eliminated (steps iii,v,vi) making

the required memory size shorter . The size of the program for a mesh

substation is reduced by 2k , when supressing those steps .

4.2.4 Conclusions
A method has been presented to deal with sequence switching .

The method was tested on-line with the substation model , described

in Chapter II . The core requirements are modest in the mesh-type

substation used it required 7K words including the network representation

software . The time required for the program execution was determined

by the speed of the output device which communicates with the

•
operator . Each intermediate stop required a few tenths of a second .

Both the speed and memory required are compatible for on-line use

in contrast with previous methods .

This facility avoids having to store a large number of pre-

-planned sequences to meet the most likely contingencies . The method

can also be used as an off-line tool for maintenance or load-

-shedding planning .
 86

Fig. 4.18, breaker z.nd half substation

Fig. 4.19 Double—busbar with breaker select substation

 87

Fig. 4.2C Mesh substation

Fig. 4.21 Double-bulbar with isolator bypass substation

Fig. 4.22 Double-busbar with isolator select substation

 88

CHAPTER V

FAULT CLEARANCE

5.1 Introduction

Besides the possibility of using digital computers to control

operational switching it is also possible to use them for fault

(140
switching . They can replace hard-wired circuits to store fault

clearance and reswitching sequences of operations . These sequences

can be easily changed if there are any modifications in the network .

As well as offering more flexibility , the computer scheme also

provides the opportunity for more efficient fault alarm display .

As faults must be cleared as fast as possible the operation

sequences are best stored in a program . The proper sequence is

chosen according to the zone in which the fault occured . Scanning

the switch status , after allowing some time for the switches to

operate , provides information on which to evaluate the success

of a switch operation . When circuit-breakers are opened it is

also advisable to check the output of the adjacent current trans-

formers . If the current is still flowing the operation was not

successfull . Highly reliable fault detection methods are assumed

to be available X29-37) toinitiate the tripping of circuit-breakers

which isolate the fault . The fault detection can.be done either

by conventional hard-wired analogue equipment or by a digital

computer based system . It is important that a fault is quickly

isolated in order to avoid damage in the area of the fault , to

preserve the stability of the system and to enable the reclosing

of circuit-breakers to operate non-faulted areas of the network .

 gg

The location of a fault must be accurate in order that , when

isolating the fault , the outage of healthy zones of the network

is minimized .

In the following sections the several steps , which occur

when a fault arises , are presented . The failure of primary

protection to detect a fault is not considered . Cnly the failure

of circuit-breakers is dealt with . Either for correct or incorrect

operation of circuit-breakers in fault clearance , isolation of

the fault followed by reclosing of circuit-breakers , is presented .

5.2 222Eing of circuit-breakers

Since in a standard mesh substation all four corners are equal

the fault clearance scheme will be produced for one corner only .

Extension to the other corners does not present any difficulty .

For fault clearance purposes it is convenient to split the

network to be protected in protection zones . These zones must be

the smallest possible in order to minimize the portion of the system

to be isolated when a fault occurs . The zones must be isolated

by circuit-breakers or isolators and fault detection means must

be'available in order that a fault can be established in one zone .

In a substation current transformers can be present in one

side or in both sides of an isolator or circuit-breaker (See

Figs. 5.1 and 5.2). In Fig. 5.1 if there is a fault between the

circuit-breaker and the current transformer it is detected as in

zone 1 but the opening of zone 1 circuit-breakers does not isolate

the• fault . The section of bus between the circuit-breaker and

 90

Fig. 5.1 A blind—spot is located between the current transformer

and the circuit—breaker.

Zone 1 Zone2

Fig. 5.2 The addition of another current transformer , causes

the zones to overlap , thus eliminating the blind—spot.

 91
current transformer is called a blind-spot , where a fault must

be cleared by back-up . Although the blind-spot belongs to zone 1. ,

a fault there to be cleared requires the operation of zone 2

circuit-breakers .

In Fig. 5.2 the addition of another current transformer causes

the two zones to overlap , thus eliminating the blind spot

In the case of non-overlapping zones it is common practice

to use a time delay for the clearance of a fault occurring in the blind

spot . If a fault persists after the breaker has been opened, the fault

is located in the blind spot and the breaker of the adjacent zone must

be made to open . This avoids the loss of two zones when only one is

faulty , with the exception of a fault occurring in the blind spot .

With overlapping zones the need for a delay to clear a fault is avoided

but a fault in the overlapped zone triggersthe protection of both zones .

The placing of current transformers is closely associated with

the type of circuit-breakers used . When bulk-oil breakers are employed

it is common practice to use overlapping zones as the accomodation of

the current tr:msformers in the bushings is inexpensive . In the case

of air-blast and small-oil-volume breakers separate housings are

necessary making non-overlapping zones the cheapest solution . Voltage

transformers are normally placed on the feeder side of the breakers

to be in the zone of feeder protection .

The type of configuration used depends on the relevance of

eliminating the blind-spot , a solution which increases the protection

performance but is more costly .

To simplify it is assumed the zones are non-overlapping and

a fault occurring in any blind-spot is sensed and cleared by the

back-up protection .

Fig. 5.3 shows the substation layout with the fault clearance

zones shown in the lower left corner .

 92,

When a fault occurs , the fault is detected *'and the fault

identified by either conventional analogue equipment or digital

relays . A location in the computer core ,FZON, assumes a value

according to the zone in which a fault is detected as follows :

00 no fault

11 fault in zone 1

22
FZON
33

44

55

Fig. 5.3 Substation layout. In the lower left corner the

fault zones are shown.
 93
In the case of overlappirig zones , values for faults occurring

simultaneously in two adjacent zones would have to be assigned

and protection contingency plans developed for those cases .

The sequence of switch operations is to open the limiting circuit-

-breakers of the zone made by grouping together the two zones,

followed by isolation ard reswitching .

• When a fault occurs , besides the fault zone code being

deposited in FZON the fault clearance routine is initiated .

This can be achieved through an external interrupt if the fault

detection is done by equipment other than the computer for fault

clearance switching .

If a fault occurs in zones 1,2,3 and 4 the circuit-breakers

2:■3 , 4:<16 , 5;<8 and 6X7 must open since they are the nearest

to the fault thus isolating it from the healthy part of the

network .

If a fault occurs in zone 5 , circuit-breaker 6:<7 and the

other zone 5 limiting breakers in the low voltage side must open .

Subsequently it is necessary to check if all the required breakers

are open .

After allowing for a delay corresponding to the time taken

for the switch to operate (a high speed circuit-breaker takes

about 40-50 mS) the switch status data is scanned to check if all

the circuit-breakers operated correctly to clear the fault .

Depending upon the result of this check the next step will

be the opening of the appropriate isolators to complete the isolation

of the faulted zone or the back-up operation of other breakers to

cover the failure of one of the zone breakers .

After the contents of FZCN are examined , the fault zone

is identified the corresponding limiting circuit-breakers are

 9+

opened through the issuing of operation codes . These are subsequently

decoded by the model hardware to cause the proper switches to

operate . A waiting loop is then executed in order to cope with

the relays plus contactors operation times .

The switch status is deposited in the first 4 locations of

the third bank of CPP core (See Appendix 2) , is scanned with

suitable masks to check the operation result . The simplified

flowchart for the fault clearance program is represented in Fig. 5.4 .

and Fig. 5.5
5.3 Correct operation of circuit-breakers

If the primary protection has operated correctly it is necessary

to isolate the faulted zone in order to restore the supply to the

healthy part of the network .

The limiting isolators of the fault zone must be opened .

Again after a suitable delay the result of that operation must be

checked by a similar process previously described .

If the operation was correct , circuit-breaker reclosing can

initiated but if any of the isolators do not open reclosing may

not be carried out . The operations are determined according to

the fault zone . Thus :

1.Fault in zone 1

Open isolator 3/4

If isolator 3/4 is open reclose breakers C,'\"16 5;;8 and C:7

2.Fault in zone 2

Open isolators 3/4 and 4/5

If above isolator 4/5 is open reclose brekers 5:%8 and 6:7

 (START) 95

fct.u.,t
Fig. 5.4 Flowchart for
• Yls.• rvorn.,
fault clearance

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vxwit- 1,. tirkkv1/2. tylcatt,

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fo

Swi ttPr■

kco.)-nP)1

cn c'/c6
A.
4.10/11 SWA.LC

Akian Y 3
 96

A 6m, 0 Fig. 5.5 Flowchart for

fault clearance

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Int ssa.

ahery
oincAdA.,- buia.Kir!
cond, Atmt
ONS vs.,t,zA

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itutost:

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 97

a. Fault in zone 3
Open isolators 4/5 and 5/6

If isolator 4/5 is open reclose breakers 2)(3 and 0;16

4. Fault in zone 4

Open isolator 5/6

If isolator 5/6 is open reclose 2X3 4)(16 and 5)(8

In zone 5 , restoration of supply to the low voltage side

is not possible and the high voltage side is not affected . If any

of the isolators failed to open or any circuit-breaker failed to

reclose an alarm is issued . The "Alarm" routine is described in

section 5.5

5.4 Failure of primary protection

To improve reliability more than one protection set is used

for a section of a power system network . One set is the main or

primary protection , which can be duplicated , and the other is a

back-up set , which can be remote or local in relation to the section

protected . The main protection has the shorter operating time , lower

fault setting and covers a smaller section since it is more discri-

minative against faults occuring outside that section . Back-up will

cover failures of main protection and failures of fault clearing

equipment . Normally there will be remote and local back-up protection .

 98

To improve fault clearance times , the use of a centralized back-up

protection computer based system has been proposed (67). Comprehensive

information from relay terminals is processed and the correct

protection strategy is decided according to the existing conditions .

Information from relay terminals will include the outputs of directional

relays , of main protection and the states of associated circuit-

-breakers . In case of failure of one relay the system can still

operate satisfactorily because information from many relay terminals

is used to produce a back-up tripping which isolates the smallest

area of network .

It is assumed in the examples given in this section that when

a fault is not cleared due to the maloperation of a circuit-breaker

nevertheless the fault is correctly detected .

If one or more circuit-breakers fail to open the back-up

protection must operate to clear the fault . A_message is issued

to inform the operator that the primary protection has failed .

Only a first degree back-up protection is implemented here

though in a real system a protection system will have more stages.

For faults in zones 1-4 the back-up for circuit-breakers 2X3

and 6)0 is not implemented here as it would be necessary to use

adjacent parts of the network simulated , not represented in the

model . In this case an alarm is issued .

•In zones 1-4 the back-up procedure for circuit-breakers

0(16 or 5X8 is identical .

 99

Failure of 4X16

Open circuit-breakers 14X15 17X20 and 18Y19

Failure of 5X8

Open circuit-breakers 11X 23 , 9 X 10 and 11Y 23

The circuit -breakers can fail singly or together , so it

is necessary for the fault clearance sequence to store which breakers

in the primary protection have failed .

After the back-up switching order has been issued again a

waiting loop delay is Lsed to allow for the back-up breakers to

operate .

If the operation is correct , sequence reswitching can start ,

otherwise an alarm is issued (See Fig. 5.4) . The isolation of the

faulted zone is completed by opening the limiting isolators . If

this operation is succeosfull the reclosing of circuit-breakers

can start . Assuming a correct back-up operation the following

sequences will apply for the different zones :

5.4.1 Fault in in zone 1

Failure of 4X16

Open isolator 3/4

Delay of 50mS

If isolator 3/4 is open reclose 5X 8 , 6X7 , 14X 15

17 )( 20 , 18X19

Failure of 5X8

Open isolator 3/4

Delay
 100

If isolator 3/4 is open reclose 4 X16 , 6X 7 , 11 X23

9X10 and 12 X13

Failure of 5 X 8 and 4 X 16

Open isolator 3/4

Delay •

If isolator 3/4 is open reclose 6 X7 , 14 X15 , 17 X20 ,

18X19 , 11X23 , 9 X 10 and 12X13

5.4.2 Fault in zone 2

Open isolator 3/4 if back—up operated correctly

Failure of 4 X16

Open isolators 4/5 15/16 and 16/17

Delay

If isolator 4/5 is open reclose 5X 6 and 6X 7

11
15/16 " 14X15

16/17 " 11
18 X19 and 17X 20

Failure of 5 X 8

Cpen isolator 4/5

Delay

If isolator 4/5 is open reclose 6 X7 , 11)(23 , 9 X10

and 12 X13

Failure of 4 X16 and 5 X8

Cpen isolators 4/5 , 15/16 and 16/17

Delay

If isolator 4/5 is open reclose 6 X7 , 9 X10 , 11 X23

and 12 X13
 .101

If isolator 15/16 is open reclose 14)(15

II
16/17 " II
18 X19 , 17)(20

5.4.3 Fault in zone 3

Failure of 4X 16

Open isolators 4/5 and 5/6

Delay

If isolator 4/5 is open reclose 2X3 , 14 X 1 5 , 17 X20

and 18X19

Failure of 5 X8

Open isolators 4/5 , 5/6 , 8/11 and 8/9

Delay

If isolator 4/5 is open reclose 2 X3 , 4 X16

►► ►► II
►► 9)(10
►► ►► II II
11 X23 and 12 X13

Failure of 4 X16 and 5X 8

Open isolators 4/5 , 5/6 , 8/11 and 8/9

Delay

If isolator 4/5 is open reclose 2X3 , 14 X15 , 18 X19

and 17X 20

If isolator 8/9 is open reclose 9X 10

8/11 "

► ► ►► ►► ►►
11 X 23 and 12 X13

5.4.4 Fault in zone 4

Failure of 4 X16

Open isolator 5/6

 1.01

Delay,

If isolator 5/6 is open reclose 2X 3 , 5X8 14 X15

18X 19 and 17X 20

Failure of 5 x8

Open isolator 5/6

Delay

If isolator is open reclose 2 X3 , 4X 16 9 X10 , 11 X 23

and 12 X 13

Failure of 4 X16 and 5x 8

Open isolator 5/6

Delay

If isolator 5/6 is open reclose 2X 3 , 14X15 , 18 X 19

17X 20 , 9X 10 , 11X23 and 12X13

5.4,5 Fault in zone 5

If circuit—breaker 6 X7 failed to open in the primary protection

breakers 2 X 3 , 4x 16 and 5 X8 should open

Open isolator 5/6

Delay

If isolator 5/6 is open reclose 2 X 3 4 X 16 and 5X8

5.5 Fault clearance subroutines

As the fault clearance computer is constantly receiving data

from the substation model a subroutine "Ono" is used to service

 iO3

the data transfers interrupts . The switch status data is deposited

under "true" form in location 4000C (octal) and 40002 and in

"complement" form in location's 40001 and 40003 .

After each transfer is made there is an interrupt to inform

the processor of that condition . The interrupt flag is cleared

by "Oflo" returning the control to the main program .

Each time a switching operation is executed a subroutine

"Fopera" is used . It transfers the switch operation code to the

substation model where it is decoded causing the proper switch to

operate . For noiseimmunity reasons only one operation every 5,;4S

is allowed . This means the when clearing a fault the operation

of the primary circuit-breakers is separated by about 201S which

is very small compared with practical fault detection times .

A delay loop , "Delay" , is used to allow for the operating

times of the relay and the contactors . The delay loop is

implemented by incrementing the contents of some location until

zero is reached . A delay of 5C-100 mS was used although in a

real system a smaller delay must be used as high-speed circuit-

breakers operate in about 40 MS . If the computer is used for

other purposes besides fault clearance the time delay can be

implemented by an external timing unit which is initiated by

program control and produces an interrupt when time interval has

elapsed.

Whenever a switch fails to operate correctly the operator

is informed on the V.D.U. and the fault zone is printed out when

there is a fault . When the primary protection fails back-up

information B is printed . Although the circuit-breaker(s)

 10.1

Le
which failed couldrPrinted out it is advisable to do this at the

end of the program in order to save time .

An audio alarm together with printed' information is issued

through the subroutine "Alarm" when the following conditions

arise :

Circuit-breakers without back-up have failed 0 is printed

Failure of any of the back-up circuit-breakers 1 "

11 It It II 11
" zone limiting isolators 2 "
u " " circuit-breakers to reclose_

The audio alarm is produced "printing" the ASCII code for

the V.D.U. audio signal in a decrementing loop , which can be made

either continuous or intormitent . Again this could be done using

a simple special purpose external unit .

For example the message

2B means a fault in zone 2 , with failure of primary

protection , with back-up , isolator opening and circuit-breaker

reclosing correct .

In practice a full message will be necessary to be easily

understood by any operator . The reason for using short messages

is that writing messages takes a lot of time ( 100mS per character

for a teletype and I mS per character for a V.D.U.) which would

not be available until reswitching is completed . One way to

overcome the problem is to use a stack register as a buffer store

to put out the data to be displayed . Another way is through more

complicated programming to store in the program the messages which

need to be displayed and display them at the end of the reswitching

sequence, .
 105

5.6 Final Comments

The use of a digital computer to control fault clearance and

(14) now presents little difficulty, offering
sequence reswitching

more flexibility than the conventional hard—wired schemes . The

time taken by the computer to operate the correct circuit—breakers

is some tens of /14S , being negligible compared compared to the

breakers operating time . The core requirements for the fault

clearance program and sequence reswitching is less than 1K for

the mesh corner .

 106

• CHAPTER VI

CONCLUSIONS AND SUGGESTIONS FOR FUTURE WCRR

6.1 Use of digital computers for switchinp. _purposes

The use of digital computers for switching high voltage

sustations is feasible , both theoretically and technically

having big advantages over conventional schemes , namely :

flexibility to cope with changes in network configuration or

unforeseen constraints .

decreased risk of a wrong switching operation

speed of decision

ability to tackle complex problems .

easily integrated with other computer controlled substation

functions .

Besides its superior performance , it is possible in the near

future with decreasing computer costs , it will become economic .

6.2 Noise and interference(43,46)

Problems with noise are antecipated in a substation environment ,

but careful shielding techniques can avoid them . The reliability

of computers and associated solid—state interfaces is also high ,

provided convenient insulation is used between the controlling

hardware and the substation .

Noise interference on output and input cables can be very

damaging both destructively and interfering. Twisted shielded pair

cable should be used to minimize interference . When transmitting

digital data it is advisable to use codes with error detection and

 107

correction capabilities .

Digital equipment should be adequately protected against high

transient voltages which can.cause breakdown . Electric isolation

can be provided through the use of opto—isolators which withstand

voltages up to 2.5kV , with low coupling capacitance . Transient

spikes can be supressed by the use of spark gaps and varistors in

parallel . In addition the logic circuitry should have good noise

immunity such as CMOS.

6.3 General conclusions

A model of a substation was built together with the computer

controlling hardware to demonstrate the feasibility of computer

controlled switching .

Information has been collected from the model and after some

consistency check , used to generate a compact and comprehensive

form of network representation . A path—finding algorithm was used

for the different switching algorithms to find the paths between

two nodes of the network .

The information gathered about the state of the network was

used to predict the effects of a switching operation , before being

carried out . The operator was shown the desirability of that

operation through the display of convenient messages . The operator

can thus rely on the computer for safe and quick decisions . The

programs can not only be used for any substation but they are fast

.and have modest memory requirements . Conventional schemes used

a limited number of constraints imposing limitations on the system

performance . A complete set of general constraints was used to make

 108

the scheme fully comprehensive . In this method the operator is

presented with a clear outline of the constraints and has to carry

out an easy procedure to request a switch operation.

A new sequence switching algorithm provides a method to pass

from one substation configuration to another in an optimal manner .

The criteria for optimisation is to use the minimum number of switch

operations without violating any switching constraints . As the

method is not based upon scanning all possible sequences of operations

computer memory and time requirements do not increase in proportion

for large networks . The method is simple and fast and can be applied

to all common types of substations . In some mesh type substations

the method may become rather more complicated . A solution was

presented for this type of substation to deal with the possibility

of operating the mesh corner isolators without violating any constraints.

The methods presented in Chapter IV produce strategies tc fit the

actual network conditions. They do not need the off-line preparation

of all possible contingencies , which would have to be stored in

the computer memory . Thus off-line studies and computer core

requirements are reduced .

Fault clearance programs were developed and tested on-line .

With the simulation of a "stuck" breaker conditions back-up protection

was also tested . Because of the need for quick fault clearance ,

the program already contains the correct sequence of operations to

be performed , according to the zone in which the fault has occurred .

Isolation of the fault after clearance was followed by circuit-

breaker reclosing . The operator at the same time received relevant

information about the fault location and the order of the fault
 io9

clearance sequence . Audio and visual alarms are displayed if there

is any anomaly in the fault clearance process .

6.4 Suggestions for future work

1. Use of read only memories (RCMs) to store switching programs

and sequences , using a machine language .

2. Combining of programs corresponding to the different substation

functions into an interconnected modular package .

3. Use of digital computer for back-up protection . The amount of

data for back-up protection poses a challenge to conventional

schemes and digital computer seems to be the best way to improve

the present performance .

4. Development of dedicated microprocessors for the "rapid" function!: .

5. Measurement of real and reactive power flows on feeders using

the data available from the data base and transmission to a central

computer for fault location .

6.Development of optical link current transformers to overcome

non-linearity and insulation problems of conventional models .

Development of voltage transducers with good transient response

using high impedance amplifiers after capacitive dividers .

 11 o

6.5 Original contributions

i)The construction of a substaticn modal and controlling interface

together with a FIFO link between the two processors . This hardware

was used to test on-line the switching algorithms and the fault

clearance routines .

ii)Development of a compact form of network representation to

include all relevant information fcr switching purposes .

iii)Development and testing of a comprehensive interlocking scheme -

which takes full account of switching constraints

iv)Use of a path finding algorithm , which scans network connections

to generate constraint information to give a clear picture of the

system to the operator .

.v) Development and testing of a sequence switching algorithm to

proceed from one network configuration to another in an optimal

manner .

vi) On-line testing of fault-clearance programs with back-up

simulation and reswitching facilities .


APPENDIX 1
111
1. Substation Modellinr3

The model described in this report represents a 4 switch mesh

substation as used by the C.E.G.B. in the 400 KV grid system. The
substation layout is shown in Fig. 1.

The four circuit breakers divide the substation into four

identical corners. For reasons of economy only one corner has been
modelled but the methods can be used on other corners. The model has
three phases and neutral, the isolators and circuit breakers are
represented by 3-phase contactors operated through auxiliary miniature
relays. Currents and voltages can be monitored through transducers
as shown in Fig. 2. This corner is called "PRIMARY CIRCUIT".

The nodal numbering has been chosen to be compatible with the

software developed during this work.

The other three substation corners have no electrical connection

with the Trimary circuit" and are called secondary circuits., The •
isolators and circuit breakers are simulated by miniature relays with
any connection between them. The purpose of the secondary circuit is
to test interlocking, sequence switching and back-up programs. Further'
details can be found in reference 36

A mimic diagram with the substation layout' shows the state of

all the isolators and circuit breakers (:.1.B's) in the substation.

2. Switch Status

In the primary circuit the switch status information is taken

from a microswitch mounted on the top of the contactor. The micro-
switch has one normally open and one normally closed contact, giving
duplicated data about the switch status. These contacts are also used
. for powering the lamps on the primary circuit boxes and on the mimic
diagram (Fig. 3).

In the secondary, a pair of contacts is used for switch status

and another for the mimic diagram.

In both cases it is necessary to use a voltage divider because

the status contacts are connected to 12V and the NOVA works with TTL
logic.

When a contact is closed the corresponding TTL input will be

approximately 5V, otherwise it will be 0.3V 220 x 1.6MA since the
TTL inputs sources 1.6MA when ON (See Fig. 4).

The voltage dividers are located in the first three boards of

the control circuits rack.

The connection tables are presented in Ref.37 with corrections

and modifications. New connections are described in the next section
and in Table 1.
 112
3. Connections between the substation model and the digital inputs
of the Nova

The information about the switch status is fed from the

corresponding 50 Way plug at the back of the model to a group of
25 Way and 50 Way plugs. These join with their- matched pairs in
the NOVA. (This arrangement was used in order to be easy to
change the NOVA from protection to H.V.D.C. research).

The miniature sockets in the lower panel are connected to

the upper panel using jumper connectors and the sockets in Fig. 5
are numbered according to the corresponding digital input they serve.

4. Secondary Relays

The C.B.'s and isolators in the secondary are represented by

ORNON 4302 initiative relays located in the upper left corner of the
model. Each operating coil is connected to the 12V unregulated supply
and to the corresponding driver transistor BFY50 (See Fig. 3).

The driver is turned 'ON' or 'OFF' by a bistable in the control

circuits. Three pairs of contacts are used.

The pair of contacts used for switch status are connected to

the 12V regulated supply, as are the pair used for monitoring on the
front panel sock.Ns• The mimic diagram pair uses the 12V unregulated
supply (see Fig. 6.)

5. Yimic Diagram

The substation layout is displayed in the mimic diagram on the

top of the model.

All switches have a red lamp close by. When•the lamp is lit it
means that the nearest switch is closed. Some C.B.'s also have a
yellow lamp nearby which, when lit, indicates that the nearby C.B. is
"stuck".

•6. Stuck Circuit Breaker Simulation

The substation corner C.B.'s can be used to simulate the "stuck"

condition.

In the model this condition is achieved using two bistable flip-

flops to control the relay (Fig. 7). In normal operation the dis-
crepancy switch address is a logical 1 implying that the D input of
bistable FF1 is equal to the command OPEN/CLOSE. As the output of FF1
is equal to the output of FF2 transistor TR2 is not turned on and the
discrepancy lamp is unlit.

To simulate the "stuck" breaker condition the discrepancy

address is made 0 making the D input of FF1 the opposite of the D
input of FF2. This causes the two outputs to be different and the
yellow lamp is lit indicating that condition.
 113
7. Power Supplies

For the primary circuits 200V d.c. unregulated and 12V d.c.
regulated supplies are necessary. For the secondary circuits 12V
regulated and 12V unregulated d.c. supplies are required (Fig. 8).

The regulated 12V is supplied by an APT SCV10 unit, the

unregulated 12V by a Mullard YL 6102 unit and the 200V d.c. supply
is provided by the laboratory source via a filter within the model.

Fig. 8 shows the model front panel layout in its present

state. (As the NOVA is now in a mobile unit the interface power
supply was removed and a 5V d.c. supply put in its place).

8. Model Interface

The substation model is connected through suitable interfaces

to the NOVA and PDP 15. Fig. 9 shows the system block diagram.

Digital data 24 x 2 inputs, are fed into ',he NOVA by the status
circuits. 42 analogue quantities, three-phase current and voltage
measurements are sampled using a 50 Hz synchronized clock, multiplexed
to three A/D converter channels, being these fed to the NOVA.

The data is validated within the NOVA using simple consistency

algorithms before being transferred to a "First-IN, First-OUT" (FIFO)
buffer store, and thence by direct memory access to the PDP 15 store.

The PDP-15 is used as the control processor, outputting

instructions to close and open isolators and C.B.'s as the outcome of
protection and switching programs.

The work of the author has been concerned with the PDP 15 inter-
face and the NOVA digital inputs. The interface for the switch
status was constructed by Mr. E. Horne. The 4-16 bit digital inputs
are connected to I/O bus drivers enabled by the device address and
by the 'DATA IN' pulse. Table 1 and Fig. 5 give details of how switch
data is located in the four NOVA accumulators.

9. PDP 15 Interface

The control words and the corresponding I/O pulse issued by

the PDP 15 arrive at the model line receivers. Then switch or
discrepancy addresses are decoded causing the operation of bistabls
which in turn control the relay driver transistors.

Fig. 10 shows the different functions of the control word bits

where two 4-16 decoders are used to address the gated clock input
of the bistables. Only when the switch address is present and the
I/O pulse goes 'low', does the bistable clock go 'high'.

The 2-4 decoder is used to select the discrepancy unit. If

the discrepancy address is present, normal operation is disabled and
the other bistable operates (see Fig. 7 and Fig. 11). The exclusive-OR
 111

output goes 'high', turning ON the discrepancy lamp transistor

driver.

Figs. 11 to 17 give the circuit diagrams and layouts of the

control logic circuits.

The transistor driver circuits are located on boards

9, 10 and 11.
The transistor drivers are used because the bistable outputs
have not the power capabilities to drive the relays. A free-
wheeling diode is used across the relay terminals to suppress the
inductive spike when the transistor is turned OFF.

Fig. 18 shows an individual driver circuit.

Using an additional bit it is possible to detect a single

bit error in the control word and prevent maloperation (see Fig. 19).
Although not implemented, it would be a simple addition to the
existing hardware.

The line receiver circuits and layout are shown in Figs. 20,
21, 22 which also show the timing circuit. This provides a delay of
the I0P4 (311s) in order that itis presentonljyhen all other data
has settled.

Fig. 23 shows a block diagram of the back of the rack which

contains the interface, the relay driver, the line receivers,and the
status circuits.

The switch code addresses are shown in Table 2. The decimal

addresses are used in FORTRAN, while the octal addresses are used
in MACRO. Binary addresses are useful to check the data in PDP 15
output buffer.

Tables 3 and 4 show the connections from the 104 way plug to
the model and the NOVA. The 100 way cable is a bidirectional link
with the PDP 15 part of which is common to the Power System
Simulator in Room 805C. A short link was built to enable easy
change over from one configuration to the other.

To test the model without the PDP-15 a simulation for the

control word and I0P4 pulse was built. It consisted of 16 switches
which can be connected to 'high' or 'low' logic levels, plus another
for the 10P4 pulse.

IMPORTANT
t-
Before connecting this simulation device the line receiver
boards (12 and 13) should be disconnected to avoid damage to the line
receivers.
 115

9. Power Supplies for the Interfaces

The electrical and electronic circuits of the Nova interface

and PDP-15 control logic require the following stabilized power supplies:

5V - 4A
+12V - less than lA
+15V - it It It
-12V - " It n .
-15V - " It It
-18V - " It It

Description: the supply arrangement is shown in Fig. 24. The positive

supplies are taken from the same unregulated source. Each negative supply
has an independent unregulated source because they have a common earth
due to the type of regulator used.

The regulator circuits use the integrated regulator RSTO5 which

has a stabilized source, error amplifier and facilities for shortcircuit
protection, with or without a foldback characteristic.

In the +5V supply of Fig. 25, the RSTO5 feeds a divided Darlington
cascade. The emitter resistors, besides 'balancing the current in the
output transistors, also sense the current level. The preset in the
output divider network allows a variable adjust:rent of the output voltage.

The output regulation curve is shown in Fig. 26. Besides using

short-circuit protection with foldback it also has overvoltage protection
through a power Zener which acts as a free-wheeling diode.

The other supplies with smaller current requirements use the RSTO5
to drive a single power transistor as shown in Fig. 27.

The output characteristic is of the type shown in Fig. 28 having

short-circuit protection for currents in excess of 1.2A.

The rectifier of the positive supplier and the power transistors

of the +5V supply are mounted on heat sinks with forced air cooling.

The meter on the front panel allows the measurement of the current
of the 5V supply and the output voltages of all the supplies through a
three wafer switch which connects the supply and the shunt or series
resistance to the panel meter.
 116

50 WAY PLUG
Switch BACK OF 50 WAY OR
2
25. AY (") BITS IN ACCUMULATORS
THE .MODEL
N/O N/C N/O N/C N/o N/C
4,16 Al Bl 1" Cl ACO bit 15 AC1 bit 15 .
5,8 A2 B2 2* C2 " n 14 1, n 14
3,4 A3 B3 3* C3 H ” 13 u " 13
4,5 A4 B4 4* c4 It It 12
H u 12
2,3 A5 B5 5* C5 tt H 11 H ” 11
5,6 A6 B6 6* c6 tt II 10 " " 10 .
6,7 A7 B7 7* 19* " " 9 n n 9
14,15 A9 B9 ' 9* 20' " " 7 n n 7
15,16 A10 am lo 18* H H 6 ” • u '6
16,17 All B10 C7 12' " " 5 It II 5
17,18 Al2 B12 C8 11" " " 4 - ” 4 u
18, 19 Cl D1 Al B1 AC2 " 15 AC3 " 15 ,
17,20 C2 D2 A2 B2 " " 14 II . " 14
20,21 C3 D3 A3 B3 " " 13 " " 13
21,22 C4 D4 A4 B4 " " 12 " " 12
20,23 C5 D5 A5 B5 " " 11 " it 11
23,24 c6 D6 A6 E6 " " 10 " " 10
24,25 C7 D7 A7 B7 11 11 9 II II 9 .
11,23 c8 D8 A8 B8 n 11 8 n " 8
8,9 C9 D9 A9 B9 n n 7 It II 7
9,10 C10 D10 A10 B10 " tt 6 u tt 6
8,11 cli Dll All Bll " " 5 It it 5
11,12 C12 D12 Al2 B12 " tt 4 ” 11 4
12,13 A8 B8 8* 17* ACO " 8 AC1 " 8

TABLE 1 : Switch status connections to NOVA

 Switch Operation Code (binary) 0.C. (octal) 0.C. (decimal) Discrepancy 0.C. (binary)
2,3 001 101 X01 111 111 .111 15 X 777 54271
3,4 101 101 X01 111 111 111 55 X 777 185343
4,5 010' 010 X01 111 111 111 22 X 777 74751 •
5,6 111 101 X01 111 111 111 75 X 777 250879
6,7 011 101 X01 111 111 111 35 X 777 119807
4,16 100 010 X01 111 111 111 42 X 777 140287 100 010 X00 101 111 111 -.
5,8 000 010 X01 111 111 111 02 X 777 9215 000 010 XC0 001 111 111 ..;
8,9 110 101 X01 111 111 111 65 X 777 218111
9,10 000 101 X01 111 111 111 05 X 777 21503
8,11 oil 110 X01 111 111 111 36 X 777 115711
11,12 001 110 X01 111 111 111 16 X 777 58367 •
12,13 110 010 X01 111 111 111 62 X 777 205823
. 11,23 100 101 X01 111 111 111 45 X 777 152575° .
14,15 110 110 X01 111 111 111 66 X 777 222207
15,16 010 110 X01 111 111 111 26 X 777 91135
16,17 000 110 X01 111 111 111 06 X 777 25599
17,18 011 010 X01 111 111 111 32 X 777 107519
18,19 101 010 X01 111 111 111 52 X 777 173055
17,20 001 010 X01 111 111 111 12 X 777 41983
20,21 111 010 X01 111 111 111 72 X 777 238571
21,22 100 110 X01 111 111 111 46 X 777 156671
20,23 010 101 X01 111 111 111 25 X 777 87039 •
.23,24 101 110 X01 111 111 111 56 X 777 189.439
24,25 111 110 X01 ' 111 111 111 76 X 777 254975 .
X is 1 for closing X is 5 for These codes X is 1 for closing
X is 0 for opening closing apply for X is 0 for opening
X is 1 for opening.
opening For closing
add 20118

TABLE 2: Codes for switch operation and discrepancy simulation

 1/8

CABLE FROM 24 WAY PLUG FOR

BIT L. RECEIVER INPUTS
L. BIT OUTPUTS
DUMMY CONTROL
LEVELS
104 WAY PLUG WORD'

+ - + - (to controllogic)

0 E A 12-2 12-4 12-6 20,11

1 K P 12-5 12-3 12-8 21,10

2 Y U 12-13 12-12 12-15 22,13 .

3 h c 12-11 12-10 12-16 23,15

4 r m 12-21 12-19 12-23 17 .
5 z v 12-18 12-17 12-24 7
12-33
6 AJ AD 12-40 12-39 12-34 19
12-35
7 AT AN 12-29 12-27 12-30 16,12,1
8 BB AX 12-26 12-25 12-31 3
13-6 18
9 BL BF 13-2 13-4

10 BV BR 13-5 13-3 13-8. 2

11 CD BZ 13-13 13-12 13-15 Not connected

it II .
12 CN CJ 13-11 13-10 13-16 .

It II
13 F B 13-21 13-19 13-23

II II
14 R L 13-18 13-17 13-24

15 Z V 13-29 13-27 13-30 it ii

si II
16 I d 13-26 13-25 13-31

Not con- II It
17 n s Not con- Not con-
nected nected nected
12-36

I0P4 AA w 12-41 12-42 12-37 8

TABLE 3: Path of PDP 15 control word from the 104 way plug on the
right lower side of the model to the 24 way plug on the
back of the.interface rack. From this plug the PDP 15
word goes to the control logic in boards 4 and 5.
From PD? Twisted pair cable From NOVA Twisted pair cable 50 WAY Plug 104 WAY plug
15 to to Level 5 on the NOVA on the model
level 8 + - - + - + - + -
. .
Bit 0 White/Green - Turquoise Bit 0 Brown - Black B12 Al3 AK AE:'
1 Blue - White/blue 1 Grey - Red B11 Al2 AV AP
2 Yellow - Green 2 White - Yellow B10 All BC AY
3 White - Red 3 Turquoise - Pink B9 A10 BM BH
4 Black - Brown 4 Green - Blue B8 A9 BW BS
5 Pink - Lilac 5 Lilac - Orange B7 A8 CE CA
6 Red/Blue - Yellow/red 6 White/Red - Orange/Green B6 A7 H C
7 Grey. - Orange/Grey 7 Blue/Black - White/Blue B5 A6 'S N
8 Orange - Red/Black 8 Yellow/Blue - Orange/Blue D12 • C13 a W
9 Red - Green/Yellow 9 Red/Blue - Green/Brown Dll C12 j f
10 Blue - Green/Yellow 10 Yellow/Red - Red/Black D10 Cll t . p
11 Red/Black - Green/Orange 11 Black - Red D9 C10 AB • .x .
12 Blue/Black - White/Red 12 Brown . ..- Lilac D8 C9 AL AF
13 Brown - Red/Blue 13 Blue - Pink D1 c8 AV AR •;•
14 Turquoise - Pink 14 White - Green D6 C7 BD AZ
15 Orange/Blue - Grey 15 Blue - Red B5 c6 BN BJ
16 Lilac - Yellow • .
17 Not conn- - Not conn-
ected 'ected
. .

I0P4 Green/Brown - White/Red DOA Yellow - Green D4 C5 CR CL

CLOCK CLOCK •

TABLE 4: Connections between 104 way plug on the front of the model to line receivers (continued from previous
table) and to the 50 way plug on the back of the NOVA computer.
 120
Card 1 (close to main transformer) •

. Pin connections

ti

1 - earth OV 23 - Base of +5V p.t.

2 - NC 24 - NC
3 - To base of +12 power 25 - NC
transistor (p.t.) 26 - External sensor of +5V
4 - NC 27 - NC
5 - External sensor for +12V 28 - NC
6 - NC 29 - NC .4

7 - NC 30 NC
8 - To emitter of +12V p.t. 31 - NC
9 - External sensor of +15V 32 - NC
10 - NC 33 - NC
11 - NC 34 - NC
12 - To emitter of +5V p.t. 35 - NC
13 - NC 36 - NC
14 - NC 37 NC
15 - NC 38 - NC
16 - NC 39 - NC
17 - NC 40 - NC
18 - NC 41 - NC
19 - NC 42 - NC
20 - To emitter of +15V p.t. 43 - Unregulated positive supply
21 - To base of +15V p.t.
22 - NC

NC - Not connected
 121
•Card 2 (close to electrolitic capacitors)

Pin connections

1 - 18V supply 23 - to base of -15V p.t.

2 - NC 24 - NC •• •
3 to base of -12V p.t. 25 - 15V supply '
4 - NC 26 - NC
5 External sensor of -12V (earth) 27 12V supply .
6 External sensor of -15V (earth) 28 - NC
7 NC 29 - AC for -12V
8 To emitter of -12V p.t. 30 - NC
9 - External sensor of -18V (earth) 31 - Unregulated supply to
10 - NC collector of -15V p.t.
11 To emitter of -18V p.t. 32 NC
12 - NC 33 -. AC for -12V
13 - NC 34 _ NC
14 - To base of -18V 35 - AC for -15V
15 NC 36 - AC for -15V
16 - NC 37 - AC for -18V
17 - Unregulated supply to 38 - NC
collector of -12 p.t. 39 - Unregulated supply for
18 - NC collector of -18 p.t.
19 - NC 40 - NC
20 - To emitter of -15V p.t. 41 - NC
21 NC 42 - NC
22 - NC 43 - AC for -18V

NC - Not connected
p.t. - power transistor
 122

Fig. 1: Mesh type substation layout -

 SECONDARY
CIRCUIT • 1.11
/
15" 16 171 201 / 23 / 2?
X
(one line simulation)

PRIMARY CIRCUIT
( three phase simulation)

fl
• Z 3 11 7
• C-X-Nir X-t3

Key

Transducer
(Linear coupler)
--CD- Voltage transformer
10

I Fi g. 2:Mesh substation primary and

. • secondary circuits.
 121

:.,
r A Red
closed signal I ;on the mimic dicgram
' (MS)

I
Front
I panel

open L t—jmicro switch

200V
, Contactor
,1.3A Fuse I (r-0'.1)
N /C 1:
--o-
500Q ? t.:10

5W 5.1:(R2 I 1.4 B1 2 1 I
RI
—I 1+
33pf
ril
R3

-
Litt
L- I I .B c
D\
r ---- ( AR)
Green
IC
Address of discrepancy unit
Ire:ay
3.9K 1 Red
CEFi) C)E L
clock I
R S Driver On the front
(DR) panel

r-- 1-2--
on the front L
panel Yellow
L -------J
3.9K
0/C Sigr.al V,■
DCFF2) 3.9K
Clock
P. S

Switch Control Logic

Fig.3: Contactor Control Unit.

 125

+12 V
330Q
, TTL INPUT (normally open)
220Q

2205
TTL INPUT (normally closed)
33052
+12V

Fig.4.

bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
L.E.D.
AC3 0000000000000000

AC20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Aci 0 0 0 0 0 0 0. 0 0 0 0 0 0 0 0 0
Ac00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4 5 6, 7 8 9 10 11 12 13 14 15

ACO 0 0 0 0 0 0 0 0 0 0 0
4 5 6 . 7 8 -9
0 0 AC1 000000
Not used i 10 11 12 13 14 15
50 way
0 AC1 000000
4 5 6 7 8 9 10 11 12 13 14 15 O D
AC20 0 0 0 0 0 0 0 0 0 0
I I]
wa:
o 8
10 11 12 13 14
AC36 25 way

Fig.5.
 126

Ormon relay
MH4P .

Q output
of bistable

Fig. 18.

To diagram
mimic
16 9.--1--• 10 12V UNREG
14 15- 8-
NIO to computer
15 - 6 -i- 12V REG
12V REG
Monitor ll 12-i-- 5-t
NIL to computer
socket

12V UNREG 1 To driver

Fig. 6.
 127

Aux. relay coil

in the control
unit.
DRIVER

Discrepancy Z= x for S=0

Switch Z=7 for 5:1
address TR1
3.9K
i t/kA BFY 50
3.9 K.

close
open

anual

Command
open (0) D - FF2
close( 1)
C r.I?i. r t

Discrepancy
lamp on the
mimic diagram

Fig. 7: One control logic and driver for a switch with discreprancy
facility.
*Clock was .previously enabled by normal switch address


128

Mimic Diagram

Secondary relays Control logic rack

12V supply 200Vsupply Set reset secondary 1.

(Reg)) Filter switcher

3/4 isolator -
. .
4/5 isolator
. .
6x7 and 2x3
circuit breakers

5/6 isolator

4x16 and 5x8

- circuit breakers

. .

n 100 way plug

12V supply (unregulated) j 5V supply

Fig. 8: Model configuration ( present state )

 129
.4
100 way I
cable

104 way plug

Line receivers Line drivers

I0 P4 Clock
Timing 1
Open
Close

Discrepancy
and switch
decoders

NOVA
Bistables

Nova digital
Relay drivers inputs 24x2

Sample and hold

multiplexers
A D converters
42 Amalog inputs

Primcry Secondary
Status circuits

Mimic diagram
Synchron.
clock

Fig.9: System block diagram ( level 8).

 1.o

enable discrep. enable switch

•if (0) bit group
discrep. close
address open bit switch address
I0 P4- .1
•

10 9 81 7 6 5 4 3 2 1 0

2-4

4 -16 2 with
Group 1 Decoder d iscreps
if tit 5=0

Gr 6
normal
62

clock
Timing

4 -16 16
Decoder normal
Group 2
•if bit 6:0

Enable control if bit 8 = 0

Fig. io pDp-15 output control interface.

 39
•
20 21

LI D R 7474 5
4n 3
3
E3
9
Discrepancycircuits- Logic board

R
41
• 13

7402 7486 7436 '

E2 E4
74155 28
3 26 27 •
11 3
bit9 0-
13 10 5 1 411
bit 10 2-4 4 29
D R 7474 5 0
Decoder 5
9 14 11 8 C ,
bit 8 10 9
bit 11 10
El C R
12 11
13 1: 13 10
12
13
11
43 )

• 1 24 25

v •5V
2
74 74
0 40
C
E6

22 23

7474 31
42 - 0
• o
E5

5
11, t7
 132 J

ES
)
1

l•

E5 E6 E7
) )
0

1 1

E3 E4
)
1 1

)
0
1
El
I
1
E2

r i
El -SN74155
E2-SN7402
E4,E8-SN7486
E3,E5,E6,E7-SN7474

Fig. 12: Discrepancy logic board, No.4 - Physical layout.

 133

74154
Vcc 24

10 bit 1 23 A 2

13 bit 2 22 B
•
14 bit3 21 c 4
•
4 -16
15 bit4 20D
Decoder
21 bit 19 62
o
20 bit 6 18
G El 7
17
16 9

15 10 e•

14 11
13 12

.43

1 .Vcc 24 74154

29 bit 1 23
•
29 bit 2 22
30 bit 3 21
31 bit 4 20
o E2
32 bit 8 19
33 bit 5 18

17
16

15 10
14 11

13 12

43

2 10P4 clock
•

Fig.13 : Switch address decoders. Logic board No.5.


1 43

E1,E2-SN74154
E3,E4,E5,E6,E7,E8-7402

Fig.14: Decoders and enable logic board, No.5-Physical

layout.
 135
42 40
11 41
S
7474 39

41

2
D 38

1C

R S
1312 1015
134 135
R S
37
7474

36

S
18 ho
130 131
R S
D 33
7474
32

11

14 C
R S
112 115
127 128
25
7474
29 C

21 C
R S
116 122

bit
3
Vcc
1

43 PIN 743
PIN 14 1

Fig.15: Control flip -flops - Board 6.



136

42 140
1
R S • 5
0 39
7474
41

121 D
10

1
R S
1316 1019
138 136
R
D 35
7474
37

D 14

12
R S

134 .132
R
31
7471

33

D 18

16
R S
115 117
130 128

27
7474
29

D 23

R S
119 122

bit 6
3
Vcc
1

43 PIN 7 43
PIN 14 1

Fig. 16: Control flip-flops- Board 7.

 137

37 35
11 41
s Q 34
74 74

36

12 D a 14

12 C
R S
13 11 1055—
__J33 131
30
7474
32

18

16
R S
115 117
129 127
R
D 26
7474
28 Not used

D 2J

21 C
R S
119 122

bit 6
2
Vcc
1
43 PIN 7 43
PIN 14 1

Fig. 17: Control flip-flops - Board B.

 138

Fig. 19: Using a word of even parity generated by the PDP 15 program,
single bit operating errors are detected and prevented with the
circuit shown above. It requires the replacement in the control
logic circuits of the 10P4 clock by the parity 10F4 clock and the
additional use of bit11.
 139
0.orr-

Outp ut
C2
Twisted pair Zine
I100pF

Vcc C1 S robe C2
0
14 ° National DM8820 line receiver.
In all the receivers the strobe is
connected to .5V through a 1-2kg
resistor.

Strobe C2 Ground

.5V
2 6 bit 1 ( 0)MSB
4
6 1
DM88201
3 9 I B bit 2(1)
5

11 16 bit 4 (3)
10 I I
2
DM8820
12
13 15 bit 3 (2)

18 24 bit 6 (5)
17 —U71

I
3
DM8820
19
21 23 bit 5 (4)

26 31 bit 9 (8)
25 I
DM8820

27
29 I 30 bit 8 (7)
1µF 5.1K .5V 0.22pF 6 8K .5v
• 5V
• 15K 5 r-u--F------15K 5
6
1.51( 74121 1.5K 74121
4 4
41
42
5
DM8820
0
4 CS

36 10P4 clock
Vcc 37
B 9 1 11 12 14

1.2K 1.2K
) SN7407 .5V
12K 12K 12K
2 3 Gnd

33 bit 7(6)
35 Open-Close
34

43 Ground

Fig.20:. Card 12 with line receivers and timing.

 1

1
140 ;

-,,

E7 E6

1 1

E8 E5

1 1

E2 E3

1 1

El E4

1 1

n
El, E2, E3,E4,E5 - DM 8820
E6, E7 -SN74121
EB -SN7407
Fig.' Line receivers - Card 12 - Physical layout.
 141

2 6 bit 10 (9)

4 [DM8820
3

5 8 bit 11 (10)

11 16 bit 13 (12)

10 DM8820
12

13 15 bit 12 (11)

18 24 bit 15 (14)

• 17 DM8820
19

21 23 bit 14 (13)

26 31 bit 17 (16)
0
25 DM8820
27

29 • 30 bit.16 (15)

Vcc
1

43
_L

Fig.22: Board 13 - Line receivers .

 192

50 Ways-Switch status from

primary and secondary.

24 Ways - P DP15 output

simulator to control logic.

24 Ways - From drivers to

secondary relays.

12 Ways to
discrepancy
lamps

50 Ways-Switch status to Nova

digital inputs.

50 Ways - to set reset of

secondary flip - flops.

Fig.23:Connectors on the back panel of the rack.

 i

193 i

+5V
I •Serie
17 Voltage
I V- Regulator
(SYR.)

+12V
S.V.R.

+15V
S.V.R.

1
S.V.R.
470p.F
-15V

S.V.R.
47011F
-12V

Fig.24: Arrangement of power supplies.

 •

2N3055 0352
We--

2N3055 0.3Q

+ Meter 2N3055 +5V

--Wy

Unregulated 56052*
10M2
supply 10
2.7kQ RSTO5 1 6V
2 10W
500pF

51IcQ Bka 7-51.d?

Fig. 25: Regulator circuit of 5V supply.

4,2A 7A

Fig.26 : Current voltage curve of the 5V supply.

 1215

2N3055 050-

6
11014
10
Unregulated 2.7l:Q RS TO5' 1
supply 2
---93 500pF
97 7 75kQ •
1

Fig. 27: Regulator circuit for small current power supplies.

Resistance values for 12V.

12V

1,2A

Fig. 28: Current-voltage curve of 12V supply.

0 0 0
+12V -12V -15V -18V

+15V
Fig. 29: Layout of the power transistors on the left side of
the power supply-unit.
 146

V(15V)
V(12V), ' , V(-12V)
V(5V) , - V(-15V)
1(5V)- - V(-18V)

Fig. 30: Front of supply unit.

1 E 7 .E
2 -12V 8 E
3 -15V 9 +5V

4 18V 10 +15V •
5 E 11 +12V

6 E 12 E

Fig.31: Pin connections on the back plug of supply unit.

 1i7
APPENDIX 2

FIFO LINK
1. Function of Device
The first-in-first-out (FIFO) link was dc-signed to enable
a fast transfer of data from the NOVA 12C0 minicomputer to the
core of the PDP 15 using direct memory access (DMA). The device
can also be used with any other peripheral provided the data rate
is not exceeded and the format is suitable.

The NOVA Computer is used as a data acquisition processor

and is interfaced with the substation model from which it receives
36
digital and analogue data . Data collection undertaken at a
variable sampling.rate according to the needs of different algorithms
and the amount of data per sample and the number of samples may also
vary according to the application.

The PDP 15 is the control and protection processor, using the

data previously validated in the NOVA. In order not to waste
processing time the data corresponding to a sampling period is
accumulated in the intermediate FIFO store and then transferred
through DMA to the PDP 15 core.

The block diagram of Fig. 1 outlines the functions of the

FIFO device.
 118

2. Mode of Oreration
2.1 General Dcserintion

As the two computers run assynchronously, FIFO memories were

chosen to form the links. They provide completely independent read
and write operations and can accept data rates up to 11.UIZ thus
making them compatible with PDP 15 I/O processor.

A single-cycle DMA channel was chosen as having adequate

speed, to allow a burst of data at 1MHZ in 18 bit bytes to be
transferred into the PDP 15 core. There is no intervention of the
CPU in this transfer and during the transfer time the CPU cannot
have access to the core. The device keeps track of word count and
address count in a single-cycle data channel access.

Fig. 2 represents a detailed functional diagi.am of the FIFO

and the control logic.

For reasons of economy the line receivers, I/O bus connectors, API and
bus drivers used are common to the Power Systems Simulator I/O unit.

A switch on the front of the device selects which system is

connected (see Fig. 3). The functions of that switch are

- to control the selection of the outputs in the data multiplexers

- to select the incoming signal as the NOVA clock or the P.S.Simulator
interrupt
- to control the bus driver enable multiplexer
- to control the overflow (OFLO) register multiplexer.
2.1.1 FIFO arrangement
A parallel-series 2 X 2 arrangement of 32 X 9 bits FIFO devices
A]1 2813 provides a storage capability of 64 - 18 bit words. Fig. 6
shows the logic block diagram of this integrated circuit.

Data on the inputs are written into the memory by a pulse on-load
(PL) which in this case is the NOVA clock. The data word automatically
ripples through the memory until it reaches the output or another data
word. Data is read from the memory by applying a shift-out pulse on •
Pulse Dump (PD). This dumps the word on the outputs and the next word
in the buffer moves to the output. An Output Ready (OR) signal
indicates that data is mailable and also provides a memory empty signal.
An Input Ready (IR) signal indicates the device is ready to accept data
and also provides a memory full signal.
 The AM2813 FIFO has 32 - 9 bit 'data registers and one 32 bit
control register as shown in Fig. 6. A "1" in a bit of the control
register indicates that a date word is stored in the corresponding
data register, otherwise the data is not valid. The control register
directs the movement of data through the data registers. When the
th th
n bit of the control register contains a "1" and (n + 1) bit
th
contains a "0" then a strobe is generated causing the (n +1) data
th
register to read the contents of the n data register, simultaneously
th control register bit and clearing the nth
setting the (n + 1)
control register bit so that the control flag moves with the data.
Data in the data register moves down the stack of data registers
towards the output as long as there are empty locations ahead of it.
This fall through operation stops when the data either reaches a
th
register n with a "1" in the (n + 1) control register bit or the end
of the register.

Fig. 7 shows the FIFO arrangement. The timing and function of the
four control blgnals P1, IR, PD and OR are such that two'FIFO's can be
placed end to end with the OR of the first driving the PL of the second
and the IR of the second driving the PD of the first.

The total ripple through time in this configuration is thus

double that of a single FIFO ( 2 x 81s).

The computer Power Clear, pr6duced either by the reset key on

the console or by the CAF instruction, has a width of 25 .s which is
enough for the TTL logic. However, as the FIFO is a MOS device it
requires a wider pulse. The FIFO Master Reset is a pulSe of 56011.8
which exceeds the minimum requirements of 400ns by a reliable margin.

It was observed that the output of the device could only operate
at a 1 MHZ rate when the Pulse dump "High" portion was narrow this
again is due to the high input capacitance of MOS device. With a P.D.
pulse width of 15Ons it takes about 750qs for the FIFO outputs to
change.

To overcome this delay the leading edge of. the Data Channel Grant
(DCH GR) pulse is used to clock P.D. whilst the trailing edge triggers
the change in address. The reduction of the P.D. pulse width is
achieved by the second monostable.
 15 0

2.2 Block Length Un-Counter and Control Logic

From the FIFO the data goes via the data multiplexers, (which
are controlled by the front panel switches) to the bus drivers. These
in turn are "Enabled" by the single cycle controllogic "Data Channel
Enable" (DCH ENA) signal.

The Block-Length-up counter in Fig. 8 receives

the Nova clock, and counts the number of data words currently stored in
the FIFO.

The left pair of BCD switches on the front of the unit (Fig. 9)
provide the setting of the Block Length (B.L.). The BL should be
equal to or rrcr,ter than the number of data taken in each sample, in
order that data accumulated in the FIFO does not exceed its capacity.

When the number of clock pulses received is equal to the D.L.

setting a date channel request pulse is generated.

This request is enabled if

1 BL < 64
and if the left pair of BCD switches, the Number of Blocks (NB) setting,
is
1 < NB < 99

These conditions prevent operating errors in the selection of the

EL and NB settings.

Setting either BL or NB to zero provides a means of disabling

the device, Which should be done when the unit is not in use, the
front panel switch should additionaly be set in the FIFO position.

An equality in the comparison between the switch data and BL

up counter outputs gives rise, after enabling by the conditions
mentioned above, to a negative pulse which is steered through a mono-
stable network to *clear the BL up counter. The delay produced is
about Nals in order that counter is ready when a new word arrives
at the FIFO input.
 151

2.3 Number of Blocks Counter and Control logic

The NB counter in Fig, 11 is set initially by the Power Clear

pulse to the number of blocks to be transferred to the PDP-15 core.
Each block contains data corresponding to a single sampling period.
The NB setting should be equal to the number of samples which are
relevant. The NB BCD switches are on the right of the front panel
(Fig. 9). The BCD Binary converters are connected to the parallel
inputs of the 7-bit down counter. Each time a block is transferred
into the PDP-15 this counter is decremented and when it reaches zero
a pulse is generated indicating that a complete block of data is
present in the PDP-15 core. After a delay this pulse is used to reset
the address and NB counters to their initial settings.

In Fig. 11 the 9,10 inputs of the E20 NOR gate are the Data
Channel Request generated by the BL counter (in Fig..8) enabled by
the condition 1 4 Bl . 64. The output of the NOR gate is restricted
to 1 4 NB ‘ 99.

2.4 Block Length Down Counter

The block length down counter in Fig. 12 is initially set to the

BL using the parallel inputs and Power Clear pulse which is clocked
each time a word goes out of the FIFO (see Fig. 2).

After the penultimate and last transfers conditions have been

detected respectively at E20-6 and E17-11, two signals are generated
which are used by the single cycle data channel and the program
interrupt control logic. The counter is reset to the BL value
approximately 10Ons after completion of the block transfer, thereby
starting the transfer of a new block. The signal "transfer of block
complete" E17-11 is used to clock down the NB counter in Fig. 11.

2.5 Address Counter

The Address .Counter in Fig. 13 is a 15 bit down counter, set

initially by the power clear pulse to the complement of the first
address in core where data is to be deposited. The use of the
complement and the down counter arises because the bus drivers invert
the outputs of the Address Counter. Fig. 14 shows a picture of board
19 where the FIFO chips, part of the single cycle control logic and
 152

the address counter are located. On the right are the miniature dual-
in-line microswitches set for 37777 (octal) which is the complement
of 40000, the first location of the third bank. The initial address
should be such that a whole block of data does not interfere with any
resident software or user's programs. Each time a transfer is made
into the PDP-15 the address counter is clocked. When all the partial
blocks are transferred the NB counter generator a pulse which sets the
address count to the initial address to allow.the overwriting of the
oldest data with fresh data.

2.6 Single Cycle Data Channel Control Logic

The Single Cycle Data Channel Control logic is represented in

Fig. 15. The Data Channel Request generated by the BL counter and
enabled by the BL and NB settings is delayed by 17us, to allow for
the worst case conditions, when the BL is set to one and the computer
responds quickly to the request. It takes about 161ts for the word to
be ready at the FIFO output (ripple-through-time) after the request
pulse is generated. The maximum latency time for servicing this
peripheral is 8.5.4s. If the BL is larger than one the required delay
will be less as each word takes 1 its to come out of the FIFO.

The delayed request pulse is used to set the Data Channel Flag.
This flag is synchronized with the I/O processor by means of the I/O synch
clock setting the Data Channel Request (DCHRQ) register. This activates
the Single Cycle Request (SINGCYRG) and Data Channel Request (DCHRQ) lines. .
The I/O Processor responds to the request with a Data Channel Grant
(DCHGR) which sets the Data Channel Enable (DCH ENA) register. This
is used to enable the data and address bus drivers, and, together with .
the grant (DOH GR) pulses, to decrement the address and word count. The
change in FIFO output is derived from the grant (DOH GR) pulses (See
Figs. 2, 7 and 10).

The DCH Flag is reset either by the Power Clear or by the control
logic.

When no data transfers are taking place the Burst/Normal register

is in the "Burst" state. It remains in this state during a transfer
peribd until the BL down counter and logic senses the penultimate transfer
 153
whereupon the register is set to the."Normal" state. Upon completion
of thb block data transfer the I/O sync clock resets the register to the
"Burst" state.

The Data Channel Enable In(DCH ENIN) line will inhibit the Data
Channel Request (DCII REQ) register if it is "low". As this peripheral
is a high priority device it should be nearest to the I/O processor in
order to avoid the condition mentioned above. When the Request register
is set the Enable Out will go "low" and the next peripheral on the bus
will receive it as a "low" Enable In pulse.

2.7 Status, Skin and Interrunt

The Status, Skip and Interrupt (in Fig. 16) receives a pulse from
the BL Down Counter each time a block of data is transferred into the
PDP-15 core. This pulse sets the OFLO flag which produces an interrupt.
The way in which the interrupt is serviced depends upon the enabling
of the Automatic Priority Interrupt (API), shown in Fig. 17, by the
program.

If API is disabled the following mechanism is used:

- The Program Interrupt Request (PROGINTREQ) line is activated.

- The C.P.U. traps to location zero in blank zero, storing the
contents of the Program Counter and executes the contents of
location 1.
- The instructions from the system routine then try to identify the
device which caused the interrupt since all the peripherals share
the same Program Interrupt Line. Successive IOT skip instructions
are issued, one for each perimpheral.
- The device that respond3with a Skip Request CEIP REQ) is identified
as the requesting device. This pulse causes the program to jump to
the device service routine.

The Read Status line is used to issue a pulse which gates the
peripheral status flag onto the I/O Bus where it is read by the C.P.U.

2.8 Automatic Priority Interrupt

As the interrupt identification flag-searching process is time

consuming.it is advisable td enable the API*.

* The API can be enabled or disabled by a single IOT instruction

 151
There are 8 levels of priority, the four upper levels service
peripherals, and the four lower levels service software routines which
transfer contro] between prbgrams.

As the FIFO requires fast servicing, its priority is located in

level zero. In a way similar to the data channel, the devices that use
the same API level are graded in priority, by multiplexing the API
Enable In signal at that level. The signal is wired in series through
the devices in the same priority level. If a device in the chain wants
to communicate with the I/O Processor it traps the signal, thereby
disabling the devices on the further side (in relation to the computer).
If the device is idle it passes the ENABLE signal to the next peri-
pheral.

The I/O bus contains for each of the /4 API hardware levels 3 lines,
the API Enable In mentioned above, the API Request and the API Grant.
The way the API controllogic works is similar to the Single Cycle
Control logic. Here the OFLO flag synchronized with- the I/O sync
clock sets the API Request register, which in it turn activates the
API Request line. The I/O processor answers back with an API Grant.
This signal sets the API Enable register.

Each device interfaced with the API, when an API Grant occurs
in answer to an interrupt sends its trap address. In this core location
there is "jump to subroutine" instruction which transfers the control .
to the device service routine. Core locations ti0 to 77 (octal) are trap
addresses for the peripherals. As seen from Fig. 17 the API Enable
register output activates address lines 12, 13, 15, 16, which means
the trap address is 66 for the FIFO device.

2.9 Device Selection

The Device Selection logic in Fig. 18 is used to decode the I/O

instructions (10T). Each peripheral has an address and all instructions
for a device should have encoded that address. During the execution
of the instruction the device address is transmitted to each device
but only the correct device decodes the address, thus enabling the
instruction signals.

As seen from the Data Selection (DS) line 0 - 5 in Fig. 18 the

device address is 50, which enables the I/O Pulses.
 155

The IOP1, I0P2 and I0P4 pulses can be sent to the device
as bits 17, 16 and 15 respectively of an IOT instruction. The SDO
line is the subdevice select line decoded from bit 12 of an IOT
instruction.I0P1 when sent alone tests the device flag and if the
flag is set at the Skip Request line is activated. When IOP1 is
sent with SDO the device flag is cleared. I0P2 is used to transfer
data from the device to the computer and I0P4 to send data from
the computer to a device register. The last two pulses are only
used by the P.S. Simulator.

Fig. 19 and Fig.. 20 show respectively the Data and the

Address bus drivers connections. In both cases the bus drivers
are enabled by the Data Channel Enable generator in the single
cycle control logic.

Fig. 21 shows the circuits on board A16. A hybrid bus receiver

with high input imfrdance is shown on the bottom to receive the Data
Channel Grant (DCHGR) signal.

Fig. 21 and Fig. 22 represent the module locations and the

module functions.

Table 1 outlines the data paths from the line receivers to

the I/O bus connectors.

Table 2 describes the Address and Data Channel bus connections.

3. Programming

The input-output instructions in the PDP-15 have the

following structure :-

MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

11 0 1 0
Operation Code
Hil
Device Selection

Subdevice
• • Selection

Clear ‘I
Accumulator
V
Control Pulse Selection (I0P4,I0P2JC
 156

For the FIFO peripheral the device selection number 50 has been
allocated. The instruction pattern is of the type 7050XY (octal) in
which X and Y depend on the type of operation required.

With this device only two operations are required, "Test device
flag with skip" and "clear device flag". In the first case IOP1 pulse
(bit 17) is used so the instruction "skip on device flag" is

705001.

In the second case; IOP1 pulse (bit 17) and the subdevice
selection line SDO (bit 12) are used so the "clear device flag"
instruction is

705041.

As seen from fig. 17, when the instruction "read flag status"
(Ions) is issued by the processor the state of the flag goes into
data line 17*. The flag status is thus read into bit 17'of the accumulator.

To check if the device is working properly the contents of the core

locations where the data is depoSited can be examined with the console
keys with the processor idle, or the program FIFO, given in the
Appendix, can be used. The contents of the first 100 (octal) locations
after the initial address are transferred to the teletype.. The data
is written in binary form as in the program and the transflar is done
bit by bit. If other words are desired to be printed it is only
necessary to change the instruction LAW 17700 into LAW K, where K is
equal to 17777 less than the number of words to be printed in octal.

As already mentioned, after each block transfer is complete

there is an interrupt, which needs to be serviced.

The device traps the API address 66 in bank 0 where there should
be a jump instruction to the service routine. If a Macro program
is being used the structure of the program should be as follows:

- Enable API (if not, the servicing will be very slow)

- Deposit in location 66 a "jump indirectly" to a subroutine that
services the interrupt, called the device handler.

* The LOPS instruction activates the Read Status line.

 157

- Main program
- Subroutines. One of the subroutines should be the device handler.

As location 66 is in bank 0 and the main program is in bank 2,

an intermediate location has to be used to link the JMS* instruction in
location 66 with the rest of the program in bank 2.

A typical example is :-

API LAC (40o 000

ENABLE APT
ISA

START LAC (10 000

DAC TEMP
LAC (OFLO OFLO is the first location of the
device handler
DAC* TEMP
LAC (66
DAC TEMP
LAC (JMS* 10 000
DAC* TEMP
A

Main program and subroutines

OFLO 0 the program counter is stored here

705041 Clear device flag
Device
DBR Debreak and restore API Handler
JMP* OFLO Return to the program
TEMP 0

.END

In this example the device hanlder clears the flag and returns
to the main program. But other requirements can be catered for, for
instance to increment the contents of some location each time an
interrupt occurs, allowing the data in the case to be related to the
instants at which it was sampled.
 158

If a FORTRAN program is being used, a subroutine which enables

API, deposits in location a a "jump to the device handler" and
includes the device handler should be run with the main program. One
of the first executable instructions of the main program should be a
"call to the device handler" subroutine. An example of a subroutine
which clears the flag and return the control to the main program is
given below for a subroutine called FIF01.

GLOBL FIF01
FIF01 0
API LAC (400 000
ISA
START LAC (10 000
DAC TEMP
LAC (OFLO
DAC* TEMP
LAC (66
DAC TEMP
LAC (JMS* 10 000
DAC* TEMP
JMP* FIF01
OFLO
705041
DBR
LIMP* OFLO

TEMP 0
0 END

In every case the FIFO device should only be enabled (using

the BCD switches) after the device handler is in the core. Otherwise
an TOPS error will result as the peripheral cannot be serviced.

When the D.O.S. system is used on the PDP 15 and the interrupt
is serviced in the same way by all users the device handler can be set
into the Monitor using the D05 GEN program.
 159

APPENDIX: EXAMELE PPOGPAM

PA0E 1 FIFO 30C

700401 A TSF=700401
700406 A TIS:700406
J0000 k 200057 START' LAC (0
00001 A 7 ; s LS
00009 a 777700 A LAW 1 7700
00003 n 04005,4 R DAC Cl
00004 R 200060 0 LAC (37777
60005 H 040056 DAC C4
00006 0 200036 33 LAC C4
00007 R 7/13;; A IAC
00010 A U4.;L:56 R DAC C4
00011 ii 200061 0 LAC (777756
0'0012 R 040055R DAC C9
00013 220056 R A2 LAC* C4
00014 k 740010 A RAL
00015 060056 0 DAC* C4
00016 k 741400 A SZL
00017 R 600025 R JN1P A4
00020 R 70j.101 A AS TSF
00021 0 600020 R JMP A5
00022 R 200062 R LAC (60
00023 0 700406 A TLS
00024 0 000031 R JMP AG
00025 R 700401 A A4 TSF
00026 600025 R JMP A4
00027 R 200063 R LAC (61
00030 0 700/106 4 TLS
00031 200055 0 AG LAC C2
00032 R 740030 A IAC
00033 R .040055 R DAC C2
00034 0 740200 A SZA
00035 ri 600013 0 JMP A2
00036 n 700401 A A7 TSF
00037 600036 R JMP A7
000/U n 200064 0 LAC (15
00041 R 700406 A TLS
00042 0 700401 A 48 TSF
00043 0 600042 R JMP AB
00044 0 200065 R LAC (12
00045 H 700406 A TLS
00046 0 200054 0 LAC Cl
00047 0 740030 A IAC
00050 0 040054 R DAC Cl
00051' 0 74020j A SZA
00052 0 600006 R JMP A3
00053 ii 740040 A HLT
00054 ii 000000 A Cl 0
00055 R 060;005 A C2 0
00056 0 000000 . A C4 0
000000 A .END
00057 0 000000 A *L
00060 0 037777 A *L
00061 0 777756 A *L
•

00062 0 00006.) A *L
00063 000061 A *L
00064 R 000015 A *L
00065 0 000012 A *L
SIZE=00066 NO ERROR LINES
 160

L ' A >------
Bit Line 37jnector 3.1170 210 N:'X(7N) 1."1:(IN) ::!-:. 3U3 I/O 21u;
,.
l.ie..a:::,r Cr:) (C1:T) ?Ir0 :i7:',Ilater CI;TrUT Dar:7:: of.. enr
00 1i' CO L B14 Ll A19 Ul 319 Al A14 H2 A14 32 Al4 E2 ;8 D2 A3 31
01 1N 01 L 314 J1 A19 V1 319 B1 Al4 D2 A14 V2 A14 32 A8 32 A3 D1
02 IN 02 L .:14 111 319 E2 319 C1 A14 N2 A14 P2 A14 R2 ..3 112 :,3 El
03 IN 03 L 314 El 319 D2 319 D1 A14 K2 A14 L2 :04 N2 A K2 A3 NI
04 1N 04 L 314 D1 319 E2 319 El A14 V2 A14 T2 A14 S2 A8 N2 A3 Ji
05 1N 05 L 314 B1 319 F2 319 Fl A14 S1 Al4 R1 A14 P1 A F2 A3 Li
06 IN 06 L 314 V2 319 H2 319 H1 A14 V1 A14 Ul A14 T1 A8 S2 A3 Ni
07 111 07 L 314 T2 319 J2 319 J1 A14 Fl A14 El A14 D1 AU V2 A3 PI
08 1N 08 L 314 S2 319 K2 B19 K1 Al4 Cl A14 B1 A11+ Al 38 D2 :s3 SI
09 IN 09 L 314 P2 319 L2 319 LI A15 H2 A15 F2 A15 E2 B8 E2 A3 D2
10 111 10 L 314 M2 319 X2 319 N1 A15 D2 Al5 V2 A15 32 38 112 A3 22
11 1N 11 L B14 K2 319 N2 B19 N1 A15 N2- A15 P2 A15 R2 38 K2 A3 112
12 1N 12 L 316 L2 819 P2 B19 D1 A15 K2 A15 L2 A15 N2 A9 D2 ::3 K2
13 1N 13 L B16 N2 319 22 319 21 A15 V2 A15 T2 A15 S2 A9 E2 A3 N2
14 iN 14 L 316 112 319 S2 B19 S1 A15 S1 A15 21 A15 P1 A9 112 A3 P2
15 1N 15 L 316 P2 BI9 T2 B19 T1 A15 F1 A15 V1 A15 T1 A9 1(2 A3 S2
16 1N 16 L 316 R2 B19 V2 319 V1 A15 V1 A15 E1 A15 D1 A9 1i2 A3 T2
17 1N 17 L 316 S2 B19 V2 B19 V1 A15 Cl A15 B1 A15 Al A9 P2 A3 V2

Table 1 Data paths from the line receivers (at level 5) to the
PDP 15 I/O BUS
 .16J

ADDIn;:.; ,:41:: Driver Eus D:dver II0 .3'.:5 ,D;_:::,

COUNTER in - out Cbl Lines
A19 32 LI7 31 A17 D? 33 Hi 03 L
A19 D2 A17 D1 A17 E2 B3 J1 04 L
A19 E2 A17 F1 A17 H2 B3 L1 05 L
-2
A19 2 ,,17 J1 :07 K2 B3 1.:1 0 L
A19 112 A17 LI A17 X2 • B3 P1 07 L
A19 J2 A17 N1 A17 ,P2 33 S1 03 L
A19 N2 A17 RI A17 S2 B3 D2 09 L
A19 L2 L17 U1 A17 V2 B3 E2 10 L
A19 +:2 B17 31 317 D2 33 H2 11 - L
A19 H2 317 D1 B17 E2 B3 1:2 12 L
A19 P2 B17 Fl B17 112 B3 M2 13 L
A19 R2 B17 J1 B17 K2 B3 P2 14 L
A19 S2 B17 L1 B17 M2 B3 S2 15 L
A19 T2 B17 N1 B17 P2 B3 T2 16 L
A19 U2 317 31 R17 S2 33 V? 17 1
DCH RQL B17 U1 B17 V2 A4 S2 Single
B18 J2 B17 V1 Cycle
Request
L
DCH RRL B9 N1 B9 P2 B4 S2 Data
B18 J2 29 P1 Channel
Reouest
L

Table 2 Address and Data, Channel Bus connections.

 162

NOVA I/O BUS

A

DATA NOVA CLOCK

DATO A

LEVEL 8

LINE DRIVERS

100 WAY CABLE •

LINE RECEIVERS
---1

DATA NOVA CLOCK

LEVEL 5
FIFO STORE AND
CONTROL LOGIC
FOR SINGLE CYCLE
DATA CHANNEL D.M.A.

DATA CONTROL

PDP-15 I/O BUS

Fig. 1 Block diagram of the transfer of data from the NOVA •

to the PDP-15.
 1G3

PDP-151/0 BUS

DATA
L INE FIFO DATA S
laW212./ DRIVERS DATA
STORE MPX / DRIVERS
Noi.a
P DUMP
SELECT] SEI. ECT ENA BLE
SWITCH
*PS SWITCH
./.TM
13LOCK MPXF
BCD SWITCHES' ANTICIPATE
& SHAPE IFELF_c-r
SW ICH
F7.5713 N.',RY PS. SIM UL Al OR

ENABLE
COMPARATOR IF
SHAPE
•■•••■■•■••■■•,

1 5 13.I 6/1 .1■•■••■■

1:NFIsc2(.3
DMA CHANNEL
DATA CHANNEL
BLOCK LENGTH GRANT ENABLE
DA1 A
UPCOUNTER CHANNEL
FL AG
I
SINGLE CYCLE
CONTROL LOGIC
(M 104 MULTIPLEXER

I IMAD
13 _ C.J-f r:
[DOWN CO'.:N

CFL.0 EL/ upy

L ETEC REGISTER -
.,,OH
C API I
LONE D!::.TECT7.7:,
BURST/ 1PS CONT._A PI
LOGIC cL.0INNEIrt.
F■N'EUStliTAELR

No. OF BLOCKS FROG.

INT ERR. sT,til)
BCD SVIITCI ES LOGIC
LINES

\'ARY INIT ADDRESS

COMPLEMEN1 ADDRE.- &
S SSABI Ft'- v.
:7,-TT
I/O BUS 1: :=71: 1,1m,

- ,COUNTER FL
) LAY f LOGIC LINES
AD ■.."
OF No. OF
BLOCKS ADDRE:SS
DOWN
COUNTER
ADDRESS
BUS
FDRIVERS

ENA BLE

Fig.2 Detailed functional diagram of the FIFO unit



161

NOVA CLOCK—FIFO PULSE LOAD

CR A19R1
DM 6E:20
PAIR No.38 LINE RECIEVER
CL P.S.SIMULATCR INTERRUPT— OFLO FLAG MP
0
A14M1

ENABLE DATA BUS DRIVERS,

DATA, AND OFLO FLAG
A14J1,A15J1 MULTIPLEXERS SELECT -

0
•5V

Fig.3: Functions of the double way switch on the front of the FIFO unit

16 15 14 13 12 11 10
All multiplexers with strobe low (enabled)
Vcc
.
Low select enables A inputs.
0
STROBE 4A 4B 4Y 3A 38

SELECT • 3Y

1A 1B 1Y 2A 2B 2Y

GRD

1 8

Fig. 4.- Pin connections of the 4 two -input multiplexers SN74157

+5V regulated Farnel Board 1-12 (fully loaded)

+5V regulated Kingshill Boards 14-20 (spare capacity) Bigger LED lamp
on panel.

-12V unregulated kingshill Board 19 (A1951) Smaller LED lamp on panel.

Fig.5: Power Supplies Connections. Power supplies are located on PDP -15 rear door
housing FIFO unit.
 CO

3
DO

D1 9 BIT 9 BIT 9 BIT 9 BIT

(P REGISTER REGISTER REGISTER REGISTER
0 1 30 31 07
D7
0 08
D8 STROBE STROBE STROBE STROBE
‘r MR

co

r-
0
<CI

PULSE PULSE
S 0 S a a PD
LOAD PL CONTROL CONTROL DUMP
Co Cl C30 C31
LOGIC LOGIC
INPUT
R ' 0 O R a L G 0-
OUTPUT
OR
READY IR MR READY
MR MR MR
U

MASTER RESET MR
 166

(319V1

OB 07 Ei19U1
08 07
GROUND 06 131971
VDD 06 VDD
819V2 05 81951
Da 05 D8
PL 04 81981
PL 04
FLAG OE FLAG OE
1319V2 D7 (319 P1
D7 03
131912 DG 023 sls 06 02 131.9N1
05 AM2813 0 AM2813
BIOS 2 D5 Q1 B19M1
01
1319112 D4 00 B19 L1
04 00
.5V Vss Vss
PD PD
IR MR IR MR
B19P 2 D3 OR
03 OR
B19N2 VGG -12V •A19 S1
D2 VGG D2
819 M2 D1
D1 DO DO

819L2

619K1
B19 J1
GROUND F3191-11
I319 K 2 B19 F1
1319E1

B19J2 131901
819H2 AM 2813 AM 2613 1319 C1
819F2 81981
1319E2 B19A1
•5V

81902
81902 -12V A19 S1
A19V1

Al 9 U1

PULSE LOAD PL
A19R1
.5V 161(0
NOVA CLOCK Wr----IFI
o-i
B14M1 ,,, 11 ji
SELECT°S'VITCH ." r
1:i"
Al
250 E21
PWR CLR L —.- A19 H1 1 n5 r 14 74121
550
■ A6V2 .5v_ _, 1Aka
y
5•B‘2 _ F FIFO RESET
ioka 4 7pF 3.9 krz 50pF
•

150 ms
PULSE DUMP
A2 4 A2 0
CARD 10
350
-1_ E12
74121
PD
74121
DCH GR ms AIGE2 5
A16K 2

lk
5V —VA

Fig.7: FIFO layout and control pulses.


PS1/ •51,
NOVA Cl. 00X
EA,. A • 21P•1

SW T6)
U. j r k
.5v .5V 3CW ,011 1, •

311

EP.?
E•
E? T :ocns
E9 to 7,61 EPP?.
7416?

" LD
CLR CLR
5
0.

3,K
311 R
I•P PP3 PI
A, A, A ) A, At A 1
(3
748S 7465
Ak? •
s (39 0, 2. O. Os ('3
•
DP0'
eZ0

TC>o •7 •
15 Ezo•

T410
7404
7430 S.SPEO
5W714
IN IIZIT

• 7474

(I EA 3k i
74,84 74164 Pi,•: s.„1, E ,..7: Pt
• S.121 1^ T

A s'r 0 I

o •P
k'CA LL S.,TPt A •

I P.? Ii PAP /en,;(/) Low,to- Ce,.tro,

 168

• *-1'.--x4

:';:Z*Fit•Ktrarr
eancAtr;Ipaisr..:-
vt

Fig. 9: Front view of the Unit

 169

5p.s

I/O SYNC H

DCH FLAG

SING CY RQL

DCH RQ L

DCH GR H

BURST MODE

NORMAL MODE
7
_50
CLEAR FLAG L ns

DCH ENA

CHANGE ADDRESS

4_350
ANTICiFATE DCH GR ns
FALLING EDGE

414_ ni 5s0 \\F

CHANGE DATA PD
(PULSE DUMP)

Fig. 10: Single cycle burst mode timing for an input transfer to the computer with the
block length set to 4 (four transfers per burst


170

BCD SWITCH INPUTS •5V

NUMBER OF BLOCKS
2.2k I 1
MSB B20 S1
o>
B20U1
MSD B2CP1
B20M1

B20K1
B2OH1
LSD B20E1
LSB B20C1

+5V
14 13 '2 11 10
E16
74184
2.

5 3 2
9 11
E
12 25 0
13 E13
14 13 12 11 10 6
El7
E21 3
74184 2\E
4 X25
4 3 2

DCH REO A2C\11-A19F1

BLOCK LENGTH COUNTER

DCH REO E15 -12
B20R1-.-A19D1
, 11/ 9 1C 1 15
•...L,- Z19 10 1 15
,BLOCK 4 LDCE3 A LD'BA
:TRANSFER_r-c EN RC 13 EN
Ele E23 -
COMF'LE I-E -=14
.CK 74191 >Cf: 74191
E17-11
12 12 11
5 DOWN DOWN

.5V B20V1
4 6 A19C1 1 El°
El 7 7404
-. E25
DELAY CO:7.F

Fig. 11: Number of blocks counter located on board AlB20.

 171

BLOCK LENGTH AFTER

BCD / BINARY CONVERSION

E1-4

MSD
r i-3
E1-2

E1 -1
-2
LSD EF.
6-1
EB-1

B20F1-.-A1S01

11 15 1 10 9 11 15 1 10 19
_L2114117ABCD 1 A BC ID
.E.N
E19 20 EN
E24
74191 74191

4 12 4 MAX 12
CK MAX MIN C
MIN
OA CB OCCD 11 RAISE Of LO F L4.3
3 2 7 6 1 B2081 Al4L1

12 11 BLOCK TPANSFER
13 E17
CON1F-LETE

A20A1-.A19A1 1 E5
74 04
DELAY 60ns
110
9 E16

10 E17

1kr), 5V

4 E13
6 13>012 PENULTM L
2 1E20
B2001 --A19M1

DCII ENA H-A1692 10 AIESP2

1376p 8 A16N2-
)-- IA1"N2 M602 A10L2-,-A19N1
eCll GR L Al 6 P2 c..; fA31:1,12
A1GJ2

Fig. 12: Block length down counter located on board 820.

 172
H
n
-.HTO BUS DRIVERS
CARRY
E'
—D OD
E6 A1932 A1751
C
74193
A19D2 A17D1
^ OB
A19 E 2 A 1 7 El
A OA

0 L DOWN UP

•5V

n
E2
CARRY
A19F2 A17J1
OD
AA E 7 A19 H2 A1711
74193 OC
---4/1V----
A19J2 A17/41
OB
'---MiN
A19X2 A17R1 •
OA
L DOWN UP

•5V

0 rHP
CARRY
E3 A19L2 A17U1
OD
E8 A19M 2 B17°1
OC
—VA 74193
A19N2 01701
OB
_......w,..._______
A19P2
A QA
I DOWN UP

.5V

12 n 1 4
CARRY
E4
7 A19R2 B17J1
OD
E9 A19S2 B17L1
0 ac
74193
--Wr
A19T2 B17N1
00
—VW- A 1 9 U 2 81 7 R1
15 A OA
2-21:Q
—W,, 11
C. L DOWN - UP
4

11

E16
12 13

V)
11)
8
0 E 0
74 04
DELAY
60ms
MR CL R L-A 19 C 1

x
U

cc Y212
wow
zej›- 0

•-00 (21

Fig. 13: Address counter located on board A/B19

 173

Fig. 14 : FIFO chips, control logic and address counter

on board VP 19
 • V 4 •
Fig. 15 :

DCH REQH
DCH EN OUT H
DCH EN IN H B1542 B18M2 —B4V12
B2V2
Singlecycl edat achannel ( DCII) t r ansfer control l ogic .

I/O SYNC H --.818H11)0_1>0 DCH ENA L

•
B7H1 61851
DCH ENAH
Bl F1

O DCH a
0R ENA S

DCH GRL A16J2

DCH GR H A16V2 DCH GR H A16 K2 B1 7U1
0 M B17V2—SING CYROL
B212 131V1
100ms 522 A452

PA

10Ons B9P2 --.DCH ROL

OCH RQ
—1 B 452
PWR CLR H 818J2
DCH a
A6V1 R
REQ
DCH ENINL

M A18F2 CLR ROL B1BS2-•—A19E1

RWRCLRL-•-A18K2 002 B18F2
o
A5V2

.5V
9
A18F2 A19P1 13 ER° E)10
DCH
C R FLAG S
C E
11 F2 .3V
24k VAr-
jvvv_r_i ILID
NORMAL H— A151.2 5 .5V
E16 3 A15H2 A18H2,A18J2 110
5 t E13
CI 17ns
PWR CLR L A19H1 1 BURST 4 74121
R E11 SO-- A2
ASV2 CNORMAL

I/O SYNC H —A19K1 A16M2 DCH ENA H

Bli3H1 g1LIP1

J—LOOns
Al9M1..-- PENULTM L A19F1 ---A20M1
620 D1
Transfer of block into FIFO complete
 175

Al2H2 OFLO FLAG (1)H

B7S2

CLR FLAG H
A10K1-A1232
A7 N1

D R
OFLO FLAG
Al2F2---.438P1
B8P2-PROG INT REO L
A4 L1

Al2D2-.-A14N1

NOVA
CLOCK

PS SIMULATOR SELECT
INT IN H
B14 M1 B8S2 REO L
1A14M1 B8S1 A4J1
BLOCK TRANSFER MPX
COMPLETE. A14L1
•B2OB1
SELECT
SWITCH
API REQ(1)
B7U2
IOT SKIP L-- B8R1
B10C1

B8V1
88V2-I/0 BUS 17L
RD STATUS H- 85U1 B5V2-B8U1
A2P1 A3V2

Fig. 16: Status, Skip, and Interrupt.

 176

•5V

B7K2 £5V
ti lit
API OEN IN H
API OEN OUT H
B2L1-B7H 2 T B7M2-04L1

B9B1
I/0 ADDR 12L
133. B9D2-B3K2
D1
I/O ;-.DDR 13L
API ENA(1) L
BgE2 B31,42
B7 S1
J1
0 I/0 ADDR 15L
API B9K2 -63S2
C
R ENA
I/O
SYNCH H C D L1
100ns IIC ArDR'16L
-,F1 SYNC.PH
B6S2 B6R1 B7H1 69M2 133T2

API 2
GRH
B 2J1 CRA'IT H
B6U1 B6V1-- PAD-

API REQ (1) L

100nsy B7J 2 API REQ (1)H
PWR CLR L
I/O PV/ AGV2
CLR H
PWR CLR H API
A2S1--
A6U1 A 6V1-- B7N1 R REQ A9S1
API OPO L
A9 R1
A9S2 - 64H1
API OEN IN L
CLR L
A7K1-B7F 2

FLAG (1) H
Al2H2-87S2

Fig. 17 : API
 ;

177

SDL B5S1-o- B10B1

SDO H
A2T2---o-85S2
SDH B5R1 A7H1 CLR RQ L
A7K1 --o- B7F2
A7K1 A7L1
CLR FLAG H
PWR CLR L
A6V2 --o- A7M1 A7N1---..A10J1
A7A1-o- A7J1

DSO H
A2D 2 --o- B5D2 B5C1-o-A7D2
B5H1-o- A7E2
DS1 H
A2E2-o- B5H2
DS2 H
B5J1-o- A7F2
A2H2-o-B5K2
B5M1-A7H2
DS3 H
A2K2.--.--B5M2 >7A1_,:- 10T SKIP L
i
B5P1 A7J2 B1OC1-.-B8R1
DS4 H 810A1
A2M2-. B5P2
B5T2 -o- A7K2 10T READ L
DS5 H
A2P2 -o- B5R2 —D0 A7D1-.- Al5M1
B8L1
B8M1
10T WRITE H
A7E1--o- B12N12
10P1 H
A2D1-.-A5D2 A5 C1-A7P 2

10P2 H
A5F1-A7R2
A 2E1 -o-A5H 2

10P4 H
A5J1-,-A7S2
A2H1-- A5K2

Fig.18: Device selection

 178

MULTIPLEXERS BUS DRIVERS I/O BUS

A14E2
dlA8D2—+ A3B1 I/O BUS OOL

A14 B2

o
A8E 2 A 3D1 I /OBUS 01L

A14R 2

A14M 2
D A8H2 —.- A3 E1 I /OBUS 02L

A8K2 A 3 H1 I/O BUS 03 L

A1452
A8M 2 A3J1 I/O BUS 04L

A14P1
A 8 P2 A3 L1 I/O BUS 05L

A14T1
A8S2 A3M1 I/ 0 BUS 06L

A14 D1
A8V2 A 3P1 I/O BUS 07L

A14 A1
B8D2 A 3 S1 I/O BUS 08L

A15E2
B8E2 A 3 D 2 I /0BUS 09L

A15B 2
B8H 2 — A3E2 I/O BUS 10L

A15R 2
B8K 2 A3 H2 I/O BUS 11L

A15M 2
A9D2 A3K 2 I/O BUS 12L

Al5S 2
A9E 2 A3M 2 I/O BUS 13L

A15P1
A9H 2 -- A3P 2 I/O BUS 14L

A15T1
A9 K 2 A 3S2 I/O BUS 15L

A15D1
A3T2 I/O BUS 16L

A15A1
A9 P2 A3V 2 I/O BUS 17L

A16U2
DCH ENA H 13 11 A16 S2
3
A15 L1 —4>°-
I318P1 12 o A15 N1
A16T2 A15M1 IMPX
SELECT SWITCH
—C>c)-

P. S. SIMULATOR
I38L1
I OT READ L B8M2 -- A4 M1 RD RO L
A7 D 1 0
B8M1

Fig.19: Data bus drivers connections.

 179

A19B2 —.A17131
A17D2 — B3 I/O AMR 03L

A19D2 — A17D1 4
A17E2 63 I/O ADDR.
I

A19E2 — A17F1
B3 I/O ADDR OSL

A19F2 — A17J1
c A17K 2 — B3 I/O ADDR COL

A19H2 — A17L1
A17M2 B3 I/O ADDR 07L

A19J2 — A17N1
c A17P2 B3 I/ 0 ADDR OSL
c
A19K2 —,-A17R1
< A17S2 63 1/0 ADDR
c
A19L 2 ---.- A17U1
c A17V2 B3 I/O ADDR
c
A19M2 -- B1731
c B17D2 B3 I/O ADDR
c
A19N2 —.- 617D1
c 317E2 B3 I/O ADDR
c
A19P2 —,- B17F1
c B17H2 63I /0 ADDR
c
A19R2 ---. B17J1
B17K2 —•- 133110 ADDR
c
A19S2 —.- B17L1
c 617M2 B3 I/0 ADDR
C

A19T2 — B17N1
c B17P2 —0- B3 I /0 ADDR
0
A19U2 --.- B17R1
B17S2 -- B3 I/O ADDR
°

DCH ENA L A17C1

618S1

Fig. 20: Address bus drivers connections.

 1 80

100 47pF
+5 V I

■
•■■•■■■■

74121
A2
350
ns A16E2 A19V2

Al 6N2—A18 N 2
10 9

7400

B18P1 wA16M2 4 5
Al 6 H2— Al 8H2
A19J1—A16L2

+5V

100 kC)

I/O BUS DC HGRL A16J2

1000
DCH GR --A16N/2 BC109
B 2T2 DCH GRH A16K2

13 12 10

7404
1.852

Fig.21: Board A16

 191

LOWER RACK
16 15 14 13 12 11 10 9 B. 7 6 5 4 3 2

cv
0) O O cv
0) r. O
0) 0) (3, lJ In In
2

rn
rn
cn

O O Cr) O
0) 0
0) C) C) L7
_

UPPER RACK I/O BUS CONNECTORS

20 19 18 17

0)

O cv
CD

Fig.22: Module Locations

Cards 1-12 are common to the P.S. simulator. The line receivers
which are adjacent to the lower rack are also common to
both units.
 182

M 103 Device Select5r (slot A7)

H 104 A'I Multinler (Slot 37)
la 104 Single Clcle Dcii Multiplexer with Buffering (Slot B18)
m 111 16 inverters (Slot A10)
M 113 10 2-i ::"'alt N:.ad Gates (Slot B10)
M 216 6 D-Flin-Flors (Slots A115 11)
M 510 110 :=;Q:7; Reccivers (Slots A13 and A136)
H 602 Dual Pulse Generator (Slot A18)
11 622 110 ase Drivers- (Slots A1B 8 and A13 9
1.1 934 Cable Connector (Slots B14 and 315)
W 941 FiFo clirs, ,dress Counter and Flg Registers (Slot A1B 19)
W 1 ;ngth Up and Down Counters, Counter of
Block I.,
Number of Blocks and Enabling of DOH Request (Slot A1B 20)
111 970 Data Multinlexers (Slot A14)
W 970 Data Multiplexers with buffering (Slot A15)

W 999 12 D Flip-Flo?s (Slots A1B 12)

w 999/2 Bus Receiver, Buffers and 4 Nand Gates (Slot A16)

W 999/2 Cable Connector (slot BIG)

Fig 23 Module Functions

 183

REFERENCES

1. IEEE Proceedings "Computers in Power Industry" , June 1974 .

2. Savulescu, .C. "Computerized operation of power systems"

Proceedings of Symposium , Sao Carlos, Brazil, August 1975.

3. Dopazo, J. and Sasson, .M. "The AEP real—time monitoring

computer system" Symposium on Implementation of Real—Time

Control by Digital Computer, Imperial College, London, September 1973.

4. Crook,D.W.E. and Harris,J.H. "The use of on—line computing

facilit)es at the national control centre of the C.E.G.B.", ibid.

5. Becker, G. "Processing computer for load dispatching experiences

with an on—line system" , ibid.

6. Kano, K. "Automatic load dispatching system in Kansai Electric

Co. Inc." , ibid.

7. Di Liacco, T.E. "E periences in the design, implementation and

operating performance of the Cleveland System Operation Center", ibid.

8. Johanson, D.E. "Operation experience with the Dittmer on—line

control center, Boneville Power Administration" , ibid .

9. Hetch, H. and Granberg, B. "The use of on—line minicomputers

in Swedish municipal power distribution systems" , ibid.

 184

10. Wimmel, K.H. and Zollenforf, K. "Experience in the use of

an on-line digital computer for switching a 380/11CkV system, ibid.

11. Stagg, G.W. "Southern Services System" , ibid.

12. Clark, B.J. "The processing of generation and transmission

protection system alarms by computer" , IEE Conference on

developments in power system protection, Conference publication

No. 125, March 1975.

13. Patterson, D. "Application of a computerised alarm-analysis

system to a nuclear power station", Proc. IEE Vol. No.115,

December 1968.

14. Allison, P.B. and Lomas, T.H. "The application of a microprocessor

system to automatic switching and reclosing on power supply

networks" , IEE Conference on developments in power system protection,

Conference publication No. 125, March 1975
15. Righezza, P., Abella, R., and Paverd, M. "Substations tele-

controlled and automated by means of standard data processing

equipment" CIGRE Paper No. 34-01 , August 1976.

16. Rockefeller, G.D. "Fault protection with digital computer"

IEEE Transactions Vol. PAS-88, No. 4, April 1969.

17. Cory, B.J. and Moont, J.F. "Application of digital computers

to busbar protection" , IEE Conference Bournemouth 1970.

18. Ranjbar, A. and Cory, B.J. "Algorithms for distance protection"

IEE Conference on developments in power systems protection,

Conference publication No. 125, March 1975.

 185

19. Man, B.J. and Morrison, I.F. "Digital calculation of impedance

for transmission line protection" , IEEE transactions Vol. PAS-90 ,

No. 1, January/February 1971.

20. Slemon, G.R. and Robertson, S.D.T. and Ramamoorty, M. "High

speed protection of power systems based on improved models"

CIGRE Paper 31-C91 1968.

21. Mc Innes, B.E. and Morrison, I.F. "Real time calculations of

resistance and reactance for transmission line protection by

digital computer", IEA Australia , March 1971

22. Sykes, J.A. and Morrison, I.F. "A proposed method of harmonic

restraint differential protection CT traisformers by digital

computer" , IEEE Summer Power Meeting, Portland, Oregon, paper

No. 71, July 1971.

23. Cheetam, W.J. "Computerised protection or not ? - Primary and

back-up protection" , IEE Conference on developments in power

system protection , March 1975.

24. Cory, B.J and Dromey, G. and Murray, B. "Digital techniques

in protection" , CIGRE Paper No. 34-C8, August 1968.

25. Edgley, R.K. "Back-up protection and overal protection of power

systems networks" , Electra Do. 34, August 1974.

26. Quazza, G. "Highlights on technological trends in the on-line

optimisation of power system operation" , IEE Conference On-line

Operation and Optimisation of Transmission and Distribution

Systems, June 1976.

 186
27. Di Liacco, T.E. "The adaptative reliability control system",

IEEE Transactions Vol. PAS-86, No. 5, May 1967.

28. Kirchmayer, L.K. and Ewart, D.N. "Automation and utility system

security" , IEEE Spectrum, Vol. 8, No. 7, July 1971.

29. Murray, B. and Hughes, G• "An approach to on—line substation

control" PSCC, Grenoble 1972.

30. Dromey, Q. and Rasmussen, J.P. "Integrated control concepts

in power systems" , CIGRE Conference August 1974.

31. Murray, B.E. and Dromey, G. "Practical design considerations

affecting the use of digital computers in high voltage substations" ,

IFAC Conference, Zurich 1974.

32. Luckett, B.G., Munday, P.G. and Murray, B.E. "A substation

based computer for control and protection" , IEE Conference

on developments in power system protection, March 1975.

33. Horne, E. and Cory, B.J. "Digital processors for substation

switching and control", ibid.

34. Gonzalez, G.E. "Relaying data validation" , Digital Protection

of Power Systems Post—Experience Course, Imperial College, London,

March 1975.

35. Ong, P.K.S. "Digital protection of transformers", M.Sc. Thesis

Imperial College, 1974.

36. Miniesey, S. "Power system report No. 94", Imperal College,

London, 1973.
 187

37. Lau, W. "M.Sc. Thesis", Imperial College, 1973

38. Warrington, A.R. "Protective relays - their theory and practice"

Vol. 1 and Vol. 2, Chapman and Hall, London

39. Schoeffler, J. and Temple, R.H. "Minicomputers hardware, software

and applications", IEEE Press, 1972

40. Peatman, J.B. "The design of digital systems", McGraw-Hill, 1972.

41. Harvey, S.M. and Ponke, W.J. "Electromagnetic shielding of a

system computer in a 230kV substation", IEEE Transactions

Vol. PAS-95, No. 1, January/February 1976._

42. Vallo, D. and Thuot, M.E. "High power laboratory testing with

a real-time computer ; a new generation of testing methods"

IEEE Transactions Vol. PAS-95, No. 1, May/June 1976.

43. Lomas, T. "Digital equipment in electrical hostile environment",

Digital protection of power systems, Post-Experience Course,

Imperial College, London, June 1976.

44. Bakker, J.K. "Planning for tomorrow's power systems", Energy

Internacional, February 1975, Vol. 12, No. '2.

45. Greco, L.S. and Jones J.L. "An integrated system for EHV

substations" , IEEE Canadian Communication and Power Conference

Montreal 1974.

46. Vaidya, V. and Mukhedar, D. "Control systems for large electrical

networks", ibid.
 169

47. Couch, G.H. and Morrison, I.F. "Data validation and topology

determination for power systems monitoring and control",

IEEE Summer Power Meeting , July 1974.

46. Traca, A.T.C. "Substation switching", Digital Protection of

Power Systems, Post—Experience Course, Imperial College,

London, 1976.

49. Hutchinson, G.P. "Interlocking in large electricity supply

substations" , Proceedings of IEE, Vol. 113, No. 6, June 1966.

50. Cory, B.J. "An approach by moans of mathmatical logic to the

switching of power systems metworks", Proceedings of IEE, Vol.110,

No. 1, January 1963.

51. Hope, G.S. and Cory, B.J. "Development of digital computer

programs for the automatic switching of power systems networks",

IEEE Transactions Vol. PAS-87, July 1968.

52. Row, C.T. and Cory, B.J. "Substation interlocking and switching

with a small digital computer", IEE Conference Computers in

Power System Operation and Control, Bournemouth, 1972.

53. Couch, G.H. and Morrison, I.F. "Substation interlocking using

a digital computer", IEEE Winter Power Meeting, New—York,

January/February 1971.

54. Couch, G.H. and Morrison, I.F. "Substation switching — an

approach to the determination of optimal sequences", IEEE

Winter Power Meeting, New—York, January/February 1972.

55. Udo, M. "Optimum changeover switching of-power system networks",

PSCC Grenoble, September 1972.

56. Giles, R.L. "Layout of EIIV Substations" IEE Monograph Series.

57. LythallI R.T. "J&P Switchgear Book", Newnes-Butterworth

55. Texas Instruments "TTL Data Book"_

59. RCA "Solid State Power Circuits"

60. Advance Microdevices " First-In First-Out Application rotes"

61. Data General Corporaticn "NOVA System Reference Manual"

62. Digtal Equipment Corporation "PDP-15 Interface Manual"

63. Idem "I6gic Handbook"

64. Idem "PDP-15 Reference Manual"

65. Idem "PDR-15 DOS User's Manual"

66. Idem "PDP-15 LCSGEN Manual"

67.Matsuoka, T. and Tsuboi, A. "The discriminative logic of fault

elements for a centralized back-up protection in power circuits"

IFAC . Melbourne , 21-25 February 1977

68.Sasson, M. "Decomposition techniques applied to the non-linear

programming load-flow method" IEEE Trans.,Vol. PAS-89, January 1970