Chapter 4

8051 Family Microcontrollers

Instruction Set
 Lesson 3

Data Transfer Instructions

 Move byte between
accumulator (an SFR) and
register at a register bank

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 MOV Rn, A

Destination Source

Rn A

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 MOV A, Rn

Source
Destination

A Rn

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 MOV A, Rn; MOV Rn, A
A Rn
R7
Bank 3
R6
8051 Bank 2
R5
Bank 1 R4
Bank 0 R3
R2
R1
R0

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 Rn
Rn: n = 0,1, 2, 3,4, 5, 6,or 7,
n is as per 3 bits coexisting with
5-bits with opcode
Register n is at the bank defined by
RS1 and RS0 at PSW
- 00 means Bank 0, -01 bank 1
- 10 bank 2- 11 bank 3

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 Instruction Execution 1 clock
Fetch cycle
STEP 1 opcode-bits
STEP 2 Fetch bits
for getting the Time
operand(s)
Register addressing mode

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Move byte from an SFR/Internal RAM
to another direct

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 MOV A, direct; MOV Rn, direct;
MOV direct, A; MOV direct, Rn

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 An SFR or Internal RAM between
00H-7FH

Source
Destination

direct A or Rn

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 A or Rn

Bank 3
8051 Bank 2
Bank 1 Direct addressed
Bank 0 SFR 80H-FFH or
Internal RAM
between 00H-
7FH
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 An SFR or Internal RAM between
00H-7FH

Source
Destination

A or Rn direct

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 Instruction Execution 1 clock
Fetch cycle
STEP 1 opcode-bits
STEP 2 Fetch direct Time

direct addressing mode

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 MOV direct, direct

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 MOV direct, direct
direct direct

Direct
8051 addressed Direct
SFR or addressed SFR
Internal or Internal
RAM RAM between
between 00H-7FH
00H-7FH
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 Instruction Execution 2 clock
STEP 1 Fetch cycles
opcode-bits
STEP 2 Fetch direct
Time
STEP 3 Fetch direct
both the operands using direct addressing
modes

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 Move indirect

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 MOV A, @Ri;
MOV @Ri, A;
MOV direct, @Ri;
MOV @Ri, direct

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 An indirect addressed Internal
RAM between 00H-FFH

Source
Destination

A or direct Address
pointed by
R0 or R1

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 indirect A or direct

8051 Indirect
SFR direct
addressed
addressed
Internal
between 80H-
RAM
8FH or A
between
register
00H-FFH

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 An indirect Internal RAM
between 00H-FFH

Source
Destination

Address A or direct
pointed
by R0 or
R1
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 A or direct
4 R0 or R1

Bank 3 1
8051 2 3
Bank 2
Bank 1
Pointed address
Bank 0
Internal RAM
between 00H-
FFH
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 Instruction Execution 1 or 2
Fetch clock
STEP 1 opcode-bits cycle(s)

STEP 2 Fetch bits for A

or direct

STEP 3 Fetch bit for i 0

or 1 Time
indirect addressing mode one operand
2 cycles when direct, 1 when A other operand
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 Instruction Execution
1. No indirect addressing in 8051
instruction for an SFR
2. Only indirect addressing in 8052
instruction Internal RAM between
80H-FFH

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 Move immediate,
MOV immediate DPTR

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 A byte

2nd Byte of
A register
instruction

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 MOV A,#data Example 1 clock
Fetch opcode cycle
For moving
and then byte
08H into A
for getting the Time
register
operand for
move
MOV A, #08H
Codes in
Sign # specifies that 08H is
Memory-
the immediate succeeding
74H, 08H
byte is the operand
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 Rn byte

8051 Rn (R0 or
R1 or ...R6
2nd Byte of
or R7) at
instruction
Bank 0 or
1or 2 or 3

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 MOV Rn,#data 1 clock
Fetch opcode cycle
For moving
and then byte
08H into Rn
for getting the Time
register
operand for
move
MOV Rn, #08H
Codes in
Sign # specifies that 08H is Memory-
the immediate succeeding 78H-7FH,
byte is the operand
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08H 30
 direct byte

direct
8051 address
internal
2nd Byte of
RAM 00H-
instruction
7FH or
SFR 80H-
FFH
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 MOV direct,#data 2 clock
Fetch opcode and cycles
For moving then bytes
08H into direct for getting the
operands Time

Codes in
MOV direct, #08H
Memory-
75H, 00H-
Sign # specifies that 08H is the
FFH, 08H
immediate succeeding byte is the
operand
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 Destination Direct Addressing clock
Fetch byte(s) cycle (s)
STEP 2
after the
opcode Time
Addressing mode specifies that fetch
byte(s) (next to the opcode of 8 bits)
specify an address, destination operand is
at that address.

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 indirect byte

indirect
8051 address
internal
2nd Byte of
RAM 00H-
instruction
FFH
pointed by
R0 or R1
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 MOV @Ri,#data 1 clock
For moving Fetch opcode cycle
08H into and then bits
indirect for getting the Time
operands

MOV @Ri, #08H Codes in

Memory-
76-77H,
Sign # specifies that 08H is 08H
the immediate succeeding
byte is the operand
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 Destination indirect
Addressing 1 clock
STEP 2 Fetch bit 0 or cycle
1 for R0 or R1
the opcode Time

Addressing mode specifies that fetch

byte(s) specify by an address pointed by
R0 or R1 at a bank

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 Immediate Addressing Four type of
instructions
• A
• Rn
• direct for Internal RAM in between
00H to 7FH or direct for SFR 80H-
FFH
• Indirect using R0 or R1

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 Immediate addressing mode for
source two-bytes

• Lower byte is second byte of the

instruction and is for DPL
• Higher byte is third byte of the
instruction and is for DPH

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 MOV DPTR, #data16 2 clock
Fetch opcode cycles
For moving
and then 16
08C1H into
bits for getting Time
DPTR
the operands
Codes in
MOV DPTR, #08C1H
Memory-
90H, C1H,
Sign # specifies that 08C1H is
08H
two immediate succeeding
bytes
2011
as the operand
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 MOVC and MOVX indirect

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 1. Only indirect addressing in 8051
instruction for a byte in external data
memory

2. Only indirect addressing in 8051

instruction for a code in internal/external
program memory

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 Always Indirect Addressing mode
Internal/External
Program Memory
(max. 64kB)

External Data Memory

and Ports (max 64kB)

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 MOVC A, @A + PC 2 clock
For Fetch opcode cycles
transferring bits
addressed C means code
code byte Time
memory is used
into A STEPS 2-3
MOVC A, @A + PC Code bits in
Memory-
indirectly specify, PC16-bits adds
with 8-bits at A register and then 83H
new 16-bits point to the code at
that
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address Microcontrollers-... 2nd Ed. Raj Kamal 43
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 MOVC A, @A + DPTR 2 clock
For cycles
transferring Fetch opcode
addressed
bits Time
code byte
into A STEPS 2-3
MOVC A, @A + DPTR Code bits in
Memory-
indirectly specify, DPTR16-bits
adds in 8-bits at A register and 93H
then 16-bits point to code at that C means code
address
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 MOVX A, @DPTR 2 clock
For cycles
Fetch opcode
transferring Sign @ means
an external DPTR is a
byte into A pointer Time
STEP 2
MOVX A, @DPTR Code bits in
X specifies external memory, Memory-
byte at DPTR points indirectly E0H
to the address for the operand
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 MOVX @DPTR, A 2 clock
For
Fetch opcode cycles
transferring A
to a byte at Sign @ means
external DPTR is a pointer Time
pointed address
STEP 2
MOVX @DPTR, A Code bits in
X specifies external memory, Memory-
byte at DPTR points indirectly F0H
to the address for the operand
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 MOVX A, @Ri 2 clock
For cycles
Fetch opcode
transferring an
external byte Sign @ means Ri
into A is a pointer Time
STEP 2
MOVX A, @Ri Code bits in
X specifies external memory, Memory- E2-
byte at Ri points indirectly to an E3H
external memory address for the
operand
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 MOVX @Ri, A 2 clock
For transferring Fetch opcode cycles
A to a byte at
external pointed Sign @ means Ri
address is a pointer Time

MOVX @Ri, A Code bits in

X specifies external memory, Memory- F2-
byte at Ri points indirectly to the F3H
address for the operand
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 Push or Pop direct or Exchange or
Swap

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 Always direct Addressing mode
for Push or Pop

Internal data Memory

(00H-7FH)

SFR (80H-FFH)

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 direct stack
4
1 SP

8051 2
Direct address Increment SP
SFR or Move the byte to SP
internal 00- pointed address 3
7FH RAM
SP is of 8-bits

Push direct

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 direct stack 1
3
2 SP

8051
Direct Move the byte to
address SFR SP pointed address
or internal and decrement SP 4
00-7FH RAM
SP is of 8-bits

Pop direct

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 Instruction Execution 2 clock
Fetch cycles
STEP 1 opcode-bits

STEP 2 Fetch byte direct

Time

direct addressing mode for source operand in

push and for destination operand for pop

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 Push an SFR or Internal RAM
between 00H-7FH

Source
Destination

stack direct

Pre-increment SP

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 Pop an SFR or Internal RAM
between 00H-7FH
Source
Destination

direct stack

Post-decrement SP

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 Exchange of A register byte with
other

Internal data Memory

A register (00H-FFH)

SFR (80H-FFH)

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 A
2
Rn or
1
internal
8051 Temp RAM or
3 SFR
A register

XCH A, Rn, XCH A, direct,

XCH A, @Ri; exchange bytes
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 Exchange of A register lower digit with
other

Internal data Memory

A register (00H-FFH)

SFR (80H-FFH)

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 bit3-bit0 bit3-bit0
3
2 4 1
temp
Indirect
8051 address A register lower 4
internal 00- bits
FFH RAM XCHD A, @Ri;
pointed by exchange lower
R0 or R1 digits (4-bits)

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 Exchange of A register lower digit
with higher digit

A register A register higher

lower bits bits

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 bit7-bit4 bit3-bit0
4
1 6 3 5 2
temp
8051
A register lower 4
A register bits
higher 4 bits

SWAP A; exchange of lower digit (4-

bits) with higher at A

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 Summary

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 We learnt
8051 family data transfer
instructions
• move (copy)
• push
• pop
• exchange
• exchange lower 4-bits
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