Single-Cycle Mips

Architecture
Arquitectura de Computador
Módulo 1
Introduction
• What is microarchitecture?
• Datapath
• Datapath and Control signals
• Alu control
• Control unit
• How to determine the clock period or clock rate?
• Performance
Single-Cycle Mips Architecture
• Microarchitecture
• How the architecture is implemented in hardware

Processor Memory

Input/Output
devices
Single-Cycle Mips Architecture
• Microarchitecture
• How the architecture is implemented in hardware

Control: control signals

Processor

Datapath: functional blocks

Single-Cycle Mips Architecture
• Microarchitecture
• How the architecture is implemented in hardware
Interprets the instructions
-Enables the signals to generate the
following address of the next instruction
Control: control signals (PC)
-Responsible of generating the correct
sequence for the execution of instructions
Processor

Functional units (ALU, Full Adders)

Datapath: functional blocks Registers
Support units (Multiplexers, buses,
decoders,etc)
 Single-Cycle Mips Architecture
Microarchitecture Instruction Fetch:
Steps for a generic implementation PC (instruction
address) –>
Memory

Decode: Control
unit

Read registers

• Arithmetic/logical result
Execution
Depending on • Memory address for load/store
instruction class • Branch target address

Write
• Registers
Depending on
instruction class
• Memory

PC+4
Single-Cycle Mips Architecture

•Type R
•Type I
•Type J
Datapath
Single-Cycle Mips Architecture
31-26 25-21 20-16 15-11 10-6 5-0
Opcode rs rt rd shamt function

•Type R 31-26 25-21 20-16 15-0

•Type I Opcode rs rt Immediate/offset

31-26 25-0
•Type J Opcode Target=Address

Datapath
Single-Cycle Mips Architecture
Datapath

[25..0]
Single-Cycle Mips Architecture
Datapath and Control signals

[25..0]

6
Single-Cycle Mips Architecture
• ALU Control
Single-Cycle Mips Architecture
• ALU Control
Single-Cycle Mips Architecture
• ALU Control
Single-Cycle Mips Architecture
• ALU Control
 Single-Cycle Mips Architecture
Datapath and Control signals

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6
Single-Cycle Mips Architecture

31
Single-Cycle Mips Architecture

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 Single-Cycle Mips Architecture
Unit Control
Opcode ALUOp ALUSrc MemRead MemWrite RegDst MemToReg RegWrite Branch Jump

R 0x00 000000 010 0 0 0 01 00 1 0 0

Addi 0x08 001000 000 1 0 0 00 00 1 0 0
Slti 0x0A 001010 101 1 0 0 00 00 1 0 0
LW 0x23 100011 000 1 1 0 00 01 1 0 0
SW 0x2B 101011 000 1 0 1 00 00 0 0 0
BEQ 0x04 000100 001 0 0 0 00 00 0 1 0
J 0x02 000010 000 0 0 0 00 00 0 0 1

ORi 0x0D 001101 011 1 0 0 00 00 1 0 0

ANDi 0x0C 001100 100 1 0 0 00 00 1 0 0
Addiu 0x09 001001 000 1 0 0 00 00 1 0 0
 Single-Cycle Mips Architecture
Unit Control
Single-Cycle Mips Architecture

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 Single-Cycle Mips Architecture LW
execution
Clock Period > Tpc+Tmemory + max(TRFread, Tsex+Tmux) +Talu + Tmemory + Tmux +TRFsetup

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 Single-Cycle Mips Architecture LW
execution
Clock Period > Tpc+Tmemory + max(TRFread, Tsex+Tmux) +Talu + Tmemory + Tmux +TRFsetup
32 ps +250ps + max (150ps, 21ps+25ps) + 200ps + 250 ps + 25ps + 20 ps
Clock Period > 927 ps

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Single-Cycle Mips Architecture
• Performance
Main:
Lui $S1, 0x1000
Ori $S1, $S1, 0x0000
Addi $S4, $0, 5 4
Addi $S5, $0, 0
For:
Beq $S4,$S5, Exit
Sll $t1, $S5,2
Add $t1, $St1,$S1
Lw $S2, 0($t1) 46
Lw $S3, 4($t1)
Sub $S3, $S3,$S4
Sw $S3, 100($t1)
Addi $S5,$S5,1
J for
Exit :
Jr $ra 1 Tex= 51 inst x927 ps/inst = 47277 ps
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Reference
Hennessy, John L. and Patterson, David A., Computer architecture : a
quantitative approach, 6th Edition. Morgan Kaufmann, 2017. Chapter
4.