2.

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue Date: Oct 2002

Abstract
A summary of electrical and optical approaches to clock distribution within high-performance
microprocessors is presented. System-level properties of intrachip electrical clock distribution
networks corresponding to three microprocessor families are summarized. It is found that global
clock interconnect performance and short-term jitter present the greatest challenges to the
continued use of conventional clock distribution methodologies. An extrapolation of trends
describing the percentage of clock period consumed by global skew and short-term jitter
identifies the 32-nm technology generation of the 2002 International Technology Roadmap for
Semiconductors (ITRS) as the first technology generation within which alternate methods of
clock distribution may be warranted. Research efforts investigating interboard through intrachip
optical clock distribution are also summarized. An optical distribution network compatible with
high volume manufacturing in conjunction with a suitable means of providing optical-to-
electrical signal conversion comprise the two fundamental challenges facing successful
implementation of an optical clock distribution network. It is found that a global guided-wave
distribution capable of efficient input and output coupling of optical power is required to meet
the first challenge. The identification of a suitable means of optical-to-electrical conversion,
however, remains an active topic of research.

3. Solid-State Circuits, IEEE Journal of

Abstract
Recently reported logic style comparisons based on full-adder circuits claimed complementary
pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS.
However, new comparisons performed on more efficient CMOS circuit realizations and a wider
range of different logic cells, as well as the use of realistic circuit arrangements demonstrate
CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and
power-delay products. An implemented 32-b adder using complementary CMOS has a power-
delay product of less than half that of the CPL version. Robustness with respect to voltage
scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of
CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This
paper shows that complementary CMOS is the logic style of choice for the implementation of
arbitrary combinational circuits if low voltage, low power, and small power-delay products are
of concern
4. This paper presents the design of high performance and low power arithmetic circuits using a new
CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical
applications. The proposed dynamic logic family allows for a partial evaluation in a computational block
before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The
proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a
large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in
high fanout and high switching frequencies due to both lower delay and dynamic power consumption.
Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic
logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and
similar combined delay, power consumption and active area product (only 8% higher), while exhibiting
lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic
domino CMOS technologies.

5. Abstract
Motivated by emerging battery-operated applications that demand intensive computation in
portable environments, techniques are investigated which reduce power consumption in CMOS
digital circuits while maintaining computational throughput. Techniques for low-power operation
are shown which use the lowest possible supply voltage coupled with architectural, logic style,
circuit, and technology optimizations. An architecturally based scaling strategy is presented
which indicates that the optimum voltage is much lower than that determined by other scaling
considerations. This optimum is achieved by trading increased silicon area for reduced power
consumption

6.Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue Date: June 2007

Abstract
This brief presents a new CMOS logic family using the feedthrough evaluation concept and
analyzes its sensitivity against technology parameters for practical applications. The feedthrough
logic (FTL) allows for a partial evaluation in a computational block before its input signals are
valid, and does a quick final evaluation as soon as the inputs arrive. The FTL is well suited to
arithmetic circuits where the critical path is made of a large cascade of inverting gates.
Furthermore, FTL based circuits perform better in high fanout and high switching frequencies
due to both lower delay and dynamic power consumption. Experimental results, for practical
circuits, demonstrate that low-power FTL provides for smaller propagation time delay (4.1
times), lower energy consumption (35.6%), and similar combined delay, power consumption and
active area product (0.7% worst), while providing lower sensitivity to power supply,
temperature, capacitive load and process variations than the standard CMOS technologies.

7. Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue Date: June 2007

Abstract
This brief presents a new CMOS logic family using the feedthrough evaluation concept and
analyzes its sensitivity against technology parameters for practical applications. The feedthrough
logic (FTL) allows for a partial evaluation in a computational block before its input signals are
valid, and does a quick final evaluation as soon as the inputs arrive. The FTL is well suited to
arithmetic circuits where the critical path is made of a large cascade of inverting gates.
Furthermore, FTL based circuits perform better in high fanout and high switching frequencies
due to both lower delay and dynamic power consumption. Experimental results, for practical
circuits, demonstrate that low-power FTL provides for smaller propagation time delay (4.1
times), lower energy consumption (35.6%), and similar combined delay, power consumption and
active area product (0.7% worst), while providing lower sensitivity to power supply,
temperature, capacitive load and process variations than the standard CMOS technologies.

8. Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue Date: Nov. 2004

Abstract
A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this
paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input
signals arrive. A modified version of this logic, where the function and its complement are
implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are
reset to low during the high phase of the clock and evaluated during the low phase of the clock.
Resetting to low alleviates the problems of charge sharing and leakage current associated with
the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like
fashion without a need for the intervening inverters. We employ this novel concept to design
several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other
published works in terms of device count, area, delay, clock rate and power consumption. The
results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition,
our FTL design compares very well with the standard CMOS technology. FTL gates are fully
compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be
included in a DCFL standard cell library for improving cell-based ASIC performance. To match
the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining
the FTL blocks. Comparisons with the other published results demonstrate the superior
performance of our dynamic latch.

9.Circuits and Systems II: Express Briefs, IEEE

Transactions on
Issue Abstract
We present an accurate model to estimate the energy and delay of domino CMOS gates derived
from a detailed description of internal capacitance switching and discharging currents. The delay
dependence with the position of the switching transistor in the gate is accurately described with
the advantage that it does not include additional empirical parameters, thus providing the
propagation delay in terms of foundry-provided MOSFET parameters. Results show a very high
accuracy with a relative error lower than a 3% with respect to HSPICE for a 0.18-μm CMOS
technology providing up to three orders of magnitude of speed improvement. The analytical
nature of the model makes it suitable for circuit optimization and is the basis for a quick
estimation of ULSI circuits power and delay when used in circuit simulation tools.

Date: Oct. 2005

10 Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue Date: Oct. 2005

Abstract
We present an accurate model to estimate the energy and delay of domino CMOS gates derived
from a detailed description of internal capacitance switching and discharging currents. The delay
dependence with the position of the switching transistor in the gate is accurately described with
the advantage that it does not include additional empirical parameters, thus providing the
propagation delay in terms of foundry-provided MOSFET parameters. Results show a very high
accuracy with a relative error lower than a 3% with respect to HSPICE for a 0.18-μm CMOS
technology providing up to three orders of magnitude of speed improvement. The analytical
nature of the model makes it suitable for circuit optimization and is the basis for a quick
estimation of ULSI circuits power and delay when used in circuit simulation tools.

11. I.S. Hwang, A.L. Fisher, Ultrafast compact 32-bit CMOS adders in
multiple-output domino logic, IEEE J. Solid-State Circuits 24 (1989)

358–3Solid-StateCircuits, IEEE Journal of

Issue Date: Apr 1989 69.

Abstract
A dynamic CMOS logic style, called multioutput domino logic (MODL), has been developed. In
this logic style, single logic gates produce multiple functions, and a circuit's device count can be
reduced by a factor of more than 2, depending on the degree of recurrence in the circuit. In
addition, MODL circuits are, by construction, considerably more stable than other dynamic
circuits including conventional domino. A 32-bit carry lookahead (CLA) structure which reduces
the adder's worst-case path by two logic stages has also been devised. This CLA structure has
been developed to effectively utilize the advantages of MODL. Taken together, these
developments have resulted in two 32-bit CMOS adders, providing area and speed improvements
of 1.5× and 1.7× over the combination of the domino and conventional CLA techniques. Both
adders have been fabricated in a standard 0.9-μm two-level metal CMOS technology, and
measured results show that the straight adder has achieved 32-bit addition times of less than 3.1
ns at 25°C with VDD+5.0 V
12. Abstract
A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this
paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input
signals arrive. A modified version of this logic, where the function and its complement are
implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are
reset to low during the high phase of the clock and evaluated during the low phase of the clock.
Resetting to low alleviates the problems of charge sharing and leakage current associated with
the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like
fashion without a need for the intervening inverters. We employ this novel concept to design
several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other
published works in terms of device count, area, delay, clock rate and power consumption. The
results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition,
our FTL design compares very well with the standard CMOS technology. FTL gates are fully
compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be
included in a DCFL standard cell library for improving cell-based ASIC performance. To match
the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining
the FTL blocks. Comparisons with the other published results demonstrate the superior
performance of our dynamic latch.

15. This paper presents the design of high performance and low power arithmetic circuits using a new
CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical
applications. The proposed dynamic logic family allows for a partial evaluation in a computational block
before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The
proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a
large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in
high fanout and high switching frequencies due to both lower delay and dynamic power consumption.
Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic
logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and
similar combined delay, power consumption and active area product (only 8% higher), while exhibiting
lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic
domino CMOS technologies.