Digital System Design

Lab report 06
Group members:
Hamad Fayon (FA17-EEE-056)
Hassam Ali (FA17-EEE-046)

Un-serial multiplier:

Figure 1: Unsigned multiplier architecture

(a)
Main module:
Testbench:

Results:
Results after several times clicking on ‘RUN’
(b)
Main Module:
Testbench:

Results:
Results after several times clicking on ‘RUN’
(c)
Full adder:

8bit RCA:
Main Module:
Testbench:

Results:
(d)
Testbench:

Results:
(e)
Testbench:

Results: