There are mainly 7 types of logic gates that are used in expressions.

By combining them in different ways,

you will be able to implement all types of digital components. Take a look at each basic logic gate and their
operation.
A Logic Gate is assigned as an elementary building block of digital circuits. Logic gate is considered as a
device which has the ability to produce one output level with the combinations of input levels. There are
seven basic types of logic gates:
 AND GATE  NOR GATE
 OR GATE  EXCLUSIVE-OR GATE (X-OR) GATE
 NOT GATE  EXCLUSIVE-NOR (X-NOR) GATE1
 NAND GATE

The reason for which the computers are capable of performing complex operation is due to the
interconnection of these logic gates. Logic gates are implemented by using transistors, diodes, relays, optics
and molecules or even by several mechanical elements. Due to this reason logic gates can also be considered
as electronic circuits. The logic gates can be build up in a wide variety forms such as large-scale integrated
circuits (LSI), very large-scale integrated circuits (VLSI) and also in small-scale integrated circuits (SSI).
Here the inputs and output of all the gates of integrated devices can be accessible and also the external
connections are made available to them just like discrete logic gates.
Inputs and outputs of logic gates are in two levels termed as HIGH and LOW, or TRUE and FALSE, or ON
and OFF, or simply 1 and 0. A table which list out the combination of input variables and the corresponding
output variables is termed as “TRUTH TABLE”. It explains how the logic circuit output responds to various
combinations of logic levels at the inputs. Here we are following level logic, in which the voltage levels are
represented as logic 1 and logic 0. Level logic is of two types such as positive logic or negative logic. In the
positive logic system, higher of the two voltage levels are represented as 1 and lower of the two voltage
levels are represented as 0. But in the negative logic system, higher of the two voltage levels are represented
as 0 and lower of the two voltage levels are represented as 1. While considering the transistor-transistor
logic (TTL), the lower state is assumed to be zero volts (0V) and the higher state is considered as five volts
positive (+5V).
AND GATE

An AND gate requires two or more inputs and produce only one output. The AND gate produces an output
of logic 1 state when each of the inputs are at logic 1 state and also produces an output of logic 0 state even
if any of its inputs are at logic 0 state. The symbol for AND operation is ‘.’, or we use no symbol for
representing. If the inputs are of X and Y, then the output can be expressed as Z=XY. The AND gate is so
named because, if 0 is called “false” and 1 is called “true,” the gate performs in the same way as the logical
“and” operator. The AND gate is also named as all or nothing gate. The logic symbols and truth tables of
two-input and three-input AND gates are given below.

2 Input AND Gate – Truth Table

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 3 Input AND Gate – Truth Table

Discrete AND gates may be realized by using diodes or transistors. The inputs represented as X and Y may
be either 0V or +5V correspondingly. The output is represented by Z . In the diode of AND gate, when both
the inputs are of same value, X=+5V and Y= +5V, then the diodes are in OFF condition. As a result, no
current flows through the resistor and there will not be any voltage drop across the resistor. Here the output
will be Z=+5V. Similarly, when both the inputs such as X and Y are equal to 0V, then the corresponding
diodes such as either D1 or D2 or both the diodes are at ON state and act as short circuits. Here the output
will be Z corresponds to 0V. In practical cases the output z corresponds to 0.6V or 0.7V, which is treated as
logic 0 state.

2 Input Diode AND Gate

2-Input Transistor AND Gate

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In the case of transistor AND gate, When the inputs X, Y = 0V or when X=0V and Y= +5V or when X=+5V
and Y=0V, both the transistors Q1 and Q2 are at OFF state. At the same time, Transistor Q3 gets enough
base drive from the supply through Resistor R3 and so transistor Q3 will be ON. Thereby the output voltage
Z= Vce(sat) corresponds to 0V. When both the inputs are equal to +5V, the transistors Q1 and Q2 will be ON
and therefore the voltage at the collector of transistor Q1 will drop. Due to this the transistor Q3 doesn’t get
enough base drive and turns OFF. As a result no current flows through the collector resistor of Q3 and ,
thereby no voltage drop across it. So the final output voltage corresponds to +5V. The truth table for this
gate circuit is shown below:

Discrete AND Gate Truth Table

OR GATE
Similar to AND gate, an OR gate may also have two or more inputs but produce only one output. The OR
gate produces an output of logic 1 state even if any of its inputs is in logic 1 state and also produces an
output of logic 0 state if any of its inputs is in logic 0 state. The symbol for OR operation is ‘+’.  If the inputs
are of X and Y, then the output can be represented as Z=X+Y. An OR gate may also be defined as a device
whose output is 1, even if one of its input is 1. OR gate is also called as any or all gate. It is also called as an
inclusive OR gate because it consists of the condition of ‘both the inputs can be present’.  The logic symbols
and truth table for two-input and three-input OR gates are given below.

2 Input OR Gate – Truth Table

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 3 Input OR Gate – Truth Table

Discrete OR gates may be realized by using diodes or transistors. The inputs represented as X and Y may be
either  0V or +5V correspondingly. The output is represented by Z . In the diode of OR gate, when both the
inputs are of same value, X=0V and Y= 0V, then both the diodes are in OFF condition. As a result, no
current flows through the resistor and there will not be any voltage drop across the resistor. Here the output
will be Z=0V. Similarly, when both the inputs or either the inputs such as X and Y are equal to +5V, then
the corresponding diodes either D1 or D2 or both the diodes are at ON state and act as short circuits. Here
the output will be Z corresponds to +5V. In practical cases the output Z corresponds to +5V-diode drop = 
+5V – 0.7V = +4.3V, which is regarded as Logic 1 state.

2 Input Diode OR Gate

2-Input Transistor OR Gate

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In the case of transistor OR gate, when the inputs X=0V and Y = 0V both the transistors Q1 and Q2 are at
OFF state. At the same time, Transistor Q3 gets enough base drive from the supply +5V through Resistor R3
and so transistor Q3 will be ON. Thereby the output voltage Z= V ce(sat) corresponds to 0V. When either the
inputs X and Y or both the inputs are equal to +5V, then the corresponding transistors either Q1 or Q2 will
be ON or both the transistors Q1 and Q2 will be ON and therefore the voltage at the collector of transistor
Q1 is VCE(sat) corresponds to 0V. Due to this reason the transistor Q3 doesn’t forward bias the base-emitter
junction and turns OFF. So the final output voltage corresponds to +5V (logic 1 state). The truth table for
this gate circuit is shown below:

Discrete OR Gate Truth Table

NOT GATE
The NOT gate is also called as an inverter, simply because it changes the input to its opposite. The NOT
gate is having only one input and one corresponding output. It is a device whose output is always the
compliment of the given input. That means, the NOT gate produces an output of logic 1 state when the input
is of logic 0 state and also produce the output of logic 0 state when the input is of logic 1 state. The NOT
operation is denoted by ’-‘(bar). When the input variable to the NOT gate is represented by ‘X’ and the
output is represented by ‘Z’. In the NOT operation it can be read as ‘Z is equal to X bar’. The logic symbol
and truth table are given below:

NOT Gate – Truth Table

Discrete NOT gate may be realized by using transistors. The inputs represented as X may be either 0V or
+5V correspondingly. The output is represented by Z. When the input X = 0V, then the transistor Q1 will be
reverse biased and therefore it remains OFF. As a result no current flows through the resistor and thereby
there will not be any voltage drop across the resistor. As a result, the output voltage Z corresponds to +5V.
When the input X= +5V, transistor Q1 is ON and the output voltage Z=V  ce(sat) corresponds to 0V. The truth
table for the NOT gate is given below:

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 Transistor Inverter NOT Gate

Transistor Inverter NOT Gate – Truth Table

NAND GATE
The NAND and NOR gates are the universal gates. Each of this gates can realize the logic circuits single
handedly. The NAND and NOR are also called as universal building blocks. Both NAND and NOR has the
ability to perform three basic logic functions such as AND,OR and NOT. NAND gate is a combination of an
AND gate and a NOT gate. The expression for the NAND gate is ‘—‘whole bar. The output of the NAND
gate is at logic 0 level only when each of the inputs assumes a logic 1 level. The truth table of two-input
NAND gate is given below:

2 Input NAND Gate -Truth Table

A Discrete two-input NAND  gate is as shown in the figure. The two inputs are represented by X and Y. The
output is represented by Z .  When the input X and Y= +5V, then both the diodes D1 and D2 are OFF. The
transistor Q1 gets enough base drive from the supply through resistor and therefore transistor Q1 is ON and
the output Z=Vce(sat) corresponds to 0V. Similarly when inputs either x=0V or Y=0V or when both inputs are
equal to 0V, at that time the transistor Q1 is OFF and therefore, output voltage Z= +5V. The truth table is
given below:

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 Discrete NAND Gate

Discrete NAND Gate -Truth Table

NOR GATE
NOR means NOT OR. That means, NOR gate is a combination of an OR gate and a NOT gate. The output is
logic 1 level, only when each of its inputs assumes a logic 0 level. For any other combination of inputs, the
output is a logic 0 level. The truth table of two-input NOR gate is given below:

2 Input NOR Gate – Truth Table

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 3 Input NOR Gate -Truth Table
Discrete two-input NOR gate is as shown in the figure. The inputs represented as X and Y may be 0V
correspondingly. As a result the transistors Q1 and Q2 are OFF, as a result no current flows through the
resistor and thereby there will not be any voltage drop across the resistor. Here, the output voltage Z
corresponds to +5V. When either of the input X= +5V or Y=+5V or both the inputs corresponds to +5V, the
corresponding transistor Q1or Q2 or both Q1 and Q2 are ON . Therefore the output voltage
Z=V ce(sat) corresponds to ground and equal to 0V. The truth table for the NOR gate is given below:

Discrete NOR Gate

Discrete NOR Gate – Truth Table

EXCLUSIVE-OR GATE (X-OR) GATE

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An X-OR gate is a two input, one output logic circuit. X-OR gate assumes logic 1 state when any of its two
inputs assumes a logic 1 state. When both the inputs assume the logic 0 state or when both the inputs assume
the logic 1 state, the output assumes a logic 0 state. The output of the X-OR gate will be the sum of the
modulo sum of its inputs. X-OR gate is also termed as anti-coincidence gate or inequality detector. An X-
OR gate can also be used as inverter by connecting one of the two input terminals to logic1 and also by
inputting the sequence to be inverted to the other terminal.

X-OR Gate – Truth Table

EXCLUSIVE-NOR (X-NOR) GATE
An X-NOR gate is a combination of an X-OR gate and a NOT gate. The X-NOR gate is also a two input,
one output concept. The output of the X-NOR gate will be logic 1 state when both the inputs assume a 0
state or when both the inputs assume a 1 state. The output of the X-NOR gate will be logic 0 state when one
of the inputs assume a 0 state and the other a 1 state. It is also named as coincidence gate, because its output
will be 1 only when the inputs coincide. X-NOR gate can also be used as inverter by connecting one of the
two input terminals to logic 0 and also by inputting the sequence to be inverted to the other terminal.

X-NOR Gate – Truth-Table

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Introduction Sequential logic circuits

Sequential logic circuits are those, whose output depends not only on the present value of the input but also
on previous values of the input signal (history of values) which is in contrast to combinational circuits where
output depends only on the present values of the input, at any instant of time. Sequential circuit can be
considered as combinational circuit with feedback circuit. Sequential circuit uses a memory element like flip
– flops as feedback circuit in order to store past values. The block diagram of a sequential logic is shown
below.

Sequential logic circuits are used to construct finite state machines, which are basic building block in all
digital circuitry, and also in memory circuits. Basically, all circuits in practical digital devices are a mixture
of combinational and sequential logic circuits.
Example:
Generally, we come across many counters in our daily life to count the number of objects .For example to
count the number of audience entering or leaving an auditorium or to count number of vehicles in parking.In
this when any person enters in to auditorium the counter increments its value depending on its present value.
Similarly, it decrements its value depending on its previous and present value. So Counter retains the present
state of the counter to do next operation.
This is analogous to sequential circuits which changes their state according to the previous and present
signals.
Combinational circuits vs Sequential circuits
COMBINATIONAL CIRCUITS SEQUENTIAL CIRCUITS

Output depends only on the present value of the Output depends on both the present and previous
inputs. state values of the inputs

These circuits will not have any memory as their Sequential circuits have some sort of memory as
outputs change with the change in the input value. their output changes according to the previous and
present values.

There are no feedbacks involved. In a sequential circuit the outputs are connected to
it as a feedback path.

Used in basic Boolean operations. Used in the designing of memory devices.

Implemented in: Half adder circuit, full adder Implemented in: RAM, Registers, counters and
circuit, multiplexers, demultiplexers, decoders and other state retaining machines.
encoders.

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Importance of clock signal in sequential circuits
The clock signal plays a crucial role in sequential circuits. A clock is a signal, which oscillates between logic
level 0 and logic level 1, repeatedly. Square wave with constant frequency is the most common form of
clock signal. A clock signal has “edges”. These are the instants at which the clock changes from 0 to 1 (a
positive edge) or from 1 to 0 (a negative edge).

Clock signals control the outputs of the sequential circuit .That is it determines when and how the memory
elements change their outputs . If a sequential circuit is not having any clock signal as input, the output of
the circuit will change randomly. So that they cannot retain their state till the next input signal arrives. But
sequential circuits with clock input will retain its state till the next clock edge occurs.

Classification of sequential circuits

Based on the clock signal input, the sequential circuits are classified into two types.

 Synchronous sequential circuit

  Asynchronous sequential circuit

Synchronous sequential circuits

Definition:
In Synchronous sequential circuit, the output depends on present and previous states of the inputs at the
clocked instances. The circuits use a memory element to store the previous state. The memory elements in
these circuits will have clocks. All these clock signals are driven by the same clock signal

  Using clock signal, state changes will occur across all storage elements.
  These circuits are bit slower compared to asynchronous because they wait for the next clock pulse to
arrive to perform the next operation.
  These circuits can be clocked or pulsed.
  The Synchronous sequential circuits that use clock pulses in their inputs are called clocked-
sequential circuits. They are very stable.
  The sequential circuits that change their state using the pulse and these are called pulsed or
unclocked sequential circuits.
Where we use synchronous sequential circuits??
• Used in the design of MOORE-MEALY state management machines.
• They are used in synchronous counters, flip flops etc.
Limitations of Synchronous Sequential Circuits

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  All the flip – flops in synchronous sequential circuits must be connected to clock signal. Clock
signals are very high frequency signals and clock distribution consumes and dissipated a large amount
of heat.
 Critical path or the slowest path determines the maximum possible clock frequency. Hence they are
slower than asynchronous circuits.
Asynchronous Sequential circuits
Definition
The Sequential circuits which do not operate by clock signals are
called “Asynchronous sequential circuits”.
 These circuits will change their state immediately when
there is a change in the input signal .
 The Circuit behaviour is determined by signals at any
instant in time and the order in which input signals change.
  They do not operate in pulse mode.
  They have better performance but hard to design due to
timing problems.
 Mostly we use the asynchronous circuits when we require the low power operations.
 They are faster than synchronous sequential circuits as they do not need to wait for any clock signal.
Where we use Asynchronous sequential circuits??
These are used when speed of operation is important. As they are independent of internal clock pulse, they
are operate quickly. so they are used in Quick response circuits.

 Used in the communication between two units having their own independent clocks.
 Used when we require the better external input handling.
DRAWBACKS:
  Asynchronous sequential circuits are more difficult to design.
  Though they have a faster performance, their output is uncertain.

Feedback in Sequential Circuits

Combinational circuits do not require any feed back as the outputs are purely dependent on the present value
of the input. But in case of sequential circuits, the outputs are dependent on past values of the input along
with present values. In order to involve memory element like a flip – flop, feedback must be introduced in
the circuit. For example, consider a simple feedback circuit as shown below.

If 0 is the input to the inverter at an instance, this 0 will propagate and the output is 1. This 1 is fed back as
input. This 1 will propagate and the output is 0. The process repeats and the result is a continuous oscillation
of output between 0 and 1. There is no stable state in this scenario.
Now consider the following example of two inverters connected as shown.

Here two inverters are connected back to back with the output of the second inverter fed back to input of
first inverter. If 0 is the input to first inverter at an instance, it propagates through the first inverter and the
output is 1. This 1 is input to second inverter and propagates through it. The output of the second inverter is
0 which is fed back to the first inverter. But the input to first inverter is already 0 and hence no change
occurs. The circuit is said to be in a stable circuit. Another stable state can be obtained when the input to the
first inverter is 1.

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Half Adder and Full Adder Circuit
An Adder is a device that can add two binary digits. It is a type of digital circuit that performs
the operation of additions of two number. It is mainly designed for the addition of binary
number, but they can be used in various other applications like binary code decimal, address
decoding, table index calculation, etc. There are two types of Adder. One is Half Adder, and
another one is known as Full Adder. The detail explanation of the two types of the adder is
given below.
Half Adder
There are two inputs and two outputs in a Half Adder. Inputs are named as A and B, and the
outputs are named as Sum (S) and Carry (C). The Sum is X-OR of the input A and B. Carry is
AND of the input A and B. With the help of half adder, one can design a circuit that is capable
of performing simple addition with the help of logic gates. Let us first take a look at the addition
of single bits.
0+0=0
0+1=1
1+0=1
1 + 1 = 10
These are the least possible single bit combinations. But the result for 1 + 1 =10. This problem
can be solved with the help of an EX – OR gate. The sum results can be re-written as a 2-bit
output. Thus the above combination can be written as
0 + 0 = 00
0 + 1 = 01
1 + 0 = 01
1 + 1 = 10
Here the output “1” of “10” becomes the carry-out. SUM is the normal output and
the CARRY is the carry-out.
The truth table of the half adder is shown below

.
The Half Adder Circuit is shown below.
The main disadvantage of this circuit is that it
can only add two inputs and if there is any
carry it is neglected. Thus, the process is
incomplete. To overcome this difficulty Full
Adder is designed. While performing complex

13
addition, there may be cases when you have to add two 8 bit bytes together. This can be done
with the help of Full Adder.

Full Adder
The full adder is a little more difficult to implement than a half adder. The main difference
between a half adder and a full adder is that the full adder has three inputs and two outputs. The
two inputs are A and B, and the third input is a carry input C IN. The output carry is designated as
COUT, and the normal output is designated as S.
The truth table of the Full Adder Circuit is shown below.

The output S is an EX – OR between the input A and the half adder SUM output B. The
COUT will be true only if any of the two inputs out of the three are HIGH or at logic 1.

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Thus, a full adder circuit can be implemented with the help of two half adder circuits. The first
half adder circuit will be used to add A and B to produce a partial sum. The second half adder
logic can be used to add C IN to the sum produced by the first half adder circuit. Finally, the
output S is obtained.
If any of the half adder logic produces a carry, there will be
an output carry. Thus, COUT will be an OR function of the half
adder CARRY outputs.
The Full adder circuit diagram is shown below.

The schematic
representation of a single bit Full Adder is shown below.
With the help of this type of symbol, one can add two bits together, taking a carry from the next
lower order of magnitude and sending a carry to the next higher order of magnitude. In a
computer, for a multi-bit operation, each bit must be represented by a full adder and must be
added simultaneously. Thus, to add two 8 bit numbers, 8 full address is needed that can be
formed by cascading two of the 4-bit blocks.
The addition of the four-bit number is shown below.
Full Adder is used for a complex addition like for adding two 8 – bit bytes together.
JK Flip Flop
The JK Flip Flop is the most widely used flip flop. It is considered to be a universal flip-flop circuit.
The sequential operation of the JK Flip Flop is same as for the RS flip-flop with the
same SET and RESET input. The difference is that the JK Flip Flop does not the invalid input states of
the RS Latch (when S and R are both 1).The JK Flip Flop name has been kept on the inventor name of
the circuit known as Jack Kilby. The basic symbol of the JK Flip Flop is shown below.

The basic NAND gate RS flip-flop suffers from two

main problems. Firstly, the condition when S = 0 and R
= 0 should be avoided. Secondly, if the state of S or R
changes its state while the input which is enabled is
high, the correct latching action does not occur. Thus to
overcome these two problems of the RS Flip-
Flop, the JK Flip Flop was designed.

The JK Flip Flop is basically a gated RS flip

flop with the addition of the clock input
circuitry. When both the inputs S and R are
equal to logic “1”, the invalid condition takes

15
place. Thus to prevent this invalid condition, a clock circuit is introduced. The JK Flip Flop has four
possible input combinations because of the addition of the clocked input. The four inputs are “logic 1”,
‘logic 0”. “No change’ and “Toggle”.
The circuit diagram of the JK Flip Flop is shown in the figure below.
The S and R inputs of the RS bistable have been replaced by the two inputs called the J and K input
respectively. Here J = S and K = R. The two input AND gates of the RS flip-flop is replaced by the two
3 inputs NAND gates with the third input of each gate connected to the outputs at Q and Ǭ. This cross
coupling of the RS Flip-Flop is used to produce toggle action. As the two inputs are interlocked.
If the circuit is in the “SET” condition, the J input is inhibited by the status 0 of Q through the lower
NAND gate. Similarly, the input K is inhibited by 0 status of Q through the upper NAND gate in the
“RESET” condition. When both J and K are at
logic “1”, the JK Flip Flop toggle.

The Truth Table of the JK Flip Flop is shown

below.
JK Flip Flop is similar to RS flip flop with the
feedback which enables only one of its input
terminals. It eliminates the invalid condition
which arises in the RS flip flop and put the input
terminal either to set or reset condition one at a
time.
When both the J and K input are at logic “1” at the
same time and the clock input is pulsed HIGH, the
circuit toggle from its SET state to a RESET or visa verse. When both the terminals are HIGH the JK
flip-flop acts as a T type toggle flip-flop.
JK flip-flop has a drawback of timing problem known as “RACE”. The condition of RACE arises if the
output Q changes its state before the timing pulse of the clock input has time to go in OFF state. The
timing pulse period (T) should be kept as short as possible to avoid the problem of timing.
This condition is not possible always thus a much improved flip-flop named Master Salve JK Flip
Flop was developed. This eliminates all the timing problems by using two RS flip-flop connected in
series. One is for the “MASTER “ circuit, which triggers on the leading edge of the clock pulse. The
other is called the “SLAVE” circuit, which triggers when the clock pulse is at the falling edge.
RS Flip Flop
A Flip Flop is a bi-stable device. There are three classes of flip flops they are known as Latches, pulse-
triggered flip-flop, Edge- triggered flip flop. In this set word means that the output of the circuit is
equal to 1 and the word reset means that the output is 0. There are two types of flip flop one is an  RS
Flip Flop and JK Flip Flop. In this article RS Flip Flop is explained in detail.
The RS Flip Flop is considered as one of the most basic sequential logic circuits. The Flip Flop is a one-
bit memory bi-stable device. It has two inputs, one is called “SET” which will set the device (output =
1) and is labeled S and another is known as “RESET” which will reset the device (output = 0) labeled
as R. The RS stands for SET/RESET.
The flip-flop is reset back to its original state with the help of RESET input and the output is Q that will
be either at logic level “1” or logic”0”. It depends upon the set/reset condition of the flip-flop. Flip flop
word means that it can be “FLIPPED” into one logic state or “FLOPPED” back into another.
The basic NAND gate RS Flip Flop circuit is used to store
the data and thus provides feedback from both of its outputs
again back to its inputs. The RS Flip Flop actually has three
inputs, SET, RESET and its current output Q relating to its
current state.
The symbol of the RS Flip-Flop is shown below.

The NAND Gate RS Flip Flop

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A pair of cross-coupled 2 unit NAND gates is the simplest way to make any basic one-bit set/reset RS
Flip Flop. It forms Set/Reset bi-stable or an active LOW RS NAND gate latch. The feedback is fed from
each output to one of the other NAND gate input.
The device consists of two inputs; one is known as
SET, (S) and the other is called as RESET, (R). The
two outputs are Q and Q bar as shown in the figure
below.
The Set State
Considering the above circuit. If the input R is at
logic level “0” (R = 0) and input S is at the logic “1”
(S = 1), the NAND gate Y has, at least, one of its
inputs at a logic “0”. Therefore, its output Q must be
at a logic level “1” (NAND gate principles). The
Output (Q) is fed back to the input “A”. Both the
inputs of the NAND gates X are at logic “1”, and therefore, its output Q must be at the logic level”0”.
The reset input R changes its state, and goes HIGH to logic “1” with S constant at logic “1”. The NAND
gate Y input are now (R = 1) and (B = 0). The output at Q remains at HIGH or at logic level “1” as one
of its inputs is still at logic level “0”. As a result, there is no change in state. Therefore, the flip-flop
circuit is said to be “LATCHED” or “SET” with Q = 1 and Ǭ = 0.
The Reset State
In this second stable state, Q is at logic level ‘0” and its inverse output Q is at logic level “1”. And is
given by (R = 1) and (S = 0). As gate X has one of its inputs at a logic “0” its output Q must equal logic
level “1”. (According to the NAND gate principle). The Output Q is fed to input B, so both the inputs to
NAND gate Y are at logic “1”., therefore, Q = 0.
If the set input S now changes the state to logic “1” with the input R remaining at logic “1”, the output
Q still remains LOW at logic level “0”. And there is no change in the state. Therefore, the flip-flop
circuits “RESET” state has been latched.
The truth table of the Set/Reset is given below.

From the truth table, it is clear that when both the inputs S = 1 and R =1 the outputs Q, and Ǭ can be at
either logic level ‘1’ or “0” depending upon the state of the inputs. When the input state R = 0 and S = 0
is an invalid condition and must be avoided because this will give both outputs Q and Ǭ at logic level
“1” at the same time and the necessary condition is that Q to be the inverse of Ǭ.
The flip-flop goes to an unstable state as both the output goes LOW. This unstable condition arises
when the LOW input is switched to HIGH. The flip-flop
switches to one state or the other and any one output of the
flip-flop switches faster than the other. This unstable condition
is known as Meta- stable state.
The bistable RS flip flop or is activated or set at logic “1”
applied to its S input and deactivated or reset by a logic “1”

17
applied to R. The RS flip-flop is said to be in an invalid condition if both the set and reset inputs are
activated simultaneously.
The NOR Gate RS Flip Flop
The circuit diagram of the NOR gate flip-flop is shown in the figure below.
A simple one bit RS Flip Flops are made by using two cross-coupled NOR gates connected in the same
configuration. The circuit will work similar to the NAND gate circuit.

The truth table of the NOR gate RS Flip Flop is shown below.

The inputs are active HIGH and the invalid condition exists when both its inputs are at logic level ‘1’.

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Important Questions Test: Digital Circuits BCA – 3
Each question carries 5 marks
MM: 25
Q1: Write a short note on followings:

(a) Flip Flop

(b) Latch

Q2: What are Feedback in Sequential Circuits? Give example

Q3: Give the drawbacks and uses of Asynchronous Sequential circuits?

Q4: What is meant by Triggering? Give their types?

Q5: What is Race round condition in Latch? How to overcome give method?

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