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Cis5100 hw3 F20
Cis5100 hw3 F20
absolute addressing, access time, addressable memory, average access time, big endian, block, data
transfer rate, data transfer unit, defragmenting, device controller, DIMM, dynamic RAM (DRAM),
direct access, disk, disk drives, EEPROM, EPROM, flash memory, flash RAM, floppy disk, firmware,
hard disk, indirect addressing, least significant byte, little endian, magnetoresistive RAM (MRAM),
memory allocation, most significant byte, nonvolatile, nonvolatile memory, offset register, phase-
change memory (PCM), parallel access, physical memory, primary storage, random access, random
access memory (RAM), read-only memory (ROM), refresh cycle, relative addressing, secondary
storage, sector, serial access, SIMM, solid-state drive, static RAM (SRAM), storage medium,
synchronous DRAM (SDRAM), volatile, wait states, Secondary storage
1. Dynamic RAM requires frequent to maintain its data content.
refresh cycles
2. The rate is the speed at which data can be moved to or from a storage device over a
communication channel.
data transfer
3. The contents of most forms of RAM are , making them unsuitable for long-term data
storage.
volatile
5. is typically stated in milliseconds for secondary storage devices and nanoseconds for
primary storage devices.
Access time
6. The access method for RAM is or if words are considered the unit of data
access. The access method is if bits are considered the unit of data access.
7. A(n) mimics the behavior and physical size of a magnetic disk drive but has no moving
parts.
solid-state drive
8. The data transfer rate of a magnetic or optical disk drive can be calculated by dividing 1 by the
drive’s access time and multiplying the result by the .
data transfer unit size
9. Tape drives are devices. are random or direct access devices.
10. Modern desktop and laptop computers generally use memory packaged on small standardized circuit
boards called .
SIMMs or DIMMs
11. For most disk drives, the unit of data access and transfer is a(n) or .
block, sector
More exercises:
1. The endian storage format places the byte of a word in the lowest memory
address. The endian storage format places the byte of a word in the highest
memory address.
little, least significant, big, most significant
2. The CPU can incur one or more when it accesses slower storage devices.
wait states
3. The number of bits used to represent a memory address determines the amount of a computer’s
.
Addressable memory
3. Describe serial, random, and parallel access. What types of storage devices use each method?
Serial access reads or writes data units in sequential order. Magnetic tape is the only widely
used form of serial access storage. Random access can “jump” directly between two
noncontiguous data units. All primary storage and disk storage devices use random access.
Parallel access reads or writes portions of a data item in parallel on separate storage devices
or media. RAM can be considered a parallel access device.
4. In what way(s) is/are SSDs an improvement over magnetic disk drives? In what way(s) isn't/aren't
they an improvement over magnetic disk drives?
By avoiding all mechanical delays in accessing storage locations, SSDs yield a significant
performance improvement compared to magnetic disk drives. However, their lifetime, as measured in
write cycles, is significantly less than magnetic disk drives. Also, their cost per unit of storage is
generally higher than for magnetic disk drives.
1. A computer with clock rating 2GHz produces, on average, the execution of one instruction per clock
cycle. How many instructions per second can this computer execute? How many instructions would
this computer execute if three instructions per clock cycle execute?
A 1 GHz clock ticks 1x10^9 ticks per second, therefore a 2 GHz clock ticks 2x10^9 ticks per second;
it can execute 2x10^9 instructions per second.
A 2 GHz computer that executes three instructions per tick can do 6x10^9 instructions per second.
2. Assume that a CPU has a clock rating of 2.4 GHz, and half of each clock cycle is used for
fetching and the other half for execution. How many wait states (per fetch) will the CPU
incur if all of primary storage is implemented with a SDRAM which has the access time of
10 nanoseconds?
The wait state = cycle time of the fetch + (2*cycle time)
Cycle time = 1/CPU frequency=1/2.4=0.42 nanoseconds
10 ÷ 0.42 = almost 24 CPU cycles to complete the fetch.
Part of the next cycle is wasted waiting for the execution cycle to begin, so 24 wait states
are incurred.
Storage device Average access Data transfer unit size Data transfer rate (bps)
time
RAM 4 ns 8 bytes (1 ÷ 0.000000004 seconds) ×
8 bytes = 16 Gbps (or 2
GBps)
Optical disc 100 ms 512 bytes (1 ÷ 0.01 seconds) × 512
bytes = 5,120 Bps (or 5.12
KBps)