GmC continuous time Fully differential folded cascade integrator

The testbench
The integrator is supposed to be used in delta sigma modulator having a sampling frequency of
500MHz. The integrator, I am talking about is a Transconductor followed by a capacitor hence called
the Gm-C integrator. First of all I would like to show the test bench I have worked out to test my
integrator. Following is the test bench:

Figure 1

The test bench comprises of an ideal delta sigma modulator on extreme left which comprises of the
following ideal blocks:

Figure 2

In the figure 2 the outputs of “subtractor” on extreme left is fed into the ideal integrator but at the
same time these outputs (so1 and sa2) are fed into the designed integrator in figure 1. This ensures
the designed integrator shall always get the required input which it must be getting when performing
100% in the delta sigma modulator architecture.
The differential output of the integrator in figure 1 are than put into the ideal qunatizers to workout
the possible relusts.

The integrator
The integrator block, like any other fully differential circuits, consists of the following modules:

Figure 3

Testing this integrator with sinusoidal input of 1MHz frequency with the following testbench:

Figure 4

Yields the following responses:

Transient:

figure 5

Magnitude response:

Figure 6

Phase response:
Figure 7

Ploe zero analysis yields:

figure 8

This pole zero analysis lies very much in accordance with the magnitude frequency response.
 Simulation results
What I infer from all these analysis is that the integrator must perform ideally within the frequency
range of 2MHz to 8 MHz. Now testing the same integrator in testbench of figure 1, with sampling
frequency of 8MHz the output is ideal as shown:

Figure 9

The bottom plot is input signal while the two top most plots are that of the quantizer acting with the
designed integrator. When the same integrator is tested with sampling frequencies higher than 8MHz,
the response of integrator tends to deteriorate as shown:

Sampling frequency of 10 MHz yields:

fig 10

Sampling frequency of 50 MHz yields:

fig 11

Sampling frequency of 100 MHz yields:

Fig 12

But in this case I put vdd=1.8 and vss= -1.8

The Problem
The problem lies with the frequency response of the main amplifier. I need to shift the dominant pole
to a higher frequency. I have done number of hand calculations in s-domain trying to shift the poles to
required frequency but translating the s-domain equations into the changes that need to be made in
the circuits is where the problem lies. I using folded cascade topology followed by a CS buffer
amplifier to drive the load. To split the poles introduced by both the folded cascade and CS, a pole
splitting Miller capacitor is inserted in between.

Any suggestions to improve the response of this integrator beyond 8MHz are welcomed!