IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO.

3, MARCH 2017 1183

Power-Gated 9T SRAM Cell for Low-Energy Operation

Tae Woo Oh, Hanwool Jeong, Kyoman Kang, Juhyun Park, Younghwi Yang, and Seong-Ook Jung
Abstract— This brief proposes a novel power-gated 9T (PG9T) static
random access memory (SRAM) cell that uses a read-decoupled access
buffer and power-gating transistors to execute reliable read and write
operations. The proposed 9T SRAM cell uses bit interleaving to achieve
soft error immunity and utilizes a column-based virtual VSS signal
to eliminate unnecessary bitline discharges in the unselected columns,
thereby reducing the energy consumption. In a 22-nm FinFET technology,
the proposed PG9T SRAM cell has a minimum operating voltage
of 0.32 V while achieving the 6σ read stability yield. Compared with
the previously proposed 9T SRAM cell, the proposed cell consumes 45%
and 17% less energy per read and write operation, respectively, at the
minimum operating voltage, and has a 12% smaller bit cell area.
Index Terms— Bit interleaving, FinFET, low-energy operation,
power gating, static random access memory (SRAM).
I. I NTRODUCTION
With the recent proliferation of portable devices, low power
consumption has been highlighted as one of the most important
design features of a system on chip (SoC). Low power consumption
in a static random access memory (SRAM) is particularly important,
because a significant portion of the SoC is occupied by the SRAM. It
is, therefore, necessary to minimize the supply voltage to achieve low
power operation in the SRAM [1]. However, scaling down the supply
voltage increases the threshold voltage (Vth ) variation due to the
variation sources, such as the random dopant fluctuation (RDF) and
line edge roughness (LER) [2]. An increase in the Vth variation exac-
erbates the mismatch between paired transistors in an SRAM cell, and
this, in turn, degrades both the SRAM read stability and write ability.
To reduce the Vth variation, FinFET is widely used in 22-nm
technology as an alternative device to conventional planar-bulk
MOSFET [3]. A low-doped or undoped channel in FinFET suppresses
the RDF, and the 3-D structure affords a better short-channel control-
lability [4]. Accordingly, the susceptibility to the Vth variation can
be alleviated in a FinFET-based SRAM. Despite the advantages of
the FinFET, it cannot achieve sufficient operational yield at a low
operating voltage using the conventional 6T SRAM cell. Moreover,
the quantized strength ratio between transistors in a FinFET-based
SRAM cell worsens the read–write tradeoff. There is thus the need
for the development of a new variation-tolerant SRAM cell.
In the light of the forgoing issues of the conventional 6T SRAM
cell, various SRAM cells have been recently proposed [5]–[8].
In 8T SRAM cell [5], the storage nodes are decoupled from the read
bitline (BL) to enable the same level of read stability as hold stability.
However, pseudoread operation in row half-selected cells during write
operation may cause data flip when bit interleaving scheme is used
Manuscript received April 2, 2016; revised June 26, 2016 and September 26,
2016; accepted October 26, 2016. Date of publication November 17, 2016;
date of current version February 22, 2017. This work was supported by
the IT R&D Program of MOTIE/KEIT through the Project entiltled Design
Technology Development of ultra-low voltage operating circuit and IP for
smart sensor SoC under Grant 10052716.
T. W. Oh, H. Jeong, J. Park, Y. Yang, and S.-O. Jung are with the School
of Electrical and Electronic Engineering, Yonsei University, Seoul 03722,
South Korea (e-mail: sjung@yonsei.ac.kr).
K. Kang was with the School of Electrical and Electronic Engineering,
Yonsei University, Seoul 03722, South Korea. He is now with Samsung
Electronics Company, Ltd., Hwaseong 18448, South Korea.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2016.2623601
1063-8210 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Fig. 1. (a) Previous 9T SRAM cell. (b) Proposed PG9T SRAM cell.
(half-selected problem). To address this issue, a write-back scheme
is required, which increases the delay, area, and power consumption.
CP10T [6] and PPN10T [7] SRAM cells were developed to eliminate
the half-selected problem without write-back scheme. However, the
write ability is weakened by the stacked write path and the large
bit cell area degrades the memory integrity. Especially, in PPN10T
SRAM cell, the write speed is significantly degraded by the Vth drop
along the stacked write path with an nMOS and a pMOS. 9T SRAM
cell in [8] improves the write ability by turning OFF the transmission
gate inserted into the feedback inverter loop, as shown in Fig. 1(a).
However, bit cell area is still large and unnecessary BL discharges in
the unselected columns increase the energy consumption during the
read operation.
This brief proposes a novel power-gated 9T (PG9T) SRAM cell,
shown in Fig. 1(b), for low-voltage operations and compares it with
previously proposed SRAM cells based on 22-nm FinFET technology.
The proposed PG9T SRAM cell achieves target read stability and
write ability yield, and less energy per operation with a smaller area.
II. P ROPOSED P OWER -G ATED 9T SRAM C ELL
The PG9T SRAM cell consists of a cross-coupled pair of inverters
(PU1, PU2, PD1, PD2, PGP, and PGN) and an access buffer (AC1,
AC2, and MDR). One of the two cross-coupled inverters (PU1, PD1,
PGP, and PGN) has stacked pMOSs (PU1 and PGP) and nMOSs (PD1
and PGN) in the pull-up and pull-down networks, respectively, where
PGP and PGN are the power-gating pMOS and nMOS, respectively.
A single-ended BL and the storage node Q are connected through the
access buffer for read and write accesses. The row-based wordline
(WL) is enabled for both the read and write operations while
the column-based write WL (WWL) is enabled only for the write
operation. The WL for PGP (WLPU) and the WL for PGN (WLPD)
are the row-based control signals, which turn OFF the pass-gate
transistors only during the write operation. Meanwhile, the column-
based virtual VSS (VVSS) is activated only during the read operation.
A. Read Operation
A read operation begins when the WL is enabled and the VVSS
is discharged to VSS while the AC2 is turned OFF. Depending on
the data stored at node Q, the precharged BL is either discharged
or remains high. When the data at node Q is “1,” MDR is turned
ON , and this causes the discharge of the BL to VSS through AC1
and MDR. Conversely, when the storage at Q is low, the BL level
remains high, because MDR is turned OFF. The read operation ends
when a sense amplifier detects the transition of the BL. Because
the data storage nodes are decoupled from the BL, the read current

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1184 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO. 3, MARCH 2017
does not flow through the storage nodes, and this eliminates read
disturbance. The read stability is thus the same as the hold stability.
In spite of an asymmetrical inverter latch, the PG9T SRAM cell
exhibits the same read stability as the other read-decoupled SRAM
cells (8T, CP10T, PPN10T, and previous 9T), which have the
symmetrical latches. This is because the strength ratios between the
pull-up network (pMOSs) and pull-down network (nMOSs), which
determine the read stability, for the two inverters in the latch are the
same as those of the other SRAM cells.
B. Write Operation
A write operation begins when the WLPU is charged to VDD
and the WLPD is discharged to VSS . The power-gating transis-
tors are then turned OFF and the paths from the power sources
(VDD and VSS ) to storage node Q are disconnected. At the same time,
both the WL and WWL are activated. The storage node Q is driven
only by the BL voltage, and the write disturbance caused by the power
supply is eliminated. The write ability is thus significantly enhanced
compared with those of the previously proposed 8T and 10T SRAM
cells.
However, writing “1” at the storage node is much more difficult
than writing “0,” because the access transistors (AC1 and AC2) are
composed of nMOSs, which have a weak ability to pass “1.” Vth
drop occurs in the nMOS transistors during a write “1” operation.
During this operation, the storage node is first charged to a middle
voltage (about VDD –Vth ) and considerable time is required for full
charging to VDD using the cross-coupled inverter pair. Moreover,
when using 22-nm FinFET technology, it is not possible to control
Vth of the access transistors by utilizing reverse short channel effect
as in [8], because the lengths of the transistor gates in an SRAM cell
should be equal for a lithography-friendly gate patterning process [9].
In order to solve this problem, boosted WL (WL and WWL) write-
assist technique can be used. When the WL boosting technique is
applied to the PG9T SRAM cell, the higher voltage can be transferred
to storage node Q to reduce the write delay.
C. Bit Interleaving Scheme
A bit interleaving scheme is necessary for nanoscale SRAM arrays
to minimize the occurrence of multiple bit errors, because the soft
error rate caused by α-particles increases with technology scal-
ing [10]. Error correction code (ECC) is a common in memories and
microprocessor caches for significantly reducing the external single
bit errors. However, the conventional ECC has very limited correction
capability, making it insufficient to protect memory in scaled tech-
nologies, which are vulnerable to multiple bit errors in a word [11].
In the bit interleaving scheme, on the other hand, neighboring bits are
arranged using different words, and then, column-based BL signals
are interleaved through multiplexers and detected by a single sense
amplifier. Thus, although the data flip occurs locally at the multiple
bits, the conventional ECC can easily recover the errors [10].
Fig. 2 shows the PG9T SRAM cell array during write “1” opera-
tion. In the row half-selected cells, the storage node Q floats for a
moment, but the data are maintained, because the write access time
is sufficiently short. In addition, in the column half-selected cells, the
storage node Q is strongly driven by the inverter and the data can
thus be maintained despite the charge sharing with the intermediate
node VX. Because only the cross point bit cell, which is located in
the selected row and column (write-selected cell), is accessed, the bit
interleaving scheme can be implemented without using a write-back
scheme in the PG9T SRAM architecture.
III. C OMPARATIVE A NALYSIS BASED ON 22-nm T ECHNOLOGY
In this section, the proposed PG9T SRAM cell is compared with
the previously proposed SRAM cells in 22-nm FinFET technology.
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Fig. 2. PG9T SRAM cell array and waveforms of data storage nodes in row
and column half-selected cell during write “1” operation.
The SRAM cells were verified by Monte Carlo simulations for
statistical analysis. In the simulation, the Vth variation was modeled
to follow Gaussian distribution whose standard deviation (σV th ) is
expressed as
AV t
σV th = √ (1)
Length × Width
where the Pelgrom coefficient A V t is assumed to be 1.8 mV · μm
[12] to consider all variation sources including RDF, LER, work
function variation, and fin width and gate length variations [13].
The simulation was performed using a qualified BSIM-CMG 106.1.0
model fitted with a commercial device based on the 22-nm FinFET
technology [14]. In the transient simulations performed in this brief
to determine the delay, energy consumption, and sensing yield, a
junction capacitance of 256 cells per BL and a wire capacitance of
0.16 fF/μm [15] were employed. The target yield was set to 6σ to
achieve sufficiently stable operations [16].
A. Bit Cell Area
Fig. 3(a) and (b), respectively, shows the layout of a single bit
cell of the previous 9T and PG9T SRAM based on 22-nm FinFET
technology. The layout of the previous 9T SRAM cell in Fig. 3(a) is
different from that in [8] for area minimization with considering the
layout rule restriction in 22-nm FinFET technology, such as width
quantization effect, single gate orientation, and regular gate pitch.
Fig. 3(c) shows the metal layout of the PG9T SRAM cell. It is
assumed that the single fin is used for all devices in the SRAM cells.
The number of metal layers is minimized by using local interconnects
(LI1 and LI2) [17]. Four metal layers are used to route the control
signals along the rows and columns. VDD and VSS are routed by
metal 1 in the column direction; BL and WWL are internally routed
by metal 2 in the row direction; BL and WWL are routed again by
metal 3 in the column direction; VVSS is also routed by metal 3
in the column direction; and WL, WLPU, and WLPD are routed by
metal 4 in the row direction.
Fig. 4 shows the comparison of the bit cell area and estimated
macrolevel area. The bit cell area of the PG9T SRAM cell is
29%, 13%, and 12% smaller than those of the CP10T, PPN10T,
and previous 9T SRAM cells, respectively. The CP10T SRAM cell
has the largest area because of many transistors and control signals.
In spite of many transistors, however, the PPN10T SRAM cell has
a relatively smaller area due to the small number of control signals.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO. 3, MARCH 2017
Fig. 3. Layout of (a) previous 9T and (b) proposed PG9T SRAM cell without metal layers and (c) with metal layers based on 22-nm FinFET technology.
Fig. 4. Bit cell and macrolevel area based on 22-nm FinFET technology.
Fig. 5. (a) Read stability yields, (b) RSNMs at different process corners,
and (c) read delays of read-decoupled SRAM cells.
The previous 9T SRAM cell has a larger layout area than the PG9T
SRAM cell, because WWL controls both pMOS in transmission gate
and nMOS in read/write access transistors; thereby sufficient gate
tip-to-tips are required, which is not the case in the PG9T SRAM
cell. For the estimation of macrolevel area, it is assumed that the
write-back scheme [18] is used only for the 8T SRAM, and the
peripheral circuit areas are the same for the other SRAMs. Referring
to [8] and [18], the peripheral circuit areas of the 8T and previous
9T SRAM are obtained, and then, macrolevel areas were estimated
by adding the obtained peripheral circuit areas to the cell array areas
for the read-decoupled SRAMs. As a result, the PG9T SRAM has
15%, 6%, and 6% smaller macrolevel area than CP10T, PPN10T, and
previous 9T SRAMs, respectively.
B. Read Stability and Delay
The read static noise margin (RSNM) [19] was used as the
read stability metric. The read stability yield is measured in μ/σ
and obtained from the Gaussian distribution of the RSNMs for
10 000 Monte Carlo samples. All of the read-decoupled SRAM cells
(8T, CP10T, PPN10T, previous 9T, and PG9T) have the same
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1185
Fig. 6. (a) Write ability yields of read-decoupled SRAM cells. (b) WWTVs
of proposed PG9T SRAM cell at different process corners.
RSNMs, which are nearly equivalent to the hold static noise margins,
because the read disturbances are eliminated by decoupling the
storage nodes from the BLs. They all achieve the target read stability
yield of 6σ , even in the low voltage region without the use of a read
assist circuit, as shown in Fig. 5(a). The minimum supply voltage
(VDD,min ) is defined as the voltage where 6σ read stability yield
is ensured. The SRAM cells have the same VDD,min of 0.32 V,
because they all use read-decoupled SRAM cell structure. Fig. 5(b)
shows the RSNM of the PG9T SRAM cell at different process
corners (FS, TT, and SF). At TT corner, the inverters in the latch are
low-skewed because of greater electron mobility than hole mobility.
FS corner makes the inverters further low skewed while the SF corner
cancels out the originally low-skewed effect by making them high
skewed from the TT corner. Therefore, the RSNM is the smallest
at FS corner. Fig. 5(c) compares the 6σ worst read delay of the
proposed PG9T SRAM cell with those of the previously proposed
SRAM cells for different supply voltages. The PPN10T SRAM cell
has the shortest read delay, because it has small BL capacitance and
its differential BL pair requires only small voltage development for
correct sensing. However, the shortest read delay of the PPN10T
SRAM is worthless, because the write delay is much longer than the
read delay, as further discussed in Section III-C. The previous 9T
and PG9T SRAM cells have the same read delays, because they use
identical read buffers.
C. Write Ability and Minimum Required Boosted WL Voltage
The write abilities of the read-decoupled SRAM cells are compared
based on the WL write trip voltage (WWTV) [19]. The write ability
yield is measured in μ/σ and obtained from the Gaussian distribution
of the WWTVs for 10 000 Monte Carlo samples. Fig. 6(a) compares
the write ability yields for low operating voltages. The write ability
yields in the CP10T and PPN10T SRAM cells are significantly
poorer than that in the 8T SRAM cell owing to the stacked access
transistors in the former. On the other hand, the write ability yields
of the previous 9T and PG9T SRAM cells are higher, because their
disconnected latches facilitate the write operation despite the stacked
access transistors. Fig. 6(b) shows the WWTVs of the PG9T SRAM
cell at different process corners (FS, TT, and SF). The WWTVs is
1186 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO. 3, MARCH 2017
Fig. 7. (a) Minimum Vboost for 6σ write yield and (b) WL energy
consumption per write operation at VDD,min using WL boosting scheme
in [20].
Fig. 8. Energy consumption per (a) read and (b) write operation.
the largest in FS corner and the smallest in SF corner due to the
stacked nMOS write path.
In the low voltage region, none of the read-decoupled SRAM
cells is able to achieve the 6σ target write ability yield without an
assist circuit. The WL (WL and WWL) boosting-assist technique
is an appropriate means of achieving the target write ability yield
and speeding up the write operation in these cells, as explained
in Section II-B. However, this technique requires a larger area and
increases the power consumption. It is thus important to minimize the
required WL boosting voltage (Vboost ). The minimum WL boosting
voltage (Vboost ) required to ensure 6σ write ability yield is shown in
Fig. 7(a). In the CP10T, previous 9T, and PG9T SRAM cells, both
WL and WWL are boosted. The minimum required WL boosting
voltage for the PG9T SRAM cell is comparable to that for the
previous 9T cell, and these two are the lowest among those for
all the SRAM cells. Conversely, the CP10T and PPN10T SRAM
cells require the highest WL boosting voltage. Although the target
write ability yield is satisfied by using the boosted WL scheme, the
PPN10T SRAM cell has a write delay of 1.02 μs at VDD = 0.32 V,
which is significantly longer than the read delay. The PPN10T SRAM
cell is thus incapable of proper operation at a low VDD when
using 22-nm FinFET technology.
With the implementation of the capacitive coupling WL boosting
scheme in [20], the WL energy consumption per the write operation
was measured, as shown in Fig. 7(b). The WL energy consumption of
the PG9T SRAM is comparable with that of the 8T SRAM because
of the small amount of Vboost . Although the previous 9T SRAM
requires the lowest Vboost among all the SRAMs, its WL energy
consumption is higher than that of the PG9T SRAM, because it has
larger WL (WL and WWL) capacitances.
D. Energy Consumption and Standby Leakage Power
The average energy consumptions per read or write operation of the
SRAMs were measured and compared for different supply voltages
using the worst case data pattern. A 4:1 bit interleaving scheme and
256 rows × 128 columns of the cell arrays were assumed.
Fig. 8(a) compares the read energy consumptions of the different
SRAMs. As the supply voltage reduces, the read energy consumption
also reduces. When VDD scales down below 0.4 V, however, the read
energy consumption increases due to the leakage current caused by
exponentially increasing read delay, as shown in Figs. 5(c) and 8(a).
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TABLE I
C OMPARISON OF L EAKAGE P OWER AT VDD,min
This shows that the minimum read energy can be achieved when the
SRAM operates with the supply voltage slightly larger than VDD,min ,
specifically 0.4 V. In the previous 9T SRAM, BL discharge occurs
in both the 96 unselected and 32 selected columns. However, in the
PG9T SRAM, BL discharge occurs only in the 32 selected columns
because of the column-based VVSS scheme. Due to the elimination
of unnecessary BL discharge from the unselected columns, the read
energy consumption of the PG9T SRAM is 30% and 45% lower
than those of the CP10T and previous 9T SRAMs, respectively, at
VDD,min . The column-based VVSS scheme can also be applied to the
previous 9T SRAM cell and this is further discussed in Section III-E.
Fig. 8(b) compares the write energy consumptions of the different
SRAMs when using the WL boosting scheme in [20] for ensuring 6σ
write ability yield. The write energy consumption is dominated by the
column-based signals, because the number of the selected columns
is much larger than that of the selected row in the 256-row ×
128-column cell array with the 4:1 bit interleaving scheme. In the
previous 9T SRAM cell, two row-based control signals (WL and
WWLB) and two column-based control signals (WWL at the gates
of MAW and MNP) are activated during the write operation. In the
proposed PG9T SRAM cell, on the other hand, three row-based
control signals (WL, WLPU, and WLPD) and a column-based control
signal (WWL) are activated during the write operation. Thus, the
PG9T SRAM consumes less write energy than the previous 9T
SRAM due to the smaller number of activated column-based signals.
The write energy consumption of the PG9T SRAM is 49% and
17% lower than those of the CP10T and previous 9T SRAMs,
respectively, at VDD,min .
The standby leakage power (Ileakage ) is measured at VDD,min
where the 6σ hold stability yield is ensured. In the standby mode of
the SRAMs, the BLs are set to a high impedance mode and the WLs
are deactivated. Table I shows the comparison of the leakage power.
The CP10T, PPN10T, previous 9T, and PG9T SRAMs consume
similar leakage power, because they use the similar stacked write
access transistors. The 8T SRAM consumes the highest leakage
power, which derives from the single access transistor.
E. Column-Based VVSS Scheme and Sensing Yield
In a single-ended SRAM with the column-based VVSS scheme, a
data-dependent leakage current undesirably discharges the precharged
BL. The BL noise particularly deteriorates when all the column half-
selected cells store “1”s. Because all the VVSSs in the column half-
selected cells are activated, many leakage paths are generated, and
the BL voltage difference between the read “1” and read “0” cases
is thus reduced. This may cause a sensing error. Correct detection of
the stored data requires sufficient BL voltage difference between the
two cases. The sensing yield presented in [21] is used as a measure
of how accurately the sensing scheme reads the stored data with Vth
variation. The target sensing yield in this case is also 6σ , which
is sufficiently high. With this target yield, the sensing scheme can
accurately detect the BL voltage without errors.
Column-based VVSS can also be applied to the previous SRAM
cell. In this case, the sensing yield of the previous 9T cell reduces and
becomes the same as that of the PG9T SRAM cell. This is because the
same bias condition of the column half-selected cells in the previous
9T and PG9T cells yields the equivalent leakage current. The read
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO. 3, MARCH 2017
Fig. 9. Comparison of sensing yields for different supply voltages.
TABLE II
C OMPARISON IN 22-nm F IN FET T ECHNOLOGY AT VDD,min
energy becomes the same as that of the proposed PG9T SRAM owing
to the same WL swing and BL discharge. In the aspects of the bit
cell area and energy consumption per write operation, the PG9T
SRAM cell outperforms the previous 9T SRAM cell with column-
based VVSS, because they are independent of the direction of VVSS.
The energy per read operation can be significantly reduced by
a column-based VVSS, as noted in Section III-D. However, the
sensing margin is slightly degraded when the same inverter sensing
scheme is used for this case, as shown in Fig. 9. Nevertheless, this
can be resolved by reducing the variation of trip voltage of the
inverter sensing scheme through the use of more fins in the sensing
scheme. Provided that the number of fins of the sensing scheme is
higher than three (Nfin,N = Nfin,P = 3), the sensing yield of the
PG9T SRAM cell would easily achieve the 6σ target at the minimum
supply voltage, with a very small area penalty. The proposed PG9T
SRAM cell is, therefore, designed with a column-based VVSS to
significantly reduce the energy consumption, while achieving the
target sensing yield.
IV. C ONCLUSION
We proposed a PG9T SRAM cell characterized by smaller area,
improved variation tolerability, and low energy consumption com-
pared with previously proposed SRAM cells. Table II summarizes
the performance between previous and proposed SRAM cells based
on the 22-nm FinFET technology at the minimum operating voltage.
By cutting off the path from the power sources to the storage nodes,
only the BL of the cell drives the storage node, thus affording
improved write ability. The energy consumption per read operation
of the proposed SRAM cell is much lower than those of the previous
SRAM cells thanks to the elimination of unnecessary BL discharge
through the use of a column-based VVSS. In addition, the proposed
SRAM cell has a smaller area and consumes less energy per write
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1187
operation than the previous 9T, CP10T, and PPN10T SRAM cells.
These features of the proposed SRAM cell afford a high integrated
memory, better noise immunity, and low energy consumption.
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