A Very-High Output Impedance Current Mirror for
Very-Low Voltage Biomedical Analog Circuits
Louis-François Tanguay, Mohamad Sawan, and Yvon Savaria
Polystim Neurotechnologies Laboratory, Electrical Engineering Department
Ecole Polytechnique de Montreal
Montreal, Canada.
louis-francois.tanguay@polymtl.ca
Abstract—In this paper, we present the design of a new
very-high output impedance CMOS current mirror with
enhanced output voltage compliance. The proposed current
mirror uses MOS current dividers to sample the output current
and a feedback action is used to force it to be equal to the input
current; yielding very high impedance with a very large output
voltage range. The proposed implementation yields an increase
of the output impedance by a factor of about gm ro compared
with that of the super-Wilson current mirror, thus offering
a potential solution to mitigate the effect of the low output
impedance of ultra-deep submicron CMOS transistors used in
sub 1-V current mirrors and current sources. A NMOS version
of the proposed current mirror circuit was implemented using
STMicroelectronics 1-V 90-nm CMOS process and simulated
using Spectre to validate its performance. The output current
is mirrored with a transfer error lower than 1% down to an
output voltage as low as 80 mV for an input current of 5 µA,
and 111 mV when the input current is increased to 50 µA.
I. I NTRODUCTION
With recent advances in CMOS technologies, the possibility
to integrate radio-frequency (RF) circuits, baseband signal
processing, and even sensors on a same chip has led to a
tremendous growth of interest in implantable smart medical
implants and their applications. Ultra-low power consumption
and low supply voltage of 1 V or less are critical to allow using
miniature batteries that can last over a long period. Recent
nano-CMOS technologies are found to be very appropriate to
reach this goal, since nano-CMOS transistors can be operated
in weak inversion up to the GHz region with reasonnable
gain, and their low threshold voltage allows designing analog
circuits that can operate under 1 V. However, the shrinking of
the supply voltage combined with the low output resistance
of transistors in these nano-CMOS processes make it very
difficult to implement current mirrors (CMs) and current
sources or sinks that offer very-high output impedance over a
large output voltage range.
Several biomedical circuits demand large-voltage compli-
ance current sources and current mirrors with a high output
impedance. In implantable microstimulators, stimulation using
precise current sources and sinks provides greater control over
the injected charge [1]. Large-voltage compliance high output
impedance CMs can also be used in low-power integrated
bioamplifiers [2] to improve the common-mode and power-
supply rejection ratios (CMRR and PSRR) of differential
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stages, as well as the DC gain factor. Finally, such CMs are
required in the charge-pump of phase-locked loops and fre-
quency synthesizers dedicated to implantable communication
modules operating under very low supply voltage [3]. Using
large-voltage compliance high output impedance CMs results
in accurate Up/Down current matching and minimum variation
of the output current magnitude over a wider voltage range,
thus minimizing reference spurs and reducing the level of
phase-noise in the output spectrum.
Under very low supply voltages, the reduction of output
voltage headroom and limited output impedance of the typical
cascode connection is unacceptable and other architectures
must be investigated. One technique consists in using an
operational amplifier (op-amp) in a feedback loop to force
the drain voltages of the output transistors and that of the
reference current source to be equal [4]. This results in
a very high output impedance, but it is accompanied with
a degradation of the bandwidth, and the op-amp must be
carefully compensated in frequency in order to achieve stable
operation. Recently, a regulated cascode CM that offers much
higher output impedance than the conventional cascode CM
was first presented in [5], and an all-cascode double nested
version was later presented in [6]. As shown in figure 1(a),
the downside of this CM is that the input of the common-
source amplifiers used in the feedback loops are connected to
the drain of the transistors M2-M4 performing the mirroring
action. Therefore, these transistors must be operated deeply in
weak inversion to allow sufficient loop gain at low CM output
voltages, thus limiting the bandwidth and increasing the area
of the CM. Finally, a low-voltage CM architecture based on
the super-Wilson CM was presented in [7]. The high-swing
super-Wilson CM, shown in figure 1(b), can operate on a
very low supply voltage of one diode drop plus two saturation
voltage, and it features a wide output-voltage swing, down to
two saturation voltages.
In this paper, we present the design of a new very-high
output impedance current mirror inspired from the high-swing
super-Wilson CM [7]. The output impedance of the proposed
CM is a factor gm ro higher than that of the high-swing
super-Wilson CM, and its output voltage compliance is also
improved. In Section II, the design and implementation of this
new CM is presented. In Section III, simulation results are
reported, and conclusions are drawn in Section IV.
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 IB IB IB IB IIN IB
IOUT IOUT

Vcn M5 M7 Vcn

IIN
M1 M3 M6 M1 M3 M5
M6 M8

M2 M4 M2 M4

(a) (b)

Fig. 1. a) All-cascode NMOS double nested regulated cascode CM [6], and b) High-swing super-Wilson CM [7].

II. C URRENT MIRROR ARCHITECTURE
A. Background
The new current mirror proposed in this paper is inspired
from the high-swing super-Wilson CM presented in [7],
and shown in figure 1(b). The high-swing super-Wilson CM
achieves a high output resistance by using negative feedback:
the current mirror formed by M2-M4 samples the output
current IOU T and compares it with the input current source
current IIN . As a result, the gate voltage of M3 is adjusted to
ensure it sinks a current equal to IIN . The output resistance is
directly proportional to the magnitude of the loop-gain of the
feedback action from the output current IOU T to the gate of
the output transistor M3. This loop-gain can be attributed to
transistor M2 which, in combination with current source load
IIN , form a common-source amplifier used to maintain the
gate voltage of output transistor M3 such that IOU T is equal
to IIN .
Assuming that the output resistance of the current sources
is very large and that transistors M2 and M4 are saturated, the
output resistance rout of the high-swing super-Wilson CM of
figure 1(b) can be approximated as:
rout ≈ gm2 ro2 ro3
where gm2 and ro2 are respectively the transconductance and
the output resistance of transistors M2 and ro3 is the output
resistance of transistors M3. In this equation as well as in
the remaining of this paper, body effect, drain-induced barrier
lowering (DIBL), and hot carriers effects are neglected for the
sake of simplicity, since the goal is to give an idea on the
order of magnitude of rout rather than finding an exact value.
The interested reader can refer to [8] for an in depth treatment
of these short channel effects.
In the high-swing super-Wilson CM presented above, a
diode-connected transistor M1 is used to reduce current
mismatch between IIN and IOU T by keeping the drain of
mirroring transistors M2-M4 approximately to the same volt-
age. However, the output resistance of this diode-connected
transistor is only 1/gm1 . Therefore, an increase of the loop-
gain -hence of the output impedance- on the order of gm ro
would result if the diode connection of transistor M1 was
replaced with a cascode one. Unfortunately, doing so would
introduce an undesired current offset since the drains of M2-
M4 would not be at the same voltage anymore. The goal is
then to find a way to maintain a high impedance at the drain
of M1, without breaking the drain symmetry of the current
mirror formed by M2 and M4.
IB IOUT IB
VD,M1
IIN M1 M5 M3
VD,M2 VD,M4
M2 M4
VB
Fig. 2. Proposed high output impedance low-voltage CM circuit schematic.
B. Proposed very-high output impedance current mirror
(1)
The new high output impedance CM presented in this paper
is shown in figure 2. The main idea is to increase the loop gain
by a factor gm ro by cascoding transistor M1 while maintaining
the drain symmetry of the current mirror formed by M2 and
M4. Let us first consider only the bias-loop circuit formed
by transistors M1 to M4 and the two current sources IB ,
and forget about the input current source IIN and the output
transistor M5 for the moment. With the output transistor M5
disconnected out from the loop and with no input current
applied at the drain of transistor M2 (IIN = 0), the steady-
state drain voltage of M1, VD,M 1 , is equal to that of M3,
and is thus equal to their gate bias voltage VB . Furthermore,
mirror transistors M2 and M4 are at the same saturation level
IF /IR (the ratio of their forward current component to their
reverse current component [9]). As a consequence, their drain
voltages are identical: VD,M 2 = VD,M 4 .
Now let us see what happens if M5 closes the feedback loop
and a current IIN is forced in the drain of transistor M2. Since

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M2 is biased with a gate voltage VB to sink a current IB , the
current applied at its drain will disturb this steady state and
result in an increase of its drain voltage. As a consequence, the
gate-source voltage of transistor M1 will be reduced, resulting
in a rapid increase of its drain voltage to allow current IB to
keep flowing. This voltage being applied to the gate of the
output transistor M5, the output current will increase and so
will the bias voltage VB , which is determined by the sum of the
drain voltage of M4 and the gate-source voltage of M3: VB =
VD,M 4 + VGS,M 3 . The steady state will be reached when the
current through M4 is equal to IIN + IB , such that the current
forced out of the source of M1 is equal to ID,M 2 − IIN = IB .
At that point, the saturation level of transistors M2 and M4 is
exactly equal to IF /IR = 2 + IIN /IB , and their drain-source
saturation voltage VDS,sat is identical as well. Therefore, the
drain symmetry of the current mirror formed by M2 and M4
is maintained and there is no current offset between the output
and input currents; the output current IOU T is exactly equal
to IIN .
C. Proposed current mirror characteristics
1) Output Impedance: The output impedance of the pro-
posed CM can be found using a test voltage source vx at
the output and finding the resulting current ix flowing into
the output port. If we assume that the output resistance of the
current sources IB and IIN are infinite, we find that the output
resistance of the current mirror is given by:

vx 1 go5 gm5
rout = = · 1+ +
ix go5 (gm4 + go4 ) gm4 + go4
gm5 gm1 gm2 + gm1 go2 + gm2 go2
 of both M2 and M4 is equal to IF /IR = 2 + IIN /IB .
+ · (2)
gm4 + go4 go1 go2
where gm1 , gm2 , gm4 , gm5 and go1 , go2 , go4 , go5 are respec-
tively the transconductances and the output conductances of
transistors M1, M2, M4 and M5. If we further assume that
the transconductance gm of the transistors is much larger than
their output conductance go , equation 2 reduces to:
rout ≈ gm1 gm2 ro1 ro2 ro5
Comparing this result with (1), we see that the proposed
implementation produces an increase of the output impedance
by a factor of gm ro over that offered by the high-swing super-
Wilson current mirror. The output resistance of the proposed
CM is equal to that of the regulated cascode, but its output
voltage compliance is larger, as will be explained below.
2) Output voltage compliance: The output voltage compli-
ance is the range of output voltages over which the current
mirror will provide an output current IOU T that corresponds
to the input current IIN . In the proposed CM, since the
transconductance gain gm5 of the active output transistors M5
is much larger than its output conductance go5 , the correction
voltage required at its gate to compensate for an output
voltage change is relatively small. This remains true unless
M5 enters the deep triode region where the value of its output
conductance approaches that of its transconductance. Still, the
very high loop gain from the drain of M4 -where the output
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current is sampled- to the gate of output transistor M5 allows
the CM to maintain a high output resistance even when the
output transistor enters the triode region.
In the regulated cascode CM shown in figure 1(a), the input
of the common-source amplifiers used in the feedback loops
are connected to the drain of transistors M2-M4 performing the
mirroring action. Therefore, the minimum output voltage must
be maintained above VGS + VDS,sat to allow transistors M6
and M8 to turn on and provide sufficient loop gain. Therefore,
transistors M6 and M8 are usually operated deeply in weak
inversion to minimize the required minimum VGS and thus
enhance the output voltage compliance. The proposed CM
does not suffer from this drawback, since the output current
of the CM is sampled at the drain of transistor M4 which
is biased at the edge of the saturation region. This current
sampling method combined with the very high loop gain allow
the CM to maintain a very-high output impedance as long as
the output voltage is a little over VDS,sat .
3) Auxiliary bias current sources IB : The value of the two
bias current sources IB used in the proposed CM determines
its output voltage range and influences its output resistance.
The minimum output voltage is for the most part fixed by the
VDS,sat of transistors M2 and M4, which in return depends
on their saturation ratio IF /IR . In order for these transistors
to mirror accurately the input current to the output, they
must operate in saturation, such that their forward current
component is much larger than their reverse component; that is
IF >> IR . In the proposed circuit configuration, all transistors
have the same aspect ratio. Therefore, the saturation ratio
Hence, making IB 10 times smaller than IIN will ensure that
M2 and M4 are always at the edge of the saturation region
[9]. The value of current sources IB can be either fixed or
adaptive, but making them equal to IIN /K will ensure that
the saturation level of transistors M2 and M4 is always equal
to IF /IR = 2 + K, regardless of the amplitude of the input
current IIN .
(3)
III. S IMULATION R ESULTS
The proposed current mirror circuit was implemented using
STMicroelectronics 1-V 90-nm CMOS process. A minimum
channel length of 0.25 µm is used in the proposed CM for
good matching, and identical device geometry is ensured by
using unit transistors with an aspect ratio W/L = 0.5/0.25
that are either put in parallel or in series to obtain different
device sizes. Figure 3 shows the output current as a function of
the output voltage for the enhanced low-voltage CM presented
in this paper when IIN is swept from 5 µA to 50 µA in 10 µA
steps. IOU T is maintained within 1% of the value of IIN for
output voltages as low as 80 mV at 5 µA, and 111 mV at
50 µA. The output impedance of the proposed CM is shown
in figure 4, where it is plotted as a functuion of the output
voltage for an input current of 10 µA. The output impedance
rapidly increases when VOU T is above 100 mV to peak at
about 200 MΩ at VOU T = 500 mV.
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 25.0
50.0

20.0
40.00
M3(0.1931V,19.98uA)
Output Current (uA)

M2(0.1622V,19.98uA)

Output Current (uA)

30.0 15.0
M1(0.0998V,19.98uA)

20.00
10.0

10.00
5.0
High-swing super-Wilson CM
0.0 Regulated Cascode CM
0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1.0 Proposed CM

Output Voltage (V) 0.0

0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1.0
Output Voltage (V)
Fig. 3. Output current variation as a function of the output voltage for the
proposed low-voltage CM. Fig. 5. Output current variation as a function of the output voltage for
the high-swing super Wilson CM [7], the regulated cascode CM [6], and the
1E9 proposed low-voltage CM.

1E8

be extended further by increasing the value of the bias current

Output Impedance (Ohm)

1E7
1E6
1E5
1E4
1E3
0 .1 .2 .3 .4
Output Voltage (V)
Fig. 4. Output impedance of the proposed current mirror for an input current
of 10 µA.
Finally, figure 5 shows the output current as a function of
the output voltage for the high-swing super-Wilson CM [7], for
the regulated cascode CM [6], and for the new CM presented
in this paper. All CMs were implemented using identical
transistor sizes and biased to obtain a similar bandwidth of
200 MHz. The input current of the CMs was set to 20 µA,
and the output voltage was swept over the supply range 0 V
to 1 V. The output impedance of the regulated cascode and
the proposed CM is significantly higher than that of the high-
swing super-Wilson due to the higher loop gain of the feedback
action. Figure 5 also shows that the proposed CM outperforms
both other CMs in terms of the output voltage at which the
output current drops by 1% below IIN .
IV. C ONCLUSION
In this paper, we presented the design of a new very-high
output impedance CM using output current sampling that has
low input and output voltage requirements. Implemented using
STMicroelectronics 1-V 90-nm CMOS process, simulations
show that the value of the output current is maintained within
1% of that of the input current for an output voltage as low
as 80 mV at 10 µA and 111 mV at 50 µA. The operating
bandwidth of the proposed CM is over 200 MHz, and it can
sources ICP /K. Such performances make the proposed CM a
good candidate for the design of ultra-low power, low-voltage
analog circuits.
ACKNOWLEDGMENT
The authors would like to acknowledge financial support
from FQRNT, Micronet R&D, and the Canadian Research
Chair on Smart Medical Devices. Thanks are also due to CMC
.5 .6 .7 .8 .9 1.0
Microsystems for the design tools and fabrication support.
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