2019 International Conference on Computer, Control, Electrical, and Electronics Engineering (ICCCEEE)
Series Parallel Cascaded H-Bridge Inverter Based
on A Simlpe Staircase Modulation
1st Ahmed Abdelghafar Awad
Electrical Engineering Department
Karary University
Omdurman, Sudan
Ahmed.a.alghaffar@gmail.com
3rd Hesaham Norallah
Electrical Engineering Department
Karary University
Omdurman, Sudan
heshamnorallah@gmail.com
Abstract—This paper presents the main types of a series-
parallel cascaded H-bridge inverter. It consists of H-bridge
cells, and an inverter which output is a multilevel voltage by
adding the dc voltage sources in series and parallel. A simple
staircase modulation is used to obtain on-off of transistors used
in series-parallel H-bridge multilevel inverter. The modulation
technique used in this paper can calculate the independent
switching angles more simply than the traditional method, and
can be applied to all kinds of multilevel inverters. The
proposed inverter topology results from implementation of
optimum switching angles in low total harmonic distortion
values in the phase and line voltage waveforms. The circuit
configuration, theoretical operation, is also discussed in this
paper. PSIM, PROTEUS-V8 based simulation results are
obtained, which are consistent with the experimental results.
Keywords—multilevel inverter, series-parallel H-bridge
inverter, staircase modulation, angle level control
I. INTRODUCTION
Few years ago, the power electronics converters
became the important types of electrical technology,
because it used in all aspects of life applications such as
residential, commercial, industrial, transportation, utility
systems, aerospace and telecommunications systems[1, 2]
.A DC to AC converter is also called an inverter, and it is
divided into two types, two-level inverter and multilevel
inverters. A voltage source inverter that produces voltage
levels 0 or is called a two-level inverter. To obtain
high-quality output voltage or current of this type of inverter
requires high switching frequencies (3 kHz-10 kHz). In
high-voltage applications, the two-level inverter has
limitations, mainly due to switching losses, switching device
voltage rating constraints, and high electromagnetic
interference (EMI)[3] . In response to a growing demand
for high-power inverters, multilevel inverters have attracted
attention from academia as well as industry. Among the
best-known topologies are: the diode clamped inverter, the
flying capacitor inverter and the H-bridge cascade inverter
[4-7]. The benefit of these circuits is to obtain a better high-
voltage waveform using low voltage switching devices. As
the rule, series connected devices are switched sequentially,
generating an output voltage modality which contains
defined discrete steps. The general multilevel inverter
structure is used to obtain a sinusoidal voltage from several
voltage levels, typically capacitor voltage sources.
978-1-7281-1006-6/19/$31.00 ©2019 IEEE
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2nd Othman Hassan Abdalla
Electrical Engineering Department
Karary University
Omdurman, Sudan
othman313@gmail.com
4th Mohamed Ismail Jibril
Electrical Engineering Department
Karary University
Omdurman, Sudan
maxamedmij@gmail.com
The attractive features of multilevel inverters can be
summarized as follows: they can generate output voltage
with extremely low distortion and lower compared to
conventional two-level inverters at the same switching
frequency; the blocking voltage of each switch is clamped to
a divided capacitor link voltage level and they generate a
smaller common mode (CM) voltage, thus reduce motor
bearing stresses. In addition, by using sophisticated
modulation methods, any CM voltage can be eliminated [8,
9]. The main disadvantages of the multilevel inverters are:
they require a large number of diodes; control becomes
complex with an increased number of levels; several DC
voltages are required, which are usually provided by
capacitors and balancing the capacitor voltage is a challenge
[10].
Cascaded H-bridge multilevel inverters (CHB-MLIs) are
sub-divided into two types: equal DC source and unequal
DC source. The major disadvantage of CHB-MLIs is that
they require a greater number of power semiconductor
switches devices. Each switch needs a concerning gate drive
and protection circuits. This implies that the universal
system to be more expensive and complex.
To avoid this drawback of CHB-MLIS the series-parallel
cascaded H-bridge will be used for power applications [7,
11-13].
Control strategies of a multilevel inverter are shown in
Fig.1. Pulse width modulation techniques and selective
harmonic elimination that are used in series-parallel
cascaded H-ridge inverter are difficult and complicated [13-
16].
In this paper a simple staircase modulation is used to
obtain on-off of transistors used in series-parallel H-bridge
multilevel inverter. The contribution in this work is that
the proposed staircase modulation technique calculates the
independent switching angles more simply than the
traditional methods.
II. SERIES PARALLEL H-BRIDGE INVERTER
A. Series Parallel H-bridge Inverter with Equal DC source
The circuit configuration of a single-phase L Levels
Series Parallel H-bridge -MLI with equal DC sources is
shown in Fig.2, Fig.3 and Fig.4 respectively. The
relationship between levels of inverters and the number of The total number of the devices (IGBT) used in a Series
DC source (Single-phase H-bridge) is given by: Parallel H-bridge-MLI with an unequal DC source can be
given by:
(1)
(5)

Vdc
Multilevel Inverter Control strategies
S1 S3
Vdc S a1
Vdc S b1 /RDG

Sa 2
Fundamental Switching Frequency High Switching Frequency PWM
Sb2 S4 S2
nearest level Selective Harmonic Space Vector Selective Harmonic Sinusoidal Vdc San
control Elimination PWM Elimination PWM PWM S bn

Level shifted Phase shifted

Fig. 2. Proposed topology of series-parallel H-bridge inverter with equal
DC source and horizental increase..

Alternative Phase
Phase opposite
opposite disposition In-phase disposition
disposition A
Vdc T11 T31
Fig. 1. Control strategies of multilevel inverters. 
VH 1
Vdc T41 
where M is the number of dc source in cells. The levels L of Ta1 T21
the inverter are constantly odd number for the Series- Tb1
Parallel H-bridge-MLI. The phase voltage of the Series-
Parallel H-bridge-MLI is given by: H1
T1 2 T32
(2) Vdc

where VHN is the output voltage of H-bridge cells. 

VH 2
V dc Ta2 T42 T22 
The total number of devices (IGBT) used in a Series
Parallel H-bridge-MLI with an equal DC source can be Tb2
given by:
H2
(3)
Vdc T13 T33
where H is number of cells and P is the number of DC
voltage sources in series-parallel connection. 
VH 3
Vdc Ta3 T43

B. Series Parallel H-bridge Inverter with Unequal DC T23
source Tb3
The DC sources used of the series-parallel H-bridge -
MLI with equal DC sources transistor cells were illustrated H3
in section A above are all equals.
T1N T3N
Vdc
Fig.5 illustrates four configurations of the proposed
topological family of a series-parallel cascaded H-bridge 
inverter with unequal DC source. For a Series Parallel H- VHN
Vdc TaN T4N T2N 
bridge-MLI with an unequal DC source, the number of cells
can be reduced by adding more DC sources to the power Tb N
transistors cells. The last level of the series parallel H-bridge
with an unequal DC source is given by: HN N
(4)
Fig. 3. Proposed topology of series-parallel H-bridge inverter with equal
where V value of DC source in series-parallel. DC source and vertical increase..

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 .
A A
A
T11 T31 T11 T31
Vdc T11 T31 Vdc  Vdc 
 T41 VH1 VH1
T21
 T41 T21 
Vdc VH 1
Ta1 T41 T21  H1 H1
Tb1 2Vdc T T 3Vdc T12 T32
 
12 32
H1
2Vdc T T VH 2 3Vdc Ta2 VH2
Vdc T12 T32 T22
 T42 T22
a2 T 42 Tb 2 
 b2

VH2 H2 H2
Vdc T T 42 T22
a2 
Tb 2 N
N b- Level 15
a- Level 11
H2
Vdc T13 T33
 A A
T11 T31 T11 T31
Vdc T VH3
a3
Tb3
T43 T23  V dc

VH1 Vdc 
VH1
T41 T21  T41 T21 

H1 H1
H3 2Vdc T12 T32 T12 T32
Vdc  3Vdc 
S1 2Vdc Ta2 VH2 VH2
S3 T42 T T42 T22 
Tb2 22 
H2
Vdc Sa1 H2
 4Vdc T13 T 9Vdc T13 T33
Vdc S b1 VHN
33
 
Sa2  T43 T23 V 9Vdc Ta 3
VH3
4Vdc Ta3  H3 Tb 3
T43 T23 
Tb 3
Sb 2
S4 S2 H3 H3
Vdc San S N N N

bn c- Level 27
d- Level 45

Fig. 4. Proposed topology of series-parallel H-bridge inverter with equal Fig. 5. Topology samples of series-parallel H-bridge inverter with unequal
DC source and horizental-vertical increase.. DC source.

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 III. STAIRCASE MODULATION TECHNIQUE shown in Fig.5 for 11, 15, 27 and 45 levels of series-parallel
cascaded H-bridge multilevel inverter. Table I presents the
The principle of the method used in this paper is shown number of angles and THD for all. Fig7 to Fig.10 shows the
in Fig.6. The inverter phase voltage is created by a fifteen- PSIM simulation of the phase voltage 11-level, 15-level, 27-
level inverter. level and 45-level series-parallel cascaded H-bridge inverter
with unequal DC sources.

13Vdc 2

11Vdc 2

9Vdc 2
7Vdc 2
5Vdc 2
3Vdc 2
Vdc 2
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14

Fig. 6. Simple staircase modulation technique. Fig. 7. Phase voltage of the 11-level series parallel cascaded H-bridge
inverter with unequal DC sources.
The method’s algorithm relies on the fact that the
inverter phase voltage intersects with an original sinusoidal
waveform at equal points on the y-axis. It can be clearly
seen from g
Fig.6 that these equal points
are . Thus, angles
to can be calculated by:

(6)

(7)

(8) Fig. 8. Phase voltage of the 15-level series parallel cascaded H-bridge
inverter with unequal DC sources.

(9)

(10)

(11)

(12)

Fig. 9. Phase voltage of the 27-level series parallel cascaded H-bridge

(13) inverter with unequal DC sources.

In general, for anyy multilevel inverter, the angles

between intervals 0 to can be given by:

(14)

where n = 0,1,2,…,M-1 , M= (L-1)/2, and L is the level of

the inverter. The angles between intervals to are
calculated from complementary angles similar to equation
13.
IV. SIMULATION RESULTS
The general equation 14 of proposed method in this
paper can easily be extended to calculate the angles of any Fig. 10. Phase voltage of the 45-level series parallel cascaded H-bridge
level of this type of inverter. It was applied to the topology inverter with unequal DC sources.

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TABLE I. NUMBER OF ANGLES AND THD OF SOME SELECTIVE LEVEL microcontroller (PIC16F877A) was used to produce the
accurate gating signals at each calculated angle by using the
NUMBER OF ANGLES FOR HALF timer and interrupting modules of the microcontroller to
INVERTER LEVEL THD generate the gating signal at pre-calculated times related to
PERIOD ( ) the calculated angles.
11 5 7.59% The MOSFT Driver (IR2112) was utilized to amplify or
boost the 5V gating signal from the microcontroller to a
15 7 5.5% level that is required by the MOSFET power transistor.
27 13 3.02% The MOSFET Power transistor (IRF450) was also used
45 22 1.84%
as main building block of the H-bridge inverter cells. DC
power supply was used to provide the required power of the
circuit items. As aforementioned, the microcontroller used
V. COMPARISON WITH OTHER STRATEGIES micro C language. The voltage phase of the experimental
Control technology strategies of multilevel inverters are result of a fifteen-level series-parallel H-bridge inverter is
divided into two types: fundamental switching frequency shown in Fig. 12.
and high-frequency switching frequency. Until now, High-
frequency switching frequency for cascaded H-bridge with
unequal DC source has no direct rule. On the other hand, the
main types of fundamental switching frequency are selective
harmonic elimination (SHE) and nearest level control
(NLC).
In selective harmonic elimination method if the levels of
the inverter increase implied that the numbers of equation
also will be increasing, which lead more difficulty and
complication to solve these equations by using a numerical
method [17-21]. Nearest level control method is easier than
selective harmonic elimination, but it needs two signals to
calculate the angles [22-27].
The method proposed in this paper is simple and easy to
calculate the angles of transistors than compared to the other
two types. Based on the analysis given in the preceding
sections, the features and drawbacks for the selective
harmonic elimination, nearest level control and simple
staircase modulation (SSM) discussed in this paper are Fig. 11. Experimental prototype of a fifteen levels with unequal DC
summarized in Table II. sources.

TABLE II. COMPRESSION BETWEEN SHE, NLC AND SSM METHODS

Compression SHE NLC SSM

Control scheme complex Simple very simple

No of equation
Two Only one
per level (m)

Time processing Very slow slow fast

VI. EXPERIMENTAL RESULTS

The practical implementation of a cascaded multilevel
inverter with staircase modulation requires designing of a
circuit that can produce gating signals for each level at
accurate angles. Although there are other methods to realize
a staircase multilevel inverter, the proposed method is based
on calculating the accurate angles for each level, making the
implantation less complicated by utilizing the high-speed
processing capability and high timing accuracy of the
microcontroller. The fifteen-level series-parallel H-bridge
inverter with unequal DC sources was first implemented
with Proteus simulation software.
Following that, the circuit was realized with actual Fig. 12. Voltage phase of experimental result of a fifteen level series-
components as shown in Fig. 11. Additionally, a parallel H-bridge inverter-with unequal DC source

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 VII. CONCLUSION
In this paper, a simple staircase modulation for
multilevel inverters was discussed and was applied to a
series-parallel H-bridge multi-level inverter with unequal
DC sources. A series-parallel configuration inverter is
used to reduce the number of switches and to obtain
output has low total harmonics distortion. This
configuration of the inverter is simulated with the help of
PSIM- and PROTEUS software’s. The modulation
technique is applied for 45, 27, 15 and 11 level. A better
result with reasonable THD is obtained. The proposed
inverter in this paper can be used to produce more number
of voltage levels with the same number of power
semiconductor devices compared to the other types of
inverters. Subsequently, the size and power consumption
of driving circuit of the proposed inverter are reduced. In
this paper, the experimental results of fifteen -level series-
parallel inverter with unequal DC were matched with the
computer simulation results.
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