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Akbar Analog Electronics 05 2011
Akbar Analog Electronics 05 2011
Akbar Analog Electronics 05 2011
Lecture # 5 1
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Copyright 2004 by Oxford University Press, Inc.
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DC Bias Point
1 W
I D K n ( V GS V t )
2
2 L
V D V DD I D R D
V D V GS V t
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Copyright 2004 by Oxford University Press, Inc.
1 W
iD K n ( V GS v gs V t )
2
2 L
1 W W 1 W 2
iD K n ( V GS V t ) K n
2
( V GS V t ) v gs K n v gs
2 L L 2 L
First component is the dc bias current, second is the current component directly proportional to the applied
signal and last is proportional to square of input signal
1 W 2 W
K n v gs K n ( V GS V t ) v gs
2 L L
v gs 2 ( V GS V t ) 2 V OV
iD I D id neglecting last term.
W
i d K n ( V GS V t ) v gs
L
id W W
g m K n ( V GS V t ) K n V OV
v gs L L
2ID 2ID
g 2K '
W L ID , g
V GS V t
m n m
V ov
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Copyright 2004 by Oxford University Press, Inc.
2
Voltage Gain
vD V DD iD R D
vD V DD (I D id ) R D
vD V DD IDR D id R D V D id R D V D vd
v d id R D g m v gs R D
vd
AV g m R D
v gs
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Copyright 2004 by Oxford University Press, Inc.
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Copyright 2004 by Oxford University Press, Inc.
3
Separating DC Analysis & Signal Analysis
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(a) Neglecting the dependence of iD on vDS in saturation (the channel-length modulation effect); and (b) Including the effect of channel-length
modulation, modeled by output resistance ro = |VA| /ID.
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Example 4.10
First find ID and VD and then find gm, ro and Av from the following equations.
1 W
ID K n ( V GS V t )
2
(No gate current so V GS V D )
2 L
1
ID * 0 . 25 * ( V D 1 . 5 ) 2
2
VD V DD R D I D
ii ( v i v o ) / R G
W
g m K n ( V GS V t ) From slide 4
L
vi
R in VA
ii ro
ID
vo
Av g m ( R D || R L || r o )
vi
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Copyright 2004 by Oxford University Press, Inc.
Resistance = V/I=vgs/gmvgs
Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted but can be added between D and S in the T model of (d).
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Alternative T Equivalent Circuit Model
(a) The T model of the MOSFET augmented with the drain-to-source resistance ro. (b) An alternative representation of the T model.
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Exercise 4.23
1 W W 1 W 2
iD K n ( V GS V t ) K n
2
( V GS V t ) v gs K n v gs
2 L L 2 L
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Exercise 4.24, 4.25, 4.26, 4.27, 4.28 & 4.29
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1 W 2
I nC ox v ov
2 L 1
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Exercise 4.30
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ig 0 Rin RG
vsig vsig
vi Rin RG
Rin Rsig RG Rsig
RG Rsig
vi vsig
vo
Av
(a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the amplifier for small-signal analysis. (c) Small-signal
analysis performed directly on the amplifier circuit with the MOSFET model implicitly utilized.
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8
Common Source Amplifier with Resistance
(a) Common-source amplifier with a resistance RS in the source lead. (b) Small-signal equivalent circuit with ro neglected. It has been observed that ro
fortunately does not effect the operation significantly in discrete circuit amplifiers.
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Copyright 2004 by Oxford University Press, Inc.
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Common Gate Amplifier
(a) A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equivalent circuit of the amplifier in (a). (c) The common-gate amplifier
fed with a current-signal input.
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CS vs CG Amplifier
Three observations:
The gain for both configuration is identical, the over all gain for CG
is small by a factor of 1 + gmRsig.
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Exercise 4.34
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(a) A common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit model. (c) Small-signal analysis performed directly on the
circuit. (d) Circuit for determining the output resistance Rout of the source follower.
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Exercise 4.35
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Summary of Comparison
The common source is best suited for obtaining bulk of the gain required in the amplifier, multiple
stages can be used depending upon the requirement of the magnitude.
The performance can be improved if a resistance is introduced in the source terminal, however, gain
is reduced.
The common gate is useful for some specific applications due to its low input resistance.
The source follower finds application as a voltage buffer for connecting high resistance source to a
low resistance load in a multistage amplifier.
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Exercise 4.36 & 4.37
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(a) Capacitively coupled common-source amplifier. (b) A sketch of the frequency response of the amplifier in (a) delineating the three frequency bands
of interest.
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High Frequency Response
Determining the high-frequency response of the CS amplifier: (a) equivalent circuit; (b) the circuit of (a) simplified at the input and the output;
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(Continued) (c) the equivalent circuit with Cgd replaced at the input side with the equivalent capacitance Ceq; (d) the frequency response plot, which is that
of a low-pass single-time-constant circuit.
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Low Frequency Response
Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity, ro is neglected.
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Sketch of the low-frequency magnitude response of a CS amplifier for which the three break frequencies are sufficiently separated for their effects to
appear distinct.
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Exercise 4.38, 4.39 & 4.40
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CMOS Inverter
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Circuit Operation
Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b) graphical construction to determine the operating
point; (c) equivalent circuit.
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Circuit Operation
Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b) graphical construction
to determine the operating point; (c) equivalent circuit.
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Voltage Transfer Characteristics
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Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the
input goes high and C discharges through QN; (d) equivalent circuit during the capacitor discharge.
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Current in the CMOS Inverter
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Exercise 4.45 & 4.46
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The Depletion Type MOSFET
(a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol applicable for the case the substrate (B) is connected to the
source (S).
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The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = –4 V and kn(W/L) = 2 mA/V2: (a) transistor with current and
voltage polarities indicated; (b) the iD–vDS characteristics; (c) the iD–vGS characteristic in saturation.
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The Depletion Type MOSFET
The relative levels of terminal voltages of a depletion-type NMOS transistor for operation in the triode and the saturation regions. The case shown is
for operation in the enhancement mode (vGS is positive).
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Sketches of the iD–vGS characteristics for MOSFETs of enhancement and depletion types, of both polarities (operating in saturation). Note that the
characteristic curves intersect the vGS axis at Vt. Also note that for generality somewhat different values of |Vt| are shown for n-channel and p-channel
devices.
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