Professional Documents
Culture Documents
Lecture 9 - Clocking, Clock Skew, Clock Jitter, Clock Distribution and Some FM
Lecture 9 - Clocking, Clock Skew, Clock Jitter, Clock Distribution and Some FM
Mark McDermott
Electrical and Computer Engineering
The University of Texas at Austin
COMB Dout
Din
Delay
Delay
DFF DFF
CLK CLK’
Clock Skew =
CLK - CLK’
Clk
Tcycle Tuncertainty
Clk’
§ Most chips use repeaters to buffer the clock and equalize the
delay
– Reduces but does not eliminate skew
gclk
3 mm 3.1 mm 0.5 mm
clk1 clk3
clk2
1.3 pF
0.4 pF 0.4 pF
4 Power Supply
3 Interconnect
2 6 Capacitive Load
Devices
© J. Rabaey, 2002
§ Clock skew
– Spatial variation in temporally equivalent clock edges; deterministic + random, tSK
§ Clock jitter
– Temporal variations in consecutive edges of the clock signal; modulation + random
noise
– Cycle-to-cycle (short-term) tJS
– Long term tJL
© J. Rabaey, 2002
Clk_A
tSkew
Clk_B
tJitter
© J. Rabaey, 2002
2 4
d + thold
T: T + d ³ tc-q + tplogic + tsu so T ³ tc-q + tplogic + tsu - d
thold : thold + d ≤ tcdlogic + tcdreg so thold ≤ tcdlogic + tcdreg - d
d > 0: Improves performance, but makes thold harder to meet. If thold is not
met (race conditions), the circuit malfunctions independent of the clock
period! © J. Rabaey, 2002
9/27/18 10
VLSI-1 Class Notes
Negative Clock Skew
R1 R2
Clock and data flow in Combinational
In D Q D Q
opposite directions
logic
tclk1 tclk2
clk
delay
T
T+d
1 3
2 4
d<0
R1
Combinational
In
logic
tclk
clk
T
-tjitter +tjitter
© J. Rabaey, 2002
9/27/18 VLSI-1 Class Notes Page 12
Combined Impact of Skew and Jitter
Constraints on the minimum clock period (d > 0)
R1 R2
In Combinational
D Q D Q
logic
tclk1 tclk2
T
T+d
1
d>0
6 12
-tjitter
d > 0 with jitter: Degrades performance, and makes thold even harder
to meet. (The acceptable skew is reduced by jitter.)
© J. Rabaey, 2002
9/27/18 VLSI-1 Class Notes Page 13
Clock Skew Solutions
§ This can result in clock jitter. Careful analysis is required to validate the benefits.
PLL
9/27/18 19
VLSI-1 Class Notes
H-Trees
§ Fractal structure
– Gets clock arbitrarily close to any point
– Matched delay along all paths
§ Delay variations cause skew
§ A and B might see big skew
A B
§ Four levels of
buffering:
– Primary driver Repeaters
– Repeater
– Second-level clock buffer
– Gater
§ Route around
obstructions Typical SLCB
Locations
Primary Buffer
© J. Rabaey, 2002
© J. Rabaey, 2002
C1 C2
UP
Ref Charge R Bias
Fdbk PFD Pump Gen VCO
DN VCNTL
NBIAS
1/N
Clock
Network
Chip 1 Chip 2
Data
Digital Digital
System System
reference
fsystem = N x fcrystal clock
Divider PLL
PLL Clock
Buffer
fcrystal , 200<Mhz
Crystal
Oscillator
© J. Rabaey, 2002
9/27/18 VLSI-1 Class Notes 27
High Performance Processor Clock Network
4*XX
4*XX/N
4*XX*F/N
§ Issues
– Load of latch (driven by clock) is data-dependent (capacitance depends on
source voltage)
– Process variations
– IR drops and temperature variations
•Tapered H-Tree
•Source: An Integrated Quad-Core Opteron™ Processor •Source: A 4320MIPS Four-Processor Core SMP/AMP with
•ISSCC 2007 •Individually Managed Clock Frequency for Low
•Power Consumption, ISSCC 2007
48
9/27/18 VLSI-1 Class Notes