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Arithmetic Circuits-2

• Multipliers
– Array multipliers
• Shifters
– Barrel shifter
– Logarithmic shifter

ECE 261 Krish Chakrabarty 1

Binary Multiplication
M-1 N-1
X =  Xi 2i  Yi 2i
Y = i=0
i=0
Multiplicand Multiplier

Product Z = X * Y
N-1 M-1
 ( XiYj2i+j) 
= i=0
j=0
Partial products
• Product = Sum of partial products
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Multiplication
• Example:

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Multiplication
• Example:

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2
Multiplication
• Example:

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Multiplication
• Example:

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3
Multiplication
• Example:

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Multiplication
• Example:

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Multiplication
• Example:

• M x N-bit multiplication
– Produce N M-bit partial products
– Sum these to produce M+N-bit product
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The Binary Multiplication


1 0 1 0 1 0 Multiplicand
1 0 1 1 Multiplier


1 0 1 0 1 0
     
AND operation

1 0 1 0 1 0   


Partial Products

0 0 0 0 0 0

+ 1 0 1 0 1 0


1 1 1 0 0 1 1 1 0

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General Form
• Multiplicand: Y = (yM-1, yM-2, …, y1, y0)
• Multiplier: X = (xN-1, xN-2, …, x1, x0)

• Product:

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Dot Diagram
• Each dot represents a bit

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The Array Multiplier
x3 x2 x1 x0
y0

x3 x2 x1 x0


y1

Z0

HA  FA  FA HA
x3 x 2 x 1 x0 y 2

Z1

FA FA  FA  HA

Z2
FA: Full adder
x3 x2 x1 x0 y3
HA: Half adder
(two inputs)

FA FA FA  HA 
Z7 Z6 Z5 
Z4 
Z3
Propagation delay = ?

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The MxN Array Multiplier


— Critical Path

HA 
FA 
FA 
HA


FA 
FA FA 
HA   
Critical P ath 1
  
Critical P ath 2
Critical Path 1 & 2


FA 
FA 
FA HA

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Carry-Save Multiplier

HA 
HA 
HA HA 

HA 
FA 
FA 
FA

Carries saved for next


HA  
FA 
FA 
FA
adder stage

HA  
FA 
FA 
HA Unique critical path

Trade offs?

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Adder Cells in Array Multiplier



P


VDD
A  
Ci
VDD

A  A  P 
P S 

Ci

 A   

B B P

VDD
V DD

P A 

Ci 
Ci

P Co 
A  
Ci

 en tica lDelaysfo rCa rry an d Su m


Id  
P

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Multiplier Floorplan
X3  
X2 X1  
X0


Y0
       
HA Mul ti pl i e r Ce l l
Y1
C S C S C S C S

Z0

  
F A Mul ti pl i e r Ce l l

Y2
   
C S C S C S C S

Z1   
V e c to r Me r g i ng Ce l l

     
Y3
C S C S C S C S

Z2
X and Y s i g nal s ar e br o adc as te d
thr o ug h the c o mpl e te ar r ay .

C 
S
C   
S
C
S
C
S


Z7 
Z6   
Z5 Z4 Z3

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Multipliers —Summary

•OptimizationGoals Differe ntVs Binary Adder

•Once Again:Id
 entifyCriticalPath
•Otherpossible techniques
-Lo garithmic versus Linear(Wallace tree 
multiplier)
-Data encoding (Booth)
-Pipelining

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Comparators
• 0’s detector:  A = 00…000
• 1’s detector:  A = 11…111
• Equality comparator: A = B
• Magnitude comparator: A < B

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1’s & 0’s Detectors


• 1’s detector: N-input AND gate
• 0’s detector: NOTs + 1’s detector (N-input NOR)

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Equality Comparator
• Check if each bit is equal (XNOR, aka equality
gate)
• 1’s detect on bitwise equality

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Magnitude Comparator
• Compute B-A and look at sign
• B-A = B + ~A + 1
• For unsigned numbers, carry out is sign bit

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Shifters
• Logical Shift:
– Shifts number left or right and fills with 0’s
• 1011 LSR 1 = 0101 1011 LSL1 = 0110
• Arithmetic Shift:
– Shifts number left or right. Rt shift sign extends
• 1011 ASR1 = 1101 1011 ASL1 = 0110
• Rotate:
– Shifts number left or right and fills with lost bits
• 1011 ROR1 = 1101 1011 ROL1 = 0111

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The Binary Shifter


  nop Left
Right
One-bit shifts
Ai  Bi 


Ai-1 
Bi-1

Bi
t-S
licei
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Multi-bit Shifters
• Cascade one-bit shifters?
• Complex, unwieldy, slow for larger number of
shifts
• Two other types of shifters
– Barrel shifter
– Logarithmic shifter

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The Barrel Shifter



A3

B3
Shift by 0 to
 
S h1 3 bits
A2

B2

 
A1
S h2


B1
  
: Da ta Wire

  
: Co ntro l Wire

 
A0
S h3


B0

   


S h0 S h1 S h2 S h3

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The Barrel Shifter
• Area dominated by wiring
• Propagation delay is theoretically constant (at most one 
transmission gate), independent of shifter size, no. of 
shifts
• Reality: Capacitance on buffer input  maximum shift
width

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4x4 barrel shifter


A3
A2
A
1


A0


Sh0 
Sh1 
Sh2 
Sh3
 ffer 
Bu
Widthbarrel ~ 2 pm M
pm = metal/poly pitch
M = no. of shifts
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Logarithmic Shifter
• Staged approach, e.g. 7 = 1 + 2 + 4, 5 = 1 + 0 + 4
• Shifter with maximum shift width M consists of log2M stages
 
Sh1 Sh1  
Sh2 Sh2  
Sh4 Sh4


A3 
B3


A2 
B2


A1 
B1


A0 
B0

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0-7 bit Logarithmic Shifter


A
3
Out3

A
2
Out2

A
1
Out1

A
0
Out0

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