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[5] R. Murgai, Y. Nishihito, N. Shenoy, R. K. Brayton, and A. Sangiovanni-
Vincentelli, “Logic synthesis for programmable gate arrays,” in Proc.
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[6] R. J. Francis, J. Rose, and 2. Vranesic, “Chortle-crf: Fast technology
mapping for lookup table-based FPGA’s,” in Proc. 28th Des. Automat.
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[7] R. Murgai, N. Shenoy, R. K. Brayton. and A. Sangiovanni-Vincentelli,
“Improved logic synthesis algorithms for table look up architectures,”
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[9] N. S. Woo,“A heuristic method FPGA technology mapping based on the
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[ll] -, “Performance directed technology mapping for look-up table
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“Performance directed synthesis for table look up programmable gate
arrays,” in Proc. Int. Con$ Compur.-Aid. Des., 1991, pp. 572-575.
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Compur. Des., Oct. 1992.
[I71 J. Cong and Y. Ding, “On areddepth trade-off in LUT-based FPGA
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1063-8210/95$04.00Q 1995 IEEE
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Low-Power Design Techniques for
High-Performance CMOS Adders
Uming KO,Poras T. Balsara, and Wai Lee
Absftoct-A high-performanceadder is one of the mast critical compo-
nents of a processor which determines its throughput, as it is used in the
ALU, the floating-point unit,and for address generation in case of cache
or memory access. In this paper, low-power design techniques for various
digital circuit families am studied for implementing high-performance
adders, with the objeftive to optimize performance per watt or energy
ef6ciency as well as silicon area efficiency. While the investigation is done
using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 pm CMOS
technology, most techniques presented here can also be applied to other
parallel adder algorithms such as carry-select adders (CSA) and other
energy ef6cient CMOS arcuits. Among the techniques presented here,
the double pass-transistor logic @PL) is found to be the most energy
emdent while the single-rail domino and complementary pass-transistor
logic (CPL) result in the best p e d o r m ~ c eand the most area efficient
adders, respectively. The impact of transistor threshold voltage scaling
on energy efficiency is also examined when the supply voltage is scaled
from 3.5 V down to 1.0 V.
Zndex Terms-Low power, digital CMOS, high performance, adder.
I. INTRODUCTION
With the advent of battery operated applications like portable
computing and personal communication systems ( X S ) [l], it has
become imperative to develop integrated circuits and systems that
use less energy without greatly sacrificing computational throughput.
Furthermore, such energy efficient circuits are also needed in high-
performance desktop, AC powered systems in which sinking large
amount of heat through packages is becoming a difficult problem.
Thus, designing a low-power processor is becoming equally important
to designing a high performance one. This trend will benefit desktop
as well as portable systems as it will allow greater integration at the
silicon level with less expensive device packaging which in tum will
lead to a further reduction in system power dissipation.
A high-performance adder has been one of the most critical compo-
nents in determining the throughput of a processor’s execution unit,
floating-point unit, and memory address generation unit. Recently,
Nagendra et al. [2] presented power-delay characteristics of various
adder architectures using the full static CMOS circuit style. They
presented a comparison of ripple carry, block carry lookahead and
signed digit adders. A similar study was also reported by Callaway et
al. [3] in which they compared dynamic power dissipation of different
adder architectures. Besides considering different adder architectures,
another approach is to employ different CMOS circuit styles to design
energy efficient, high-performance adder circuits for a given architec-
ture. Conventional static CMOS has been the technique of choice in
most processor design. Altematively, static pass-transistor circuits, in
particular, have also been suggested for low-power applications [ 11.
Dynamic circuits, when clocked judiciously, can also be used in low-
power microprocessors [4]. However, several other design techniques
need to be applied and evaluated along with these circuit styles for
low-power/voltage processor applications.
Manuscript received April 22, 1994; revised November 3, 1994.
U. KO and W. Lee are with Texas Instruments, Inc., Dallas, TX 75265
USA.
P. T. Balsara is with the Department of Electrical Engineering, University
of Texas at Dallas, Richardson, TX 75083 USA.
IEEE Log Number 9410845.
 328 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (-1)
T T
+-+--P
- -
Fig. 1. XOR using high-performance static CMOS.
In this paper, we present a study and evaluation of various digital
circuit families and techniques to optimize performance per watt or
energy efficiency as well as the silicon area of an adder. A 32 b carry
lookahead adder architecture is implemented and evaluated using five
different CMOS circuit styles: full static CMOS [5], complementary
pass-transistor logic (CPL) [ 6 ] double
, pass-transistor logic (DPL) [7],
dual-rail Domino dynamic logic [8], [9], and single-rail Domino [lo],
[ 1 11 dynamic logic with supply voltages varying from 3.5 V to 1.5 V.
These techniques are characterized in terms of power, performance,
and area for each circuit family. Lastly, we present the impact of
threshold voltage scaling on power and energy efficiencies of these
circuit families.
11. 32 BIT CLA ADDERIMPLEMENTATIONS
In order to compare different circuit techniques mentioned in
Section I, five different 32 b carry lookahead (CLA) adders are
designed. The CLA adders are designed using a two-bit group
approach with six cany generation stages [12]. The circuit families
are briefly described below using the XOR gate, which is the most
basic gate in an adder circuit.
A. Full Static CMOS
A schematic diagram of a full static CMOS XOR gate is depicted
in Fig. 1. While it is a common CMOS design practice since it
involves minimum design risk, the serial nMOSFET or pMOSFET
transistors (Fig. 1) tend to demand that their width be increased to
obtain a reasonable conducting current to drive capacitive loads. This
results in significant area overhead, which also causes high gate input
capacitance and therefore high power dissipation. Furthermore, the
high input capacitance also loads the previous stage, increasing its
delay.
B. Complementary Pass-Transistor Logic (CPL)
Y h o et al. [6] described a logic technique in which a boolean
function is implemented using a network of nMOSFET pass transis-
tors. A CPL XOR gate is depicted in Fig. 2. When compared to the
full static XOR gate, CPL implementation utilizes only half as many
transistors and it avoids the design problem of appropriately sizing
series connected transistors in the pull-up or pull-down planes [5].
In CPL, internal dual rail signals (p and p in Fig. 2) are typically
generated simultaneously to minimize the propagation delay through
each circuit block. However, when the outputs of the nMOSFET pass-
transistor network are logically high, they are at v d d - vt, which
results in the incomplete turn-off of pMOSFET's in the inverters.
This results in a high static through current. To minimize the through
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SYSTEMS, VOL. 3, NO. 2, JUNE 1995
a b
Fig. 2. XOR using high-performance CPL.
a. T b~
Fig. 3. High-performance CPL XOR with pMOSFET feedback.
'-D-p
Fig. 4. Low-power CPL XOR with pMOSFET feedback.
current in CPL, a weak pMOSFET feedback device, as depicted in
Fig. 3, is added across the output inverter stage to pull the output node
of the pass-transistor network to full V d d . However, this ph4OSFET
pull-up increases the propagation delay of the CPL XOR gate. A
low-power CPL can be created by combining the two CPL gates
from Fig. 3 into one gate, as shown in Fig. 4. However, this leads to
an increase in delay of one of the outputs.
C. Double Pass-Transistor Logic (DPL)
Suzuki et al. [7] proposed a double pass-transistor logic (DPL)
which is a modified version of CPL. DPL alleviates the CPL problems
of noise margin and speed degradation at reduced supply voltages.
A high-performance DPL XOR gate is depicted in Fig. 5. A DPL
implementation avoids the series sizing (and high gate capacitance)
issues of the full static circuits as well as the nMOSFET threshold
voltage drop issue of the CPL design, by having both pMOSFET and
nMOSFET pass gates. Similar to Fig. 4, a low-power DPL can be
created by combining the two gates shown in Fig. 5 into a single gate
(except that DPL does not need the feedback pMOSFET).
D.Dual-Rail Domino Logic
Besides the above three static techniques, precharged circuit tech-
niques like Domino [8, 91 are also known for its high throughput. A
dual-rail domino XOR gate is illustrated in Fig. 6. The precharging
occurs when the CLK signal is at a logic low, and when CLK is at a
logic high the evaluation phase starts. A feedback pMOSFET device
is added to enhance the noise margin as well as to maintain the
logic state. One major advantage of this dynamic, precharged circuit
over the previous three static families is that it eliminates all the
spurious transitions and the corresponding power dissipation which
 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,VOL. 3, NO. 2, JUNE 1995 329

-
a b
i,
C4 4L K - I t L ~ ~ zi
(Single-rail signal)

' ''I
b
& L
J

L
.b
I Fig. 7. NOR using high-performance single-rail domino.
a
Fig. 5. XOR using high-performance DPL

CLKdm
T i T l t t

si Pi ti (single-rail signals)

Pi gi zi single-rail signals)
t t f
Fig. 6. XOR using high-performance dual-rail domino. IPre-Conditioning1

is inherent in any static logic implementation. However, in dual-rail

domino circuits, additional power is dissipated by the gating devices
and its clock drivers and distribution network.
E. Single-Rail Domino Logic
A closer examination of the domino design revealed that the
dual-rail inputs are only needed in the XOR implementation. Other
functions, such as NAND and NOR, can be implemented with single-
rail inputs only in order to reduce power dissipation. The single-rail
architecture is very sirmlar to the dual-rail domino, except that group
generation and propagation blocks in a CLA can be implemented
using single-rail inputs and outputs. Since dual-rail carry signals are
still required for the final sum (XOR) stage, an additional bit needs
to be produced and fed to the carry stage to generate dual-rail carry
signals from the single-rail propagation and generation inputs. This
additional bit called z , is defined in [l 11 as follows
z, = a , + b,. (1)
Fig. 7 depicts a single-rail domino implementation for this additional
bit z,. This signal 2% along with the propagate (pt) and generate (gz)
signals at bit position z is used to generate the dual-rail carry signals
as follows. First, a merge with the subsequent stage is performed in
the following manner
2, = z , + (zz--l . P t ) , where, P, = p , . Pz-l. (2)
Later, in the last stage, the dual-ral carry signal at bit position 2 is
generated as follows
cz = gz + .E ) ,
( ~ ~ - 1 and, c; = 2, + (E.
P z ) (3)
Therefore, the single-rail domino adder needs a modified precondi-
tioning circuit (Fig. 8) in order to produce three signals p , ,gz, and
2, instead of the usual two (pt and gz). The modified merge block
Fig. 8. Single-rail domino preconditioning and cany block diagram.
will merge the three signals p , , gz, and z, from the previous stages
to create P, and 2,. The carry cell accepts dual-rail carry-in signals
and single-rail gl, P, and 2, signals, as shown in Fig. 8. The sum
circuit remains the same as in the previous dual-rail domino adder.
This implementation reduces the internal signals from four (dual-
rail p , and gl) to three (single-rail p , , gt, and t,),and hence cuts
down the total gate capacitance. More importantly, it also reduces the
loading of the clock signal because of fewer number of clocked gates.
Another domino circuit technique, called a multiple-output domino
circuit, was proposed by Hwang et al. [lo]. This circuit performs
well at a 5 V supply voltage, but may suffer in performance at lower
supply voltages due to multiple series nMOSFET's used to implement
the multiple-output functions. Furthermore, as demonstrated later in
Section 111, since all domino adders are far less energy efficient
compared to the DPL adder, the multiple-output domino was not
added in our study on energy efficient adders.
111. POWER, DELAYAND AREACOMPARISONS OF CLA ADDERS
For the sake of having a regular physical layout, the adders
described above are designed using a two-bit group approach with six
carry generation stages [12]. Inputs to all five adders are single rail
signals, and receiving inverters were used to generate complementary
signals. Single-rail outputs to drive a capacitive load of 0.2 pF were
produced by all five adders. These adders were designed using a 0.6
pm, two level metal CMOS technology. The bit pitch was 25 p m
wide for all five adders and the interconnect metal capacitances were
estimated using a value of 0.25 pF/mm. Interconnect lengths were

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 330 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 3, NO. 2, JUNE 1995

estimated based on size and placements of individual building blocks. TABLE I

These were then used to calculate the interconnect capacitances which CPL POWER, DELAY, AND AREAEFFICIENCIES
FOR DIFFERENT
TECHNIQUES
were added to appropriate circuit nodes for the SPICE simulation.
Power estimation was done by carrying out detailed circuit simulation Parametera
(Vddd.3 v)
using SPICE under nominal condition at 3.3 V, 25°C with an input
signal frequency of 100 MHz. Since power dissipation depends on Percentage
the input and its history, for the sake of our evaluation we used a 230 237 2.24
uniformly distributed randomly generated sequence of input patterns, 110 113 107
as used in the available literature [I, 31. Propagation delay was
measured from the carry-in signal to the most significant bit of sum Percentage 262 139 1 139
output, under the same SPICE conditions.
Table I gives a comparison of various CPL methods for a
32 b CLA. The second and third columns, CPL and CPL with
pMOSFET#l, indicate that adding the pMOSFET feedback transistor TABLE I1
reduces power dissipation to 48% of that in CPL. However, there is DPL POWER. DELAY,
AND AREAEFFICIENCIES FOR DIFFERENT
TECHNIQUES
10% performance degradation and a 2% area overhead due to the
feedback device. As shown in the fourth column, which is CPL with Optimlzed
pMOSFET#2, a stronger feedback pMOSFET transistor size can also (Vdd=33 V) DPL DPL Units
be utilized to further reduce the power with a nominal speed penalty, Power @ 100 MHz 40.1 27.5 mW
however the reduction in power is not as significant. In order to
Percentage 146 100 %
further reduce power dissipation without degrading performance, we
re-examined our adder circuit to isolate the speed critical paths. These Delay of critical path 2.11 1.98 w
paths include the nets from carry-in to carries C7, CIS,Cm. and C:~I. Percentage 107 100 %
For the gates on these paths we used the high-performance CPL gates Energy @ 100 MHz 84.6 54.5 PJ
(Fig. 3), whereas for the gates on the other nonspeed critical paths
Percentage 155 100 z
the low-power CPL gates (Fig. 4) were used. Further reduction in
power dissipation is still possible, if the power reduction technique Area: totaltr. width 30242 19116.5 pm
suggested in [I31 is applied. Using this technique we can reduce Percentage 158 100 %
overall power dissipation of a circuit by judiciously choosing drive
strengths (i.e., device sizes) of the gates on nonspeed critical paths
in that circuit. In this method we first characterize power dissipation power as DPL, and is 21% faster than DPL. Among all the design
of each gate for various drive sterngths using different values of styles evaluated in Table I11 we can see that the static families are
input signal slew and output fanout load. From this characterization more energy efficient compared to the domino circuits. Furthermore,
we can determine the most suitable drive strength for a gate (i.e., the DPL family is most suited for energy efficient, high-performance
one that results in lowest power dissipation) by considering its input adder designs.
slew and output fanout when it is used in a circuit. Since device
sizes are only changed on the nonspeed critical paths in a circuit, this I v . EFFECTOF SCALING SUPPLY VOLTAGE
method yields overall power reduction withour adversely affecting AT CONSTANT THRESHOLD VOLTAGE
performance of that circuit. The fifth column in Table 1 depicts the
SPICE simulations for different supply voltages using the same
results of this optimized CPL CLA adder. Compared to the fourth
CMOS device models with constant threshold voltage were conducted
column of Table 1, this results in a power reduction of 31%, an area
and the results are shown in Figs. 9-1 I . At lower supply voltages
reduction of 63%, and enhances performance by 6%.
( < 2 . 5 V), the insufficient pull-up strength of nMOSFET severely
A summary of results for various DPL implementations is given in
compromises the speed of CPL, and it fails to respond to the 100 MHz
Table 11. In the table, the optimized DPL was obtained by applying
input pattern rate at 1.5 V. Hence, except for CPL, the dependency
the method similar to the one described above for CPL. The third
of delay T d on supply voltage I& is well modeled by (4) given in
column of Table I1 indicates that optimized DPL yields 46% power
reduction with a 7% speed improvement and a 58% area reduction
U , 141
compared to the original DPL. DPL’s two separate current paths in (4)
charging and discharging output capacitive loads is the main reason
for a 13% improvement in speed compared to the optimized CPL with (Y = 1.6 which is consistent with the device models used in our
implementation from Table I. A comparison of the three static styles SPICE simulations.
with the dynamic domino families is depicted in Table 111. The After applying the low-power design techniques described in
columns in this table correspond to the optimized versions of the Section 111, the DPL adder consumes the lowest power and the
CLA adder circuits for each of the families. Among three static circuit single-rail domino adder is the fastest at all supply voltages as
styles, full static, CPL and DPL, the DPL adder is 42%-47% more shown in Figs. 9-10, respectively. The power-delay product, which
energy efficient than the other two. As for the silicon area, Table I11 is equivalent to the energy required to perform additions, is the
shows that the DPL adder occupies 47% less area compared to the lowest in the DPL implementation. Fig. 1 1 depicts that relative to
full static version, and 10% more area compared to the CPL circuit. the DPL adder, for a supply voltage range of 3.5 V-1.5 V, the
Compared to the best static style, i.e., the DPL, the dual-rail domino single-rail domino and full static adders consume 81%-71% and
consumes three times as much power but is only 12% faster. This high 47%-25% excess energy, respectively. On an average, a factor of 2.1
power dissipation in the domino circuit is due to the additional gating improvement in energy efficiency is achieved by scaling the supply
transistors and clock signal drivers required in that circuit. The single- voltage from 3.5 V to 1.5 V, without any change in the device
rail domino, on the other hand, consumes about 2.19 times as much technology.

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 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 3, NO. 2, JUNE 1995 331

Single
Parameters DualRail Rail
(Vddd.3 V) static CPL DPL Domino Domino Units
Power@ 100MHz 34.3 34.5 21.5 82.5 60.2 mW
percentage 125 125 100 300 219 %

-.
Delnv of critical uath
~
I1
2.33 I
2.24 I
1.98 I
1.78 1.64 118

Percentage 142 137 121 109 100 %

Energy@ 100MHz 11 79.9 I 71.3 I 54.5 I 146.9 I 98.7 IPJ

Percentme - 11 147 I 142 I 100 I 270 I 181 1%
Area: pMOSFET width 17700 8295.6 11935.5 14716.4 12064.4 pm
nMOSFET width 9655 9141.5 7181 17728 14862 Cun
total tr. width 27355 17437.1 19116.5 32444.4 26926.4 pm
Percentage 157 100 110 186 154 %

100, I 7

I 1 ' I
1.5 2 2.5 3 3.5 1.5 2 Supply Voltage
2.5 (volts) 3 3.5
Supply Voltage (volts)
32 b adders average power versus supply voltage. 32 b adder delay versus supply voltage.

v. EFFECTOF SCALING THRESHOLD

VOLTAGE WITH SUPPLY VOLTAGE By simultaneous Vt scaling, the CPL adder benefits significantly
and is fully functional at 100 MHz down to 1 V supply voltage
The amplitudes of most internal noises, such as those generated
(Fig. 12). The speed degradation for all circuit families at low supply
from interconnect coupling and ground bounce, scale proportionally
voltages is also eased considerably, as evident in Fig. 13. This can
with supply voltages. Therefore, the threshold voltage of MOS
devices can be scaled proportionally with supply voltages to reduce
be predicted by (4).By keeping a constant vt/vdd
ratio, the delay,

the logic noise margins at low supply voltages, thereby main-

taining the same signal to noise margin ratio. Assuming that the
threshold voltage can be kept at 1/5 of the supply voltage while
using the same 0.6 pm technology, a series of SPICE simulations
were carried out and the results are shown in Figs. 12-14. With
this particular scaling rule, the threshold voltage will be 0.2 V
when the supply voltage is 1 V. This low value of threshold
voltage will lead to a high leakage current even when the gate
bias is at 0 V. The contribution from this high off-current to the
total power dissipation of these adders running at 100 MHz is
around 1 1%-l8% for the five CLA adders. In applications where
the duty cycle of the circuit is much longer, the contribution of
the off-current will increase and an active substrate bias will be
needed to reduce the leakage current when the device is in the off
state.
T d cc vJi-a).For cy = 1.6, T d 0: v&'',which is a weaker vdd
dependency than the previous case of scaling supply voltage without
corresponding Vi scaling. Consequently, adder delay under 4.5 ns
is achievable at 1 V supply. Further scaling of FET channel length
to keep the devices operating in the velocity saturation regime (cy
approaches unity) will bring a less severe speed degradation at low
voltages. At 1 V supply voltage or 0.2 V threshold voltage, single-
rail and dual-rail domino adders are 27% and 8% faster than the DPL
adder, respectively. For 3.5 V-1.0 V supply voltage, DPL is the most
energy efficient and dual-rail and single-rail domino consume about
2.78-2.63 times and 1.8-1.62 times as much energy as compared
to DPL, respectively. Full static and CPL consume 1.48-1.45 and
1.24-1.23 times as much energy relative DPL. On the whole, with
simultaneous scaling of supply voltage and threshold voltage, energy
efficiency is improved by a factor of 4.4 when the supply voltage is
reduced from 3.5 V to 1.0 V.

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 332 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,VOL. 3, NO. 2. JUNE 1995

4.5

140 - Static - 4

110 - 3.5

70 . 2.5

1.5
1.5 2 2.5 3.5
supply Voltage (volts) Threshold Voltage, 1/5 of Supply Voltage (volts)

Fig. 11. 32 b adders energy versus supply voltage. Dependency of delay on Vt scaling.

170 I
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
nl I 10
0.2 0.3 0.4 0.5 0.6 0.7 0.2 0.3 0.4 0.5 0.6 0.7
Threshold Voltage, 115 of Supply Voltage (volts) Threshold Voltage, 1/5 of Supply Voltage (volts)
Dependency of power on Vt scaling. Dependency of energy on Vt scaling.

VI. CONCLUSION
Although CPL uses fewer transistors than the other four static and
dynamic circuit styles to implement the same logic functions, the
partial swing at the intermediate nodes results in more than 50%
of the power being wasted. Reduction in the Vt of the nMOSFET
pass transistors has been proposed to ease this problem [l], but
it will reduce the noise margin to an unacceptable level at low
supply voltages. An additional feedback pMOSFET device in the
inverter stage combined with both the low-power CPL and the high-
performance version and the technique in [13], yields an improvement
by a factor of 2.62 in energy efficiency and a 59% reduction in
area, compared to the original CPL. Because of the presence of
both nMOSFET and pMOSFET devices, all nodes in DPL have
a full voltage swing and there is no static short-circuit current
problem. Dual current paths in DPL implementation also improves
performance. With the similar techniques applied in CPL (except
for feedback pMOSFET), the optimized DPL's energy efficiency
is increased by a factor of 1.55 with a 58% area reduction when
compared to the original DPL.
Precharged circuits like domino offers performance advantage over
DPL (fastest in the three static circuit families investigated) by
12%-21%, but at the expense of burning 300%-219% power relative
to DPL. Compared to DPL, dual-rail and single-rail consume 270%
and 181% energy and require 76% and 44% more silicon area,
respectively.
In summary, the improved CPL uses the least amount of silicon
area, and single-rail domino offers the fastest performance. The
improved DPL is the most energy efficient circuit and is suitable for
applications in which power and performance are equally important.
ACKNOWLEDGMENT
The authors would like to thank the anonymous referees for their
helpful comments in improving the presentation of this paper.

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 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,VOL. 3, NO. 2, JUNE 1995
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333
Sequential Circuit Testability
Enhancement Using a Nonscan Approach
Elizabeth M. Rudnick, Vivek Chickermane,
Prithviraj Banerjee, and Janak H. Patel
Abstmct-Recent studies show that a stuck-at test applied at the
operational speed of the circuit identifies more defective chips than
a test having the same fault coverage but applied at a lower speed.
Design-for-testability approaches based on full scan, partial scan, or
silicon-based solutions such as Crosscheck achieve very high stuck-at
fault coverage. However, in all these cases, the tests have to be applied
at speeds lower than the operation speed. In this work, we investigate
various design-for-testability (DFT) techniques for sequential circuits that
permit &-speed application of tests while providing for very high fault
coverage. The method involves parallel loading of flip-flops in test mode
for enhanced controllability combined with probe point insertion for
enhanced observability. Fault coverage and ATG effectiveness improved
to greater than 96% and 99.72, respectively, for the ISCAS89 sequential
benchmark circuits studied when these nonscan DFT techniques were
used. The average area overhead for the nonscan DFT enhancements
was 9.9% for standard cell implementations of three circuits synthesized
from high-level descriptions, compared to 202% for full scan. ATG
effectiveness improved to greater than 99.3% for all three circuits with
the nonscan DFT enhancements.
Index Term-At-speed testing, design for testability, sequential cir-
cuits, testable chip implementation, test point insertion.
I. INTRODUCTION
High quality is of critical importance to manufacturers of integrated
circuits. Test sets having very high fault coverage are needed to ensure
high quality. However, generating test sets with high fault coverage
is a difficult problem, especially in highly sequential circuits. With
deterministic test generators, generation of a test sequence to detect a
fault typically involves fault excitation, fault effect propagation, and
state justification. Good observability of the fault site is required
for propagating the fault effects, and good controllability of the
flip-flops is required for justifying the state. Typical design-for-
testability (DFT)techniques involve improving the controllability
and observability of internal circuit nodes, thereby reducing the
complexity of test generation [l]. With full scan design, complete
controllability and observability are provided at the flip-flops. As
a result, the state justification phase is avoided, and the fault effect
propagation phase is simplified. Partial scan design is a cost-effective
alternative in which only a subset of the flip-flops are placed in
the scan chain; state justification and fault effect propagation are
simplified, and delay and area overheads are reduced relative to full
scan. The disadvantages of full scan and partial scan are that vectors
cannot be applied at the clock speed, and test application time is
higher than in a nonscan design due to shifting of test vectors through
scan chains.
Manuscript received June 10, 1993; revised March 16, 1994. This work was
supported by the Semiconductor Research Corporation under Contract SRC
92-DP-109.
E. M. Rudnick was with the Center for Reliable and High-Performance
Computing, University of Illinois, Urbana, IL 68101 USA. She is now with
Motorola Incorporated, Austin, TX 78730 USA.
V. Chickermane was with the Center for Reliable and High-Performance
Computing, University of Illinois, Urbana, IL 68101 USA. He is now with
IBM Corporation, Endicott, NY 13760 USA.
P. Banerjee and J. H. Patel are with the Center for Reliable and High-
Performance Computing, University of Illinois, Urbana, IL 68101 USA.
IEEE Log Number 9410846.