Carrier based PWM for Even Power Distribution
in Cascaded H-bridge Multilevel Inverters
within Single Power Cycle
Krishna Kumar Gupta1,Member, IEEE,
Pallavee Bhatnagar2, Member, IEEE
Jai Narain College of Technology, Bhopal
India (M.P.)
1
kkg.manit@gmail.com, 2pallaveevbhatnagar@gmail.com
Abstract—A cascaded H-bridge multilevel inverter offers
important advantages over the conventional two-level topologies,
though it necessitates isolated input dc sources. Even power
distribution amongst these sources is an important control issue
for an enhanced life-time of the overall system. In currently used
control schemes, for ‘n’ number of input sources and a
fundamental period ‘T’ for the output voltage, average power
drawn from each source become equal after cyclic time spans of
‘n*T’. In this paper, a methodology is presented using which
these spans are reduced to ‘T’, irrespective of the number of
input sources. In the proposed scheme, sine-triangle pulse-width-
modulation (SPWM) technique has been espoused to obtain a
‘multilevel reference signal’. This signal is further manipulated,
so as to impart flexibility for the selection of redundant states.
Actual driving signals for the power switches are then derived
from the manipulated multilevel reference signal, utilizing chosen
states such that the respective average currents drawn from the
input sources are repeatedly equalized within one power cycle of
the output voltage. Such flexibility is not directly offered by the
standard multilevel SPWM methods. Simulation and
experimental results indicate that for two input sources and an
output voltage of 50 Hz, the conventional ‘carrier rotation’
scheme requires repeated time-spans of 0.04 sec for even power
distribution whereas the proposed scheme requires only 0.02 sec.
Thus, the proposed scheme leads to a better and effective
utilization of sources, especially when the number of input
sources is large.
Keywords—Multilevel inverters; even power distribution; pulse
width modulation; carrier rotation
I. INTRODUCTION
Dc-ac power conversion has become an important constituent
of the modern set-up of generation, transmission, distribution
and utilization of electric power. Dc-ac power converters
(‘inverters’) play critical role in variable frequency drives,
uninterruptible power supplies, induction heating, air
conditioning, high voltage dc power transmission, electric
vehicle drives, static var compensators, flexible ac
transmission systems and renewable energy based power
generation [1,2].
Based on the nature of the output waveform, inverters
are classified as: square wave, quasi-square wave, two-level
PWM and multilevel inverters [3]. The concept of multilevel
inverter (MLI) was primarily introduced for high power and
978-1-5090-3474-1/16/$31.00 ©2016 IEEE
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Hani Vahedi3, Kamal Al-Haddad4
Department of Electrical Engineering, GREPCI
Ecole de Technologie Superieure
Montreal, Canada
3
Hani.Vahedi@etsmtl.ca, 4Kamal.Al-Haddad@etsmtl.ca
medium voltage applications. It is based on the methodology
of using power semiconductor switches along with several
lower voltage dc levels to synthesize a staircase voltage
waveform. Thus, in general, the voltage stress on a power
switch is much lower than the operating voltage. In addition,
there are many other advantages such as: reduced common
mode voltages, reduced dv/dt stresses on the load, staircase
waveform with better harmonic profile, smaller filter
requirements, flexibility to operate on low- and high switching
frequencies and possibility of fault-tolerant operation [3–5].
In the last few decades, the topologies which have
attracted maximum attention from the industry and academia
are: neutral point clamped (NPC) converters, cascaded H-
bridge (CHB) converters and flying capacitors (FC)
converters. Amongst these, the CHB topology offers higher
reliability due to its modularity [6]. The CHB structure
comprises series connection of several single-phase full bridge
inverters (also called ‘power modules’ or ‘cells’). Each power
module is similar in terms of circuit topology, control and
modulation scheme [6, 7].
Modules of the CHB structure, as shown in Fig.1,
consist of electrically isolated input dc levels. These levels are
obtained by either using actual sources or through rectified ac
with capacitors as filters. The power drawn from these dc
inputs vary as a function of modulation index, output voltage
levels and load power factor [8]. This may result in unsteady
and, at times, unstable dc voltage levels. Hence, the dc inputs
deliver unequal power. As a result, different dc inputs would
have different lifetimes and hence complex maintenance
issues. Thus, ‘even power distribution’ or ‘charge balance
control’ amongst input dc sources is important so that all dc
sources have equal life times [8]. Even power distribution is
also crucial when the dc sources are renewable sources such as
PV cells. For CHB inverter with multiple input dc sources, the
so-called carrier rotation scheme is employed for equal
utilization of sources [9,10]. An important limitation of this
scheme is in terms of the minimum time-span for average
power (or charge) to be cyclically balanced. For ‘n’ number of
series connected power modules and a fundamental period ‘T’
for the output voltage, it takes repeated time spans of ‘n*T’ for
even power distribution. In this paper, a methodology is
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presented using which even power distribution is attained which consists of ‘n’ number of modules. A ‘jth’ module has
within a time spans equal to ‘T’. In addition, the harmonic input dc source with voltage VDC and four power
profile of the output voltage is at par with that obtained semiconductor switches viz. S1, j , S’1, j , S2, j and S’2,j. The
through ‘carrier rotation scheme’. Thus, a better control is source current is shown as is,j(t). Output voltage of the ‘jth’
administered without compromising the power quality. module can be designated as v0,j(t). The module is capable of
Rest of the paper is organized as follows. In section synthesizing three voltage levels viz. 0 and ±VDC, and the
II, the CHB topology and its switching model is presented. In possible states are shown in Table I, along with the values of
section III, the principle of even power distribution is source current is,j(t) in terms of the load current iL(t).
described and the proposed methodology is presented. In
section IV, MATLAB/Simulink based simulation results are TABLE I
POSSIBLE SWITCHING STATES FOR ‘jth’ MODULE
presented for the proposed methodology and the conventional
State Switches in ON State Output Voltage vo,j(t) Source Current is,j(t)
‘carrier rotation scheme’. Experimental results are discussed in 1j S1, j , S2, j 0 0
section V and concluding remarks are presented in section VI. 2j S’1, j ,S’2,j 0 0
3j S1, j , S’2,j +VDC +iL(t)
II. THE CASCADED H-BRIDGE TOPOLOGY: STRUCTURE, 4j S’1, j , S2, j -VDC -iL(t)
MODELLING AND CONTROL
For a given switch Sk,j (where, k = 1 to 4 and j = 1 to
n), a switching function Tk,j(t) can be defined such that,
0 , if power switch S k , j is OFF
Tk , j (t ) =  (1)
 1 , if power switch S k , j is ON
Then, the output voltage of the ‘jth’ module can thus be
expressed as:
vo, j (t ) = {T1, j (t ) − T2, j (t )} * VDC (2)
And, the source current can be expressed as,
is, j (t ) = {T1, j (t ) − T2, j (t )} * iL (t ) (3)
Since all the power modules are connected in series, the load
voltage vL(t) can be expressed as,
n n (4)
v L (t ) = ∑v o , j (t ) =
j =1
∑
[{T1, j (t ) − T2, j (t )} * V DC ]
j =1
Considering the load to be a generic RLE-load with equivalent
resistance R, inductance L and back ac emf eb(t),
di L (t ) (5)
v L ( t ) − i L (t ) * R − L * − eb ( t ) = 0
dt
In addition, the number of levels ‘N’ in output voltage would
be,
N = 2*n + 1 (6)
And, the peak value of the output voltage would be,
vL,max = n*VDC (7)
Equations (1)-(7) form the complete mathematical model of
the CHB topology. It can be observed from Table I that each
power module has two independent switches and thus 22 = 4
valid states. Thus, an inverter consisting of ‘n’ power modules
would have ‘22*n’ possible states in total. The process of time
based selection of appropriate states so as to obtain the desired
voltage levels at the output is called modulation. As is the case
with the conventional two-level inverters, sine-triangle pulse
width modulation (SPWM) is a popular scheme for multilevel
Fig.1. A generalized single-phase configuration of the cascaded H-bridge modulation [4,7,9].
(CHB) multilevel inverter For an N-level inverter, SPWM entails a sinusoidal
reference and (N-1) carrier signals. For example, a 5-level
The CHB topology was first introduced in a patent inverter (i.e. two power modules in CHB structure), four
awarded to Baker and Bannister [11] in the mid-1970s. The carrier signals are required, as depicted in Fig.2(a) (only
topology consists of single-phase full bridge inverters (‘power positive half cycle of the reference waveform is shown for the
modules’ or ‘cells’) connected in series as depicted in Fig.1, sake of clarity). Indeed, hereafter arguments are presented for

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a 5-level CHB inverter, though these arguments remain valid T
1 (9)
for a general N-level inverter realized with the CHB topology.
Carrier signals can be arranged in a number of ways as
Pavg , j = V DC *
T ∫i
0
s , j (t ) dt

discussed in [12]. With this scheme, the utilization of sources

Thus, for any two given sources (and, for that matter, all the
of two modules is different and thus they undergo unequal
sources), power drawn can be equalized within one power
charging-discharging [10]. To overcome this problem, the so-
cycle, if following condition can be achieved,
called ‘carrier rotation’ scheme has been proposed [9,10]. In
T T
this scheme, as depicted in Fig.2(b) for a 5-level CHB 1 1 (10)
inverter, the carrier waveforms are ‘rotated’ so that both the
input sources are utilized equally. With the ‘carrier rotation’
V DC *
T ∫0
i s, j (t ) dt = V DC *
T ∫
0
i s , j −1 (t )dt

scheme, for an N-level inverter with ‘n’ number of dc sources,

Using equations (10) and (3),
it would take ‘n’ power cycles for average power to be
T
balanced. In the next section, description of the proposed
scheme is presented using which balancing can be achieved
within one power cycle, irrespective of the number of input
∫ [{T
0
1, j (t ) − T2, j (t )} * i L (t )]dt =

sources. T (11)

∫ [{T
2
1, j −1 (t ) − T2, j −1 (t )} * i L (t )]dt
Carrier and reference signals

0
1
Equation (11) indicates that, for any given load current, with
the help of appropriate control of the switching functions,
0 average power drawn from input dc sources can be equalized
within one power cycle. Hence, with proper time-based
-1 selection of module ‘states’, the currents (and hence respective
powers) drawn from the input sources can be controlled so as
-2 to achieve even power distribution within one power cycle.
Such a methodology for a 5-level CHB inverter is herewith
0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01 explained.
Time [sec]

(a)
2
Carrier and reference waveforms

-1

-2 Fig.3. A schematic representation of the proposed methodology

0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01
Time [sec]
(b) Four triangular waveforms are used as carrier signals
Fig.2. (a) Carrier and reference signals for a 5-level inverter with level- which are disposed so that they occupy contiguous bands
shifted SPWM scheme; (b) Carrier and reference signals for a 5-level (refer Fig. 2(a) and Fig.3). The zero reference is placed in the
inverter with the ‘carrier-rotation’ scheme middle of the carrier set. The modulating signal is a sinusoidal
waveform. At every instant each carrier is compared with the
III. PRINCIPLE OF CHARGE BALANCE CONTROL AND THE modulating signal. For the carrier signals above the zero
PROPOSED METHODOLOGY reference, the comparator gives ‘1’ if the modulating signal is
greater than the triangular carrier, ‘0’ otherwise. For the
Each power module of the CHB inverter has a dc carrier signals below the zero reference, the comparator gives
source with voltage VDC from which a current is,j(t) is drawn ‘-1’ if the modulating signal is lower than the carrier signal,
(refer Fig.1). Thus, the instantaneous power drawn from the ‘0’ otherwise. The results are added to obtain a signal which is
‘jth’ source can be expressed as, a replica of the load voltage waveform. This signal is referred
p j (t ) = is, j (t ) * VDC (8) to as ‘multilevel reference signal SML(t)’, shown in Fig.4(a).
Thus, over a fundamental time period ‘T’, average power Actual driving signals for the power switches have to be
drawn from the ‘jth’ source would be, derived from SML(t) by utilizing chosen states for various
modules for corresponding levels of SML(t). This signal,

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however, is further manipulated as depicted in Fig. 4(b), to 80

obtain S*ML(t), which is then used for the desired objective of 60

charge balance control. 40
6 20

Voltage [V]
0
4
-20
2 -40

-60
0
-80
-2 6 6.01 6.02 6.03 6.04 6.05 6.06 6.07 6.08 6.09 6.1
Time [sec]
(a)
-4 30

-6 20
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time [sec]
10
(a)

Current [A]
6 0

-10
4

-20
2

-30
0 6 6.01 6.02 6.03 6.04 6.05 6.06 6.07 6.08 6.09 6.1
Time [sec]
(b)
-2 30

-4
20

-6
Current [A]

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 10

Time [sec]
(b) 0
Fig.4. Waveforms for the proposed methodology: (a) multilevel reference
signal ‘SML(t)’; (b) manipulated multilevel reference signal ‘S*ML(t)’
-10

Signal S*ML(t) consists of eleven distinct levels (from

-5 to +5, in steps of 1). In the proposed scheme, signal S*ML(t) -20
6 6.01 6.02 6.03 6.04 6.05 6.06 6.07 6.08 6.09 6.1
is successively compared with constants -5 to +5 and resultant Time [sec]
pulses are fed to switches which need to conduct for a state (c)
30
associated with a given level, as shown in Fig.3. States shown
in Fig.3 correspond to Table I in the context of j=1, 2. For
example, ‘(31, 12)’ indicates that the first module is in its state 20

3 (i.e. the module output voltage is +VDC) and the second

Current [A]

module is in its state 1 (i.e. the module output voltage is 0). 10

Thus, for ‘(31, 12)’, the load voltage is ‘VDC + 0 = VDC’. As a

result of the proposed methodology, within a power cycle, 0

both the sources are equally utilized, as demonstrated by the

results presented in the next section. -10

IV. SIMULATION RESULTS -20

6 6.01 6.02 6.03 6.04 6.05 6.06 6.07 6.08 6.09 6.1
Time [sec]
Using SimPowerSystem toolbox in (d)
MATLAB/Simulink environment, a 5-level CHB inverter was Fig.5. Simulated waveforms for the 5-level CHB inverter using ‘carrier
simulated using the ‘carrier rotation’ and the proposed rotation’ scheme: (a) load voltage; (b) load current; (c) source current
from the first power module; and (d) source current from the second
modulation schemes. Phase disposed triangular signals with power module
frequency 1 kHz are employed as carriers and sinusoidal modulation index of 0.85. Input sources are taken as 40 V
reference with frequency 50 Hz is used with an amplitude each. An arbitrary inductive load with R = 2Ω and L = 5 mH is

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considered. For the ‘carrier rotation scheme’, simulated results 80

are shown in Fig. 5. It can be seen from Fig. 5(a) that the load 60
voltage is a 5-level waveform with equal sized steps of 40V 40
each and a peak voltage of 80V. The load current, as shown in 20

Voltage [V]
Fig. 5(b), reflects inductive nature of the load. Source currents
0
are shown in Fig.5(c) and (d). The current waveforms of two
equal dc sources indicate an alternating pattern which is a -20

result of rotation of carrier signals. For example, the current -40

waveform of first source in the duration t = 6.02 to 6.04 sec is -60
same as that of the second source in the duration t= 6.04 to -80
6.06 sec and vice versa. Thus, the effective charge/discharge 6 6.01 6.02 6.03 6.04 6.05 6.06 6.07 6.08 6.09 6.1
of these two sources is identical, thereby achieving even Time [sec]

power distribution within the two sources. However, average (a)

30
values of the source currents are equalized only after repeated
spans of two complete power cycles (i.e. 0.04 sec in this case). 20
If there are ‘n’ number of input dc sources, it would take
10
‘0.02*n’ sec (for a 50 Hz output voltage) for the equalization

Current [A]
of power drawn. 0
With the similar input voltages and load, simulations
are carried out using the proposed methodology and -10
simulation results are presented in Fig.6. The load voltage and
-20
current waveforms, shown in Fig. 6(a) and (b) respectively,
are same as those in Fig. 5(a) and (b). -30
Thus, the load voltage and current are of the same quality 6 6.01 6.02 6.03 6.04 6.05 6.06 6.07 6.08 6.09 6.1
Time [sec]
for both the schemes, as is expected. The source current (b)
waveforms are shown in Fig. 6(c) and (d). Here too, the 30
current waveforms of two equal dc sources indicate an
alternating pattern which is a result of swapping the two 20

sources for voltage-level synthesis in quarter cycles. For

example, the current waveform of first source in the duration t 10
Current [A]

= 6.02 to 6.03 sec is same as that of the second source in the

duration t= 6.03 to 6.04 sec and vice versa. Thus, the effective 0

charge/discharge of these two sources is identical, thereby

achieving even power distribution within the two sources. -10

Thus, average values of the source currents are equalized

within one power cycle (i.e. 0.02 sec in this case). If there are -20
6 6.01 6.02 6.03 6.04 6.05 6.06 6.07 6.08 6.09 6.1
‘n’ number of input DC sources, it would still take ‘0.02 sec’ Time [sec]
(for a 50 Hz output voltage) for the equalization of power (c)
30
drawn, with appropriate extension of the proposed scheme.
20
V. EXPERIMENTAL RESULTS
To validate the proposed methodology, a prototype of 10
Current [A]

the CHB 5-level inverter is developed in the laboratory.

Photograph of the set-up is shown in Fig.7. MOSFETs 0
(IRF460), driven with suitable gate drivers, are used as power
switches and two regulated power supplies with 40V each are -10
used as input dc sources. The inverter is arbitrarily loaded with
an inductive load with R = 35Ω and L = 3.25 mH. Carrier and -20
6 6.01 6.02 6.03 6.04 6.05 6.06 6.07 6.08 6.09 6.1
reference signals of respective frequencies of 1 kHz and 50 Hz Time [sec]
are used. The control scheme is implemented through a (d)
dSPACE DS1103 real time controller. As shown in Fig. 8(a), Fig.6. Simulated waveforms for the 5-level CHB inverter using the
the load voltage is a 5-level waveform with steps of 40 V proposed scheme: (a) load voltage; (b) load current; (c) source current
each and a peak of 80 V as expected while the current from the first power module; and (d) source current from the second
power module
indicates the inductive nature of the load. As can be observed
from the current waveforms in Fig.8(b), the patterns are swapped such that the average waveforms are equal within
one power cycles. Power measurements are taken at the load
and the two sources and readings are shown in Table II. It can

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 be seen that the power delivered by both sources are equal and
even power distribution is effectively achieved.
Fig.7. Photograph of the experimental set-up
(a)
(b)
Fig.8. Experimental results: (a) Upper trace: load voltage (y-axis:20V/div)
and lower trace: load current (y-axis: 1A/div) (x-axis: 10ms/div) ; (b)
Upper trace: source current from the first source and lower trace : source
current from the second source (y-axis: 2A/div; x-axis: 5ms/div)
TABLE II
MEASUREMENT OF POWER IN THE EXPERIMENTAL SET-UP
Power measured at Power measured at first Power measured at
load [W] source [W] second source [W]
60.5 36.0 36.0
VI. CONCLUSION
The cascaded H-bridge topology was the first amongst many
topologies of multilevel inverters to be commercialized. Its
simple and modular structure is one of the principle reasons
behind this. The topology, however, requires electrically
isolated input dc sources. With the regular level-shifted sine-
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triangle PWM schemes, these input sources do not share equal
power amongst themselves and hence undergo unequal cycles
of charge and discharge. This, in effect, leads to unequal
lifetimes and complex maintenance. This issue is
conventionally solved using the so-called ‘carrier rotation’
scheme. With this scheme, charge balance takes place with
time equal to number of sources times the fundamental time
period. In this paper, an alternative methodology is presented
using which, charge balance is achieved within one power
cycle, irrespective of the number of input sources. The
methodology is based on the SPWM scheme with appropriate
adaptation so as to achieve flexibility in the selection of
inverter states. Simulation and experimental results are
presented which validate the proposed concept.
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