Advanced Compiler Engineering – Question Catalogue

1. What does data flow analysis mean?

2. What is a program point?
3. What is a reaching definition?
4. How can reaching definitions be determined?
5. What is the advantage of data flow analysis at basic block level?
6. How does depth-first-search work for a directed graph?
7. What is the advantage of the worklist-algorithm?
8. What are UD/DU-chains?
9. What is an available expression?
10. Which confluence operators is used for calculation of available expressions?
11. Given an example for backward dataflow analysis!
12. How can live variables be determined?
13. What is the advantage of an incremental dataflow analysis?
14. Name a use-case for the SSA.
15. Define the term “Dominance Frontier”
16. Where are dominance frontiers used?
17. Which types of dependencies can arise between two statements?
18. What is a problem for the dependency analysis of memory accesses?
19. What is complexity of the dependency analysis for array accesses in loops?
20. What is the GCD test?
21. Name advantages of the interprocedural dataflow analysis!
22. What is meant by "procedure cloning"?
23. What is the purpose of a call graph?
24. Which problems can arise in the construction of call graphs?
25. What are variable aliases?
26. What is the goal of code optimization?
27. Explain the following terms: constant folding, common subexpression elimation,
copy propagation, dead code elimation. How do these transformation impact the
code size and performance?
28. Which IR optimizations are based on dataflow analysis algorithms?
29. Give an example for strength reduction
30. How can the control flow be optimized?
31. Explain the graph-matching-based procedure for the reduction of jump instructions.
32. What is the function of a "preheader"?
33. How can loop invariant code be relocated?
34. For which optimization can induction variables be used?
35. What is meant by function inlining?
36. What is teal-recursion?
37. What are the most important phases of a compiler-backend?
38. Explain the typical procedure of instruction execution on a CPU.
39. Why do modern computer systems use a memory hierarchy and what are the
components of such an hierarchy?
40. Which components of memory hierarchy can be explicitly controlled?
41. What are the key performance characteristics of a processor?
42. Define the term ISA.
43. Name 5 types of target processor s.
44. What are the characteristics of a CISC processor, and how does CISC the compiler
back-end?
45. What are the characteristics of a CISC processor? How is RISC motivated?
46. Explain the performance equation for processors
47. What does the CPI value mean?
48. What is Load/Store architecture?
49. Explain the idea of instruction pipelining
50. Draw a simple 4-stage RISC pipeline.
51. What is mean by a pipeline hazard?
52. Does the compiler have to take pipeline hazards into account when generating
code?
53. Which backend phases are especially important for RISC processors?
54. What are the characteristics of a superscalar processors?
55. What is meant by out-of-order execution?
56. What is meant by instruction level parallelism?
57. Why are modern x86 processors superscalar?
58. How should a backend be designed for a superscalar processor?
59. What are DSPs used for?
60. Name 5 DSP characteristics?
61. What is meant by saturating arithmetic?
62. Why do DSPs typically have multiply-accumulate (MAC) instructions?
63. How is an AGU structured?
64. Why is the code generation for DSPs more challenging compared to a general-
purpose processor?
65. How are commands executed on a VLIW processor?
66. What is main difference between a VLIW and a superscalar processor?
67. What is a NPU?
68. Why are ASIPs used and how does an ASIP affect the compiler?
69. Draw the Tensilica Xtensa ASIP design process
70. Define register allocation and register assignment.
71. Why does a compiler need to generate spill code?
72. Explain an algorithm for register allocation for trees.
73. How can profiling information be used for register allocation?
74. What is the graph colouring problem?
75. What is the lifetime of a virtual register?
76. What is an interval graph?
77. When is a graph planar?
78. Explain the left-edge algorithm for register allocation.
79. What is an interference graph?
80. How does Briggs algorithm for global register allocation work?
81. Does the graph-colouring based global register allocation always provide optimal
results?
82. How can coalescing be used for register allocation?
83. What is safe coalescing?
84. Why can precoulored nodes appear in an interfence graph?
85. What are the requirements for the implementation of interference graphs?
86. How do adjacency matrices and adjacency lists differ?
87. What is the goal of instruction scheduling?
88. Compare global and local scheduling.
89. What is the complexity of optimal scheduling under resource constraints in general?
90. Which processor classes use static/dynamic scheduling?
91. Which boundary conditions have to be considered for scheduling?
92. How to avoid pipeline hazards through scheduling?
93. How are scheduling dependencies formally represented?
94. What is a critical path in a dependency graph?
95. Is a critical path always unique?
96. Define ASAP- and ALAP-scheduling.
97. What is the significance of ASAP/ALAP times for real schedulers?
98. Describe the list-scheduling heuristic for basic blocks.
99. What are the dependencies between scheduling and register allocation
100. For which processor classes are global scheduling methods useful?
101. Describe the trace scheduling algorithm
102. What is the basic problem with the application of global scheduling methods with
regard to the trade-off between performance and code size?
103. What ideas are the basis of the percolation scheduling?
104. What is the key idea of software pipelining?
105. For which target processor classes is software pipelining suited?
106. What is a reservation table?
107. Explain the following terms in the context of software pipelining: prologue,
epilogue, kernel
108. Explain the Aiken/Nicolau-aglorithm for software pipelining without resource
constraints.
109. Explain the iterative modulo scheduling.
110. What is the relationship between software pipelining and register allocation?
111. Explain the basic structure of an AGU.
112. By which parameters do real AGUs differ?
113. Which instructions are usually supported by AGUs?
114. What is the idea of address code optimization?
115. Define the simple offset assignment (SOA) problem.
116. Which stack frame addressing is assumed in the SOA problem?
117. How is the access graph defined for SOA?
118. What is a Hamiltonian path?
119. What is the complexity of the SOA problem?
120. Describe the modification of the Kruskal algorithm for constructing maximally
weighted Hamiltonian paths.
121. Execute the Hamiltonian path-based SOA algorithm on an example.
122. How can modify registers be optimally used?
123. Explain the basic of genetic algorithms
124. Which parameters have to be chosen appropriately for GAs?
125. Describe the GA-based method for SOA.
126. How can the GA-based SOA process be extended to GOA?
127. What is a SIMD instruction?
128. Name an example for a SIMD instruction.
129. How can SIMD instructions be used for software development?
130. Can SIMD instructions be exploited by means of tree parsing in the compiler?
131. Define the integer linear programming problem (ILP).
132. What is meant by linear programming?
133. Sketch the ILP-based method for code selection with SIMD instructions.
134. What is the difference between an orthogonal and a clustered VLIW architecture?
135. Sketch the basic structure of a clustered VLIW processor.
136. What is a copy operation?
137. What has to be considered in particular when scheduling for clustered VLIW ?
138. Explain the phase ordering problem.
139. How scheduling and cluster partitioning be coupled?
140. Explain the simulated annealing algorithm.
141. What is meant by processor architecture exploration?
142. What is a retargetable compiler?
143. Name an example for a retargetable compiler.
144. How is the machine description of the lcc compiler structured?