Design of a Hybrid Ring Oscillator at 1.5/3.

0 GHz
with Low Power Supply Sensitivity

Vivek Sharma∗ , Kapil Jainwal∗ , Abhishek Tripathi†

∗ The
LNM Institute of Information Technology, Jaipur, India
† Madhav
Institute of Technology and Science, Gwalior, India
Email:∗ sharma.vivek@lnmiit.ac.in, ∗ jainwalkapil@gmail.com, † abhishek210189@gmail.com

Abstract—In this paper a hybrid ring oscillator, with oscilla- supply noise directly to the output of the VCO due to back to
tion frequency of 1.5/3.0 GHz, is presented with reduced sensi- back connection [1].
tivity for supply variations. An analysis of oscillation frequency
variation due to static and dynamic power supply noise, is given. In this paper, a ring oscillator with hybrid delay cell
Simulation results show a static supply sensitivity of 1.06% at and negative feedback circuit is proposed in order to improve
200 mV static supply noise and a dynamic supply sensitivity of dynamic supply sensitivity. The paper is organized as follow.
2.54% (worst case) as compared to 16.55% dynamic sensitivity In Section II, a conventional CMOS inverter delay cell is
of a conventional ring oscillator at 50 mV(peak-to-peak), 10 described, followed by the proposed delay cell in Section III,
MHz sinusoidal noise signal. The design is simulated at 180 nm while simulated results are discussed in Section IV. Finally,
standard CMOS technology at different stages 3/5/7 having a conclusions are drawn in Section V.
maximum power consumption of 5.2 mW and supply voltage of
1.8 V. II. CONVENTIONAL CMOS RING OSCILLATOR
Keywords—Supply sensitivity (SS), ring oscillator(RO), negative Conventional ring oscillators (CRO) are widely designed
feedback. using delay cell as shown in Fig. 1(a). Delay of the unit cell
in the ring oscillator depends on its RC value also defined as
I. I NTRODUCTION time constant(τ ) of the cell. The oscillation frequency(fosc ) of
Voltage controlled oscillator (VCO) forms an integral part the ring oscillator can be calculated as:
of an Analog phase locked loop (APLL) as well as that of 1
fosc = , (1)
Digital-PLLs’ (DPLL). These circuits (APLL and DPLL) are 2N τ
used in high performance microprocessors, communication where N is the odd number of stages in the ring oscillator. The
systems, on-chip clock distribution, clock synchronization and product of RC(= τ ) at the output of any stage can be given
on-chip signal generation, because of wide tuning range, ease as:
of integration, and multi-phase clock generations DPLL are τ = (Cbd + CL )(rp  rn ), (2)
more preferred as compared APLL [1]. Noise deteriorates the where Cbd is body to drain capacitance, CL is the load
efficiency of any system. The major source of the noise in capacitance of the next stage, rp and rn are channel resistance
the PLL is mainly attributed to the intrinsic noise generated of PMOS and NMOS, respectively. Cbd can be written as [8]:
in the devices (1/f noise, dominant at low frequency and
Cj0
high frequency thermal noise) and the noise coupled from Cbd = Cj AD + Cjsw PD ; Cj = , (3)
the digital block of the system which in turn degrades the (1 + Vφbd
j
)m
performance of PLL [2]. Supply variation is another external
where Cj and Cjsw is junction and side-wall junction ca-
factor which introduces noise in the VCO and it affects the
pacitance. AD is the drain area, PD is the perimeter of the
oscillation frequency of ring oscillator. In passive oscillators
drain, m is junction diffusion gradient whose typical value lies
(e.g. LC-oscillator) where oscillation frequency solely depends
between 0.33 to 0.5, Vbd is body to drain potential and φj is
on passive components rather than power supply [4]. Hence,
built-in junction potential. When the supply voltage VDD is
passive oscillator have better noise rejection. On-chip realiza-
varied by ΔV , assuming ideal current source Id , the body and
tion of an inductor consumes more area as well as integration
source potential of the PMOS transistor also varies by ΔV .
of passive oscillators with other circuitry is difficult, while,
This causes variation in Cbd and in rp . rn will not vary as
ring oscillators are easily realizable and consumes lesser area.
there is no change in gate to source potential of NMOS. The
VCOs have an intrinsic tendency of positive supply change in Cbd with respect to change in power supply is:
sensitivity (SS) which can be compensated by having an
∂Cbd ∂Cbd ∂Vbd −m.Cbd
additional circuitry with negative supply sensitivity [5]. Dif- =( . )=  . (4)
ferential topologies with cross coupled structures [6] and ∂VDD ∂Vbd ∂VDD φj 1 + Vφbd
j
large decoupling capacitors help in reducing static as well
as dynamic supply sensitivity. Asymmetry of the VCO by as body of PMOS is connected to VDD , ∂V∂Vbd
DD
≈ 1. Variation
using variably controlled biasing voltages helps in reducing in the channel length resistance of PMOS is:
supply sensitivity [7]. However, conventional delay cell of ring
∂rp ∂Vbd ∂(λ.Id )−1 1 ∂Id
oscillator, as shown in Fig. 1(a), has a major drawback of = = −( 2 ). . (5)
process-voltage-temperature (PVT) variations and coupling of ∂Vbd ∂VDD ∂VDD λ.Id ∂VDD

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 VDD
∂Id ∂VSG ΔL ∂rp ∂VSG
∝ ;λ = ; ∝ , (6) CP
∂VDD ∂VDD L ∂VDD ∂VDD
where, ΔL is the channel diffusion length of PMOS, L is
the length of the channel and VSG is source to gate potential,
here ΔVSG = 0. ΔV variation in source potential will change
the drain current and thereby affect oscillation frequency. Due VDD Id
to variation in Cbd and rp with power supply, the oscillation
frequency of ring oscillator will change. Variation in fOSC is M4
M1
∂fosc 1 ∂τ fosc ∂τ
=− 2 =− . (7)
∂VDD τ ∂VDD τ ∂VDD CL
hence, the supply sensitivity function ASS can be defined in M2
terms of frequency variation with power supply can be given (a)
as:

1 ∂fosc 1 ∂Cdb
ASS = =− rp
fosc ∂VDD rp (Cdb + CL ) ∂VDD ΔV
 VDD VDD
rn ∂rp
+(Cdb + CL ) . (8) g-1
M1
(rp + rn ) ∂VDD M12 M7
M11 ds Mp
The value of ASS of conventional ring oscillator is very high
due to direct coupling of noise on oscillators’ output. A by-pass
Vd7
Ibias M8
coupling capacitor (CP ) is used to reduce the value of ASS . r n8 M4 Mn
CP couples the noise from power supply directly to the current
source, controlling the total current in the oscillator by-passing
the ring stages. A large CP is required to reduce dynamic SS, Id
which will consume more area on-chip. Due to CP , the drain M10 M9
potential of the current source varies which eventually changes RLP
the drain current. From (8), it can be concluded that supply CLP
sensitivity of oscillator decreases with decrease in the values of
∂Cbd ∂rp
factors ∂V DD
and ∂VDD then the supply sensitivity of oscillator (b)
can be reduced.
III. PROPOSED RING OSCILLATOR
Fig. 1. (a) Conventional ring oscillator (b) Proposed Ring Oscillator
A proposed ring oscillator which utilizes a new hybrid
delay cell with current source as a load (transistors M1 and
Mp ) is shown in Fig. 1(b). The output of each stage is
connected to the gate of NMOS (transistors M4 and Mn ) of
the next stage. The proposed design eliminates the need of a load transistors and thus ΔVSG ≈ 0. From (5) and (6) it can
bypass capacitor. A negative feedback is used to compensate be written as:
∂rp 1 ∂Id
the changes in supply voltage due to the static and dynamic = −( 2 ). = 0. (10)
noise. RLP and CLP are the resistance and capacitance of ∂VDD λ.Id ∂VDD
the low pass filter, respectively and any ripple in the current in (10) rp is the channel resistance of current source load
mirror circuit is attenuated by a low-pass filter connected at whereas there is no change in rn (channel resistance of NMOS)
the gate of transistor M9 . Low-pass filter will not allow any as gate to source potential is constant and supply sensitivity
change in current through M9 , due to the power supply noise. factor given in (8) reduces to
ΔV variation in supply voltage will vary the source potential  
1 ∂Cdb
of the M7 transistor. This ΔV change will appear across the ASS1 = − . (11)
(Cdb + CL ) ∂VDD
resistive divider circuit formed by M7 and M8 transistors. In
Fig. 1(b) the voltage drop across rn8 is Vd7 , using voltage hence, proposed ring oscillator (PRO) have a low supply
−1
division in a resistive divider circuit (gds and rn8 ), Vd7 can sensitivity factor (ASS1 ). Coupling of the dynamic supply
be written as: rn8 .ΔV noise with the output of the oscillator is eliminated because of
V d7 = −1 , (9) no direct path from supply to the input of the oscillator.
rn8 + gds
where gds is trans-conductance of PMOS transistor M7 , rn8 IV. SIMULATED RESULTS
is channel resistance of M8 transistor. Since gds is very small Conventional and proposed ring oscillators are designed at
compared to rn8 , total voltage drop will occur across M8 . This 1.5 and 3.0 GHz oscillation frequency with number of stages
will change the drain potential of M7 , which is connected in varying from 3 to 7. A DC voltage source varying from 0 −
diode configuration. This ΔV variation in gate potential of 200 mV is applied at the power supply to study the static
M7 will change the gate potential of all the current source supply sensitivity. Percentage change in oscillation frequency

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 TABLE I. SUMMARY AND PERFORMANCE COMPARISON OF PROPOSED RING OSCILLATOR

Process fosc fnoise Dynamic SS DC noise Static SS PN @ 1 MHZ Power VDD ftemp
(nm) (GHz) (MHz) (worst case) (dBc/Hz) (mW) (V) MHz (Worst case)
[6] 180 2.5 10 0.38 mUI/mV;normalized N/A N/A -92.83 10.1 1.8 N/A

[9] 130 4.0 N/A N/A 10 mV 0.013 (%) N/A 4 1.2 N/A
CRO
180 1.5 10 16.55/15.6/15 (%) 200 mV 1.07/0.24/0.24 (%) -78.38/-84.83/-87.10 2.0/3.65/4.36 1.8 17.92/3.14/5.04
3/5/7
CRO
180 3.0 10 15.6/14.9/14.5 (%) 200 mV 0.18/0.08/0.04 (%) -81.41/-85.42/-89.15 2.8/4.36/4.70 1.8 6.76/15.20/4.29
3/5/7
PRO
180 1.5 10 2.30/2.40/2.48 (%) 200 mV 1.06/0.23/0.23 (%) -82.60/-92.10/-94.01 2.36/4.22/4.5 1.8 7.99/6.28/7.8
3/5/7
PRO
180 3.0 10 1.46/2.35/2.54 (%) 200 mV 0.17/0.07/0.03 (%) -85.70/-86.72/-93.45 3.15/4.60/5.2 1.8 3.24/1.66/4.59
3/5/7

due to the dc noise is shown in Fig. 3(a) and (c). Static supply
sensitivity of CRO and PRO at 1.5 GHz are approximately
same as shown in Fig. 3(a) with maximum variation of 1.06%
5 and 1.07% in proposed and conventional ring oscillator. Static
Conventional
sensitivity of the oscillator at 3.0 GHz is depicted in Fig. 3(c)
Proposed
and the worst case variation is 0.18% / 0.17% in CRO and
4 PRO. A sinusoidal signal of 50 mV peak-to-peak with variable
frequency (10-100 MHz) is used as a dynamic power supply
Power (mW)

noise source. The jitter produced due to frequency variation

can be estimated as follows [6]:
Δf
Jp−p = , (12)
2 2πfnoise fosc
where Δf is the peak-to-peak amplitude of frequency variation
and fnoise is the frequency of perturbation/noise. Peak-to-
peak jitter (Jp−p ) is inversely proportional to fnoise and
fOSC as mentioned in (12). Oscillation frequency variation
0 due to dynamic change in power supply is dominant at low
3 5 7 noise frequency and at lower fosc . In a worst case scenario
for 10 MHz supply noise the percentage change in fosc is
Stages

(a)
2.3% for PRO whereas it is 16.55% for CRO at 1.5 GHz
oscillation frequency as deduced from Fig. 3(b). Whereas at
6 3.0 GHz the same is 1.46% / 15.6% as shown in Fig. 3(d).
Conventional

Proposed
Proposed design shows a significant improvement in the noise
suppression at lower noise frequency. Generally the noise due
to digital switching is less than 20 MHz however, at higher
4 noise frequency both designs shows comparable performance.
Phase noise (PN) of proposed ring oscillator at an offset of
Power (mW)

600 kHz and 1 MHz is depicted in Fig. 3(e) and (f ). From

Fig. 2(a) the power consumption of conventional and proposed
ring oscillator at 1.5 GHz is 4.36 and 4.5 mW and at 3.0
2 GHz it is 4.7 and 5.2 mW (all for 7-stages) as shown in
Fig. 2(b). Temperature sweep of simulation environment has
been carried out from −40◦ C to 100◦ C and the variation in
oscillation frequency due to temperature (ftemp ) is presented
0 in Table I. CRO has a ftemp value of 17.9 MHz in a worst
3 5 7 case at 1.5 GHz (3-stage) which is 1.19% change in fOSC
whereas PRO has a ftemp of 7.99 MHz and it is 0.05% of
Stages

(b)

Fig. 2. Comparison of conventional and proposed ring oscillator at 1) 1.5
GHz : (a) Power consumption with variable number of stages 3/5/7. 2) 3.0
GHz : (b) Power consumption with variable number of stages 3/5/7.
fOSC (1.5 GHz;3-stage). Corner analysis for the proposed
ring oscillator has been carried out and there is no significant
variation change in percentage of oscillation frequency. CRO
and PRO are simulated with different number of stages (3/5/7)
to analyze the performance of proposed design. A comparison

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 1.2 18 0.20
Proposed-3 stage Proposed-3 stage
Proposed-3 stage
Proposed-5 stage Proposed-5 stage
Proposed-5 stage

Proposed-7 stage 16
Proposed-7 stage

Conventional-3 stage
0.18 Proposed-7 stage

Conventional-3 stage

1.0 Conventional-3 stage Conventional-5 stage

Conventional-5 stage

Conventional-7 stage

0.16
Conventional-7 stage
Conventional-5 stage

14
Conventional-7 stage
Change in Oscillation Frequency (%)

Change in Oscillation Frequency (%)

Change in Oscillation Frequency (%)

0.8 0.14
12
0.12
0.6 10 0.10

8 0.08
0.4
0.06
6
0.2 0.04
4
0.02
0.0 2 0.00
0 20 40 60 80 100 120 140 160 180 200 0 10 20 30 40 50 60 70 80 90 100 110 0 20 40 60 80 100 120 140 160 180 200
Supply Noise Voltage (mV) Supply Noise Frequency (MHz) Supply Noise Voltage (mV)
(a) (b) (c)
16 -75
Proposed-3 stage
-78.34 3.0 GHz, 3 stage 1.5 GHz, 3 stage

-75
Proposed-5 stage

Proposed-7 stage 3.0 GHz, 5 stage 1.5 GHz, 5stage

14 Conventional-3 stage

Conventional-5 stage
3.0 GHz, 7 stage 1.5 GHz, 7 stage

Conventional-7 stage

-80
Change in Oscillation Frequency (%)

-75.88

12 -80 -82.60

Phase Noise (dBc/Hz)

-80.47 -85.71
Phase Noise (dBc/Hz)

10 -85 -85.05

-85
8
-86.72
-90
-90
6 -86.15
-92.10

-90.10

4 -95
-93.45
-95

2 -94.01

-100 -100
0 10 20 30 40 50 60 70 80 90 100 110 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Supply Noise Frequency (MHz) Offset Frequency (MHz) Offset Frequency (MHz)

(d) (e) (f)

Fig. 3. Comparison of conventional and proposed ring oscillator at 1) 1.5 GHz : (a)% change in fOSC with static supply noise variation (b)% change in
fOSC with dynamic supply noise variation at 3/5/7 stages. 2) 3.0 GHz : (c)% change in fOSC with static supply noise variation (d)% change in fOSC with
dynamic supply noise variation at 3/5/7 stages (e) Phase noise graph proposed ring oscillator at 3.0 GHz (f) Phase noise graph proposed ring oscillator at 1.5
GHz.

of the proposed ring oscillator and CRO along with other [3] In-Chul Hwang, Chulwoo Kim and Sung-Mo Kang, “A CMOS self-
recent work is shown in Table I. regulating VCO with low supply sensitivity,” in IEEE Journal of Solid-
State Circuits, vol. 39, no. 1, pp. 42-48, Jan. 2004.
V. C ONCLUSION [4] C. H. Ho, K. A. Jenkins, H. Ainspan, E. Ray, B. P. Linder and P. Song,
“Performance Degradation Analysis and Hot-Carrier Injection Impact
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based ring oscillator and the proposed design has been sim- Transactions on Electron Devices, vol. 62, no. 7, pp. 2148-2154, July
ulated. A negative feedback hybrid delay cell is proposed. 2015.
PRO shows an improvement in supply sensitivity, as the static [5] T. Wu, K. Mayaram and U. K. Moon, “An On-chip Calibration Technique
supply sensitivity variation in both the designs are robust with for Reducing Supply Voltage Sensitivity in Ring Oscillators,” in IEEE
an advantage in the PRO. Phase noise of the proposed design Journal of Solid-State Circuits, vol. 42, no. 4, pp. 775-783, April 2007.
at 1 MHz (7 stage, 1.5 GHz) is −94.01 dBc/Hz which is 6.91 [6] X. Gui and M. M. Green, “Design of CML Ring Oscillators With Low
Supply Sensitivity,” in IEEE Transactions on Circuits and Systems I:
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Supply and Control Voltages,” in IEEE Journal of Solid-State Circuits,
ACKNOWLEDGMENT vol. 44, no. 9, pp. 2488-2495, Sept. 2009.
The authors thank the Department of Electronics and Com- [8] Y. P. Tsividis, Operation and Modelling of the MOS Transistor. New
York: McGraw-Hill, 1999.
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Technology, Jaipur, India, to support this work. [9] Y. S. Park and W. Y. Choi, “On-Chip Compensation of Ring VCO Oscil-
lation Frequency Changes Due to Supply Noise and Process Variation,”
in IEEE Transactions on Circuits and Systems II: Express Briefs, vol.
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