The Design of a Low-Power High-Speed Current Comparator
in 0.35-μm CMOS Technology
Soheil Ziabakhsh1, Hosein Alavi-Rad1, Mohammad Alavi-Rad2, Mohammad Mortazavi3
1
Electrical Engineering, University of Guilan, Faculty of Engineering, Rasht, Iran
2
Electrical Engineering Department, Sharif University of Technology, Tehran, Iran
3
Engineering & Science Department, Sharif University of Technology, International Campus, Kish, Iran
soheil.ziabakhsh@gmail.com, alavi.itmc@gmail.com, alavirad@ee.sharif.edu, mortazavi@sharif.ir
Abstract
A novel low power with high performance low current
comparator is proposed in this paper which comprises of low
input impedance using a simple biasing method. It aimed for
low power consumption and high speed designs compared
with other high speed designs. The simulation results from
HSPICE demonstrate the propagation delay is about 0.7 ns
and the average power consumption is 130 μW for 100 nA
input current at supply voltage of 1.8 V using 0.35 micron
CMOS technology.
Keywords
Current Comparator, Propagation Delay, Instantaneous
Power, Positive Feedback, Signal Processing
1. Introduction
Current comparators are important building blocks within
many analogue circuit designs. In particular, they are used for
front-end signal processing applications and increasingly
within neuromorphic electronic systems [1,2]. Low voltage
and low power application demands confront voltage mode
IC designs, for there is less dynamic available under low
power supply condition. While the circuit implemented in
current mode technique occupies small area, consumes less
power dissipation and achieves more dynamic range and high
operation speed. Thus the current mode circuit design
methodology receives increasing wide attention in the recent
years [3,4].
Moreover, many sensors in SoC such as temperature
sensors, photo sensors provide current signal. In these
applications and high speed data converters, where the
function of comparison is a limiting component for accuracy,
noise and power consumption reasons, the introduction of
current mode solutions is highly desirable. The current
comparison process is injecting one or two current flowing
into the comparator and distinguishing the current (or the
difference of two currents) is positive or negative. The output
voltage generated by the output current is used conveniently
to indicate the result of the comparison.
The comparison process is relatively simple, but the
implementation of the current comparator is becoming more
complex. Low input impedance, which is required by current
mode circuits, should be considered first. Secondly, a quick
time response is demanded by the current comparator. The
main limitation to the time response usually comes from the
initial balance of the output branches that often leads to the
triode region some output transistors. Finally, the precision of
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comparator designs are playing an important role in the
design requirements, and it depends on the offset caused by
the mismatch of transistors. In the recent years, there have
been many good implementations reported [5,6]. However,
many of the proposed implementations had only emphasized
on one or several aspects at the cost of deterioration in other
characteristics. Obviously there is a requirement to transform
the input current to a large voltage signal. Thus to design a
high speed current comparator, one has to consider the
voltage swing carefully since it directly determines the
propagation delay.
Conventionally, most reported current comparators [7, 8]
are based on the concept shown as a block diagram in Fig 1,
where the input current signal is converted to the voltage Vin
and V1 by the transimpedance stage comprising inverter
amplifier A1 and voltage buffer A2. The resulting voltage V1
is then amplified by the latter high gain inverter amplifier A3
to produce output logic voltage. There exist parasitic
capacitors at all nodes.
Ideally for high speed comparators, the signal swing at
V1 should be maintained as small as possible and situated
exactly around the inverter threshold voltage of the inverter
A3. However, the reported works were relating to improve
the lowest input current acquiring ability by arranging a
proper biasing to turn on the MOSFETs of the buffer A2 all
the time.
Most of them utilized diode connected MOSFETs as a
level shifter to create VGS of the buffer MOSFETs. It is seen
that although the transimpedance stage is formed in a
negative feedback loop, a much larger loop gain has not been
exploited to keep the signal Vin and V1 as low as possible.
Moreover with a larger loop gain, the input impedance at
node Vin could be much lower and receive a much smaller
input current in the range of Pico-Amps. The dead zone term
which is the smallest input current range to which
comparators are insensitive is then minimized. However, a
drawback of having the small voltage swing at V1 is that the
gain of the latter inverter amplifier must be necessarily high.
Hence it yields to higher power consumption. Obviously,
there is a conflict that if the speed as a result of a small
voltage swing of the tranresistance stage is desired, a very
high gain of the latter inverter amplifier will be necessary to
provide the rail to rail output swing.
107 10th Int’l Symposium on Quality Electronic Design
Figure 1: Current Comparator Concept.
2. Preview Low-Power High-Speed Current
Comparators
Recently, a number of current comparator circuits have
been reported [9,10]. The current comparator reported in [9]
is perhaps the first current comparator which possesses lower
input impedance than previous circuits. In the circuit shown
in Fig 2, M1 and M2 form a class B voltage buffer; and M3-
M6 form two inverting amplifiers. Iin is the input current,
which is the difference between the signal and the reference
currents. The circuit has three modes of operation. When Iin
is positive, V1 is pulled high.
This is amplified by M3 and M4, causing V2 to go low.
VGS1 and VGS2 are negative, turning M1 off and M2 on. In
this state, V1 is a low impedance node, because Iin is
supplied by M2. When Iin changes its sign, there is
insufficient gate drive for the buffer to supply Iin, thus V1 is
temporarily a high impedance node. When Iin is negative, V1
is pulled low and V2 is pulled high, turning M1 off and M2
on; again V1 is a low impedance node. The width of this dead
band region in the transfer characteristic of the buffer is
determined by the threshold voltage of M1 and M2, and the
response time of the comparator significantly increases as the
input current decreases. The current comparator reported in
[10] reduced this dead band by changing the biasing scheme
of M1 and M2 from class B to class AB operation. This
results in smaller voltage swings at V1 and V2 and hence
faster response. However, this comparator requires a complex
biasing circuit in order to reduce the dead band, and increase
the power consumption.
Therefore, the comparators proposed in [9,10] use
nonlinear positive feedback to enhance the response time,
and it can be said that improvement is achieved at the
expense of sensitivity and power consumption. The feedback
operation of these circuits does not allow the input node to
slew from rail to rail. Instead it maintains the operating
voltage of the comparator node midway between the
threshold voltages of the PMOS and NMOS transistors M1
and M2. This allows high speed operation but consumes high
current through transistors M1-M4 as quiescent non-zero DC
power consumption.
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Figure 2: The Original Current Comparator [9].
One of most significant hurdle is to minimize the dead
zone. Fig. 3 shows the new circuit which employs one diode-
connected NMOS transistor instead of two to provide the
voltage drop between the gates of M1 and M2 [11]. The
advantages are not only saving one transistor but also
reducing the channel width. Here, the (VGS - VTH) value of
M4 is proportional to the square root of current through M3,
M4 and M5.
Since the input current (Iin) is very small, the variations
of current and (VGS - VTH) of M4 are also very small. The
input impedance is about 1/ (gm1 + gm2), which is much
smaller than that of Fig 1 due to higher VGS . The drain and
source of M4 are connected to the gates of M6 and M7,
respectively. The purpose is to provide higher current for
charging and discharging the gates of M8 and M9, and thus
enhance the speed. In order to reduce the current through M6
and M7, the channel lengths were increased to save the
power consumption. M8-M11 are a pair of inverters to
amplify the output signal.
Figure 3: The Current Comparator Proposed in [11].
The problem of using inverters as amplifiers is sensitivity
of processes. Since the process may go to the SS, FS, SF and
FF comers, the output of M6 and M7 may not be at the right
threshold voltage of the inverter M8/M9. Here, S and F stand
for slow and fast, respectively. The first character is for
NMOS transistors, while the second one is for PMOS. The
two transistors Mn and Mp are used to adjust the inverter
threshold voltage using different voltage values of Vn and
Vp. For the typical case (TT), Vn is equal to VDD and Vp is
grounded. A schematic of the positive feedback system
proposed in [12] is shown in Fig 4.
 Positive feedback operates at the output nodes of the were adjusted. The dead-band region created by M7 and M8
inverters M5/M6 and M7/M8, respectively. In the pre- is minimized by setting the lengths and widths of both
decision state transistors M2 and M3 are closed and transistors to a minimum. M9-M12 are a pair of CMOS
transistors M1 and M4 are open. As the voltage on the inverters to output a rail-to-rail resulting signal with a
comparator node is affected by input current, so the inverter negligible delay time.
M5/M6 begins to switch. As this slews to either rail the
transistors M2 or M3 are switched open, and then with a
delay of about 10 ns the transistors M1 or M4, respectively,
are switched closed. This latched feedback dumps enough
charge on the comparator node to significantly speed the
decision process, particularly at low current inputs.

Figure 5: . New Current Comparator.

Figure 4: Current Comparator Proposed in [12].
One disadvantage of this system is that the input node
slews from rail to rail and this can slow the operation of the
comparator. However, this is still a significant speed
improvement over a simple inverter comparator.
3. Proposed Low-Power High Speed Current
Comparator Architecture
The proposed high speed, low DC offset, and low-power
consumption CMOS current comparator is shown in Fig. 5.
The current comparator consists of a current amplifier (M1-
M4 and Rp), a Class B output stage (M7/M8), and three
CMOS inverters (M5/M6, M9-M12). The proposed design is
a modified version of the simple current comparator in [9],
with an added current amplifier and an extra pair of inverters
compared to the original design. The current amplifier
enhances the degrading response of the current comparator
for small input currents. It consists of two current mirrors. To
minimize power consumption, the widths of M1-M4 were
kept to a minimum while the lengths were adjusted to achieve
a desired current gain.
After matching the currents through M1 and M2, the
currents were matched as well through M3 and M4. An
additional Rp was added to minimize the DC current offset.
Dimensions of M1-M4 were chosen while taking into
consideration the inverse relationship between the gain and
the 3-dB frequency of the current amplifier. M5 and M6 are
in the positive feedback loop and serve to invert the incoming
signal. In order to reduce parasitic capacitances while
allowing the inverter to draw more current for a faster charge,
the lengths of M5 and M6 were minimized and their widths
4. Experimental Results
With HSPICE, the new current comparator was simulated
using TSMC 0.35 μm CMOS technology parameters and
with 1.8 V power supply. Fig. 6 shows the input square-wave
current which changes between -100 nA and 100 nA, as well
as the transient waveform of output voltage of the proposed
comparator and other three comparators discussed in the
previous section. Incidentally, the rise and fall time delays of
the new comparator are both 0.7 ns and the average power
consumption is 130 μW.
Obviously, the solid line from the new circuit switches
faster than the other cases. To our knowledge, the simulation
results of the proposed current comparator are better than
existing comparators to date. When the circuit in [9] was
simulated, the delay was 1.7 ns for a 5 μA wave and 2.5 ns
for a 1 μA wave. A major problem of this comparator is its
response to low inputs. A large delay for small signals can
jeopardize the performance of the current comparator.
Instantaneous power of the proposed comparator is shown in
Fig. 7.
Fig 8 and Fig 9 compare the propagation delay and the
average power of different comparators. In these figures, the
labels “1”, “2”, “3” and “4” represent three different
comparators shown in figures 2, 3, 4 and the new comparator
in Fig 5, respectively. The propagation delay is defined as the
time difference between the output and the input signals
when they reach the 50% of their total variations.
As it can be seen from Fig. 8, the delay time of the new
comparator is lower than comparators in [9] and [12] for all
ranges of input current and is only slightly higher than
comparator in [11] for input current lower than 10 nA. But,
the power dissipation of the new comparator is very low in
comparison with others. So for the power delay product, the
new comparator is superior to the other circuits, especially at
low input current. The component values of the new
comparator and other comparators discussed in the previous
section are presented in Table 1.
Performance comparisons among reported circuits are
listed in Table 2.

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 Figure 8: Delay Time Comparison Due to Input Current

Figure 9: Power Consumption Comparison Due to Input

Current.

5. Conclusion
We have proposed an improved current comparator for
Figure 6: Comparison of Waveform Responses of the Input high speed and low-power applications. Simulation results
Current and Output Voltage. done by HSPICE and by using TSMC 0.35 μm CMOS
technology with 1.8 V supply voltage show that in the
proposed comparator, the power-delay product has been
significantly reduced at low input current level in comparison
with other reported comparators.
Since for many applications, the response time of
comparator at low current level limits the overall speed of the
system, this circuit will allow a significant speed
improvement in system level designing. Also the low power
dissipation characteristic of it is quite suitable for portable
and battery supplied electronics devices.

Figure 7: Instantaneous Power of the Proposed Comparator.

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 Table 1: The Channel Length and Width of Transistors Parameters Used for Current Comparators.
Träf [9] Lin [11] Banks [12] Our Approach
Name W(μm) L(μm) Name W(μm) L(μm) Name W(μm) L(μm) Name W(μm) L (μm)
M1 9 2 M1 0.5 0.35 M1 2 2 M1 0.36 0.48
M2 3 2 M2 1.2 0.35 M2 2 2 M2 0.36 2.04
M3 9 2 M3 0.5 0.6 M3 2 2 M3 0.36 0.24
M4 3 2 M4 0.5 0.7 M4 2 2 M4 0.36 0.6
M5 9 2 M5 2.5 1 M5 2 2 M5 1.08 0.35
M6 3 2 M6 0.6 1 M6 2 2 M6 0.36 0.35
M7 1.8 1 M7 2 2 M7 0.36 0.35
M8 0.8 0.35 M8 2 2 M8 0.36 0.35
M9 3.7 0.35 M9 1.08 0.35
M10 0.9 0.35 M10 0.36 0.35
M11 3.5 0.35 M11 1.08 0.35
Mn 1.9 0.35 M12 0.38 0.48
Mp 5 0.35

Table 2: Table Performance Comparisons Used for Current Comparators.

Träf [9] Lin [11] Banks [12] Our Approach
Year 1992 2000 2008 2009
Power supply (V) 3 3 3 1.8
Technology (μm) 2 0.35 0.35 0.35
Minimum Input Current
500 50 10 10
Amplitude (nA)
Propagation delay (nsec) 10 2.8 14 0.7
Power dissipation (μW) 390 580 300 130
(at 10 nA) (at 100 nA) (at 10 nA) (at 10 nA)

[7] H. Lin, J. H. Huang, and S. C. Wong, “A simple high-

6. References
speed low current comparator,” IEEE Trans. Circuit
[1] D. J. Banks, P. Degenaar, and C. Toumazou, “A Colour
Syst., pp. 713-716, 2000.
and Intensity Contrast Segmentation Algorithm for
[8] L. Ravezzi, D. Stoppaa, and G. F. Dalta Betta, “Simple
Current Mode Pixel Distributed Edge Detection,”
High Speed CMOS Current Comparator,” Electronics
Eurosensors XIX, Barcelona, 2005.
Letters, vol. 33, no. 22, pp. 1829-1830, 1997.
[2] D. J. Banks, P. Degenaar, and C. Toumazou,
[9] H. Träff, “Novel Approach to High Speed CMOS
“Distributed Current-Mode Image Processing Filters,”
Current Comparators,” Electronics Letters, vol. 28, no.
Electronics Letters, 41, pp. 1201–1202, 2005.
3, pp. 310-312, 1992.
[3] H. Hassan, M. Anis, and M. Elmasry, “MOS Current
[10] A. T. K. TANG and C. TOUMAZOU, “High
Mode Circuits: Analysis, Design, and Variability,”
Performance CMOS Current Comparator,” Electronics
IEEE Transactions on VLSI, vol. 13, no. 8, pp. 885-
Letters, 30, (l), pp. 5-6, 1994.
898, Aug. 2005.
[11] H. Lin, J. H. Huang, and S. C. Wong, “A Simple High-
[4] G. K. Balachandran and P. E. Allen, “Switched-
Speed Low Current Comparator,” IEEE International
Current Circuits in Digital CMOS Technology with
Symposium on Circuits and Systems (ISCAS), Geneva,
Low Charge-Injection Errors,” IEEE Journal of Solid-
Switzerland, May 2000.
State Circuits, vol. 37, no. 10, pp. 1271-1281, Oct.
[12] D. Banks and C. Toumazou, “Low-Power High-Speed
2002.
Current Comparator Design,” 31st Electronics Letters,
[5] V. Boonsobhak, A. Worapishet, and J. B. Hughes,
vol. 44, no. 3, January 2008.
“Reduced Kickback Regenerative Current Comparator
for High-Speed Switched-Current Pipeline Analogue-
To-Digital Converters”, Electronics Letters, vol. 39, no.
1, pp. 4-5, Jan. 2003.
[6] G. Palmisano and G. Palumbo, “Offset-Compensated
Low Power Current Comparator,” Electronics Letters,
vol. 30, no. 20, pp. 1637-1639, Sept. 1994.

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